XC95216-15PQ160C - Xilinx - Datasheet.Support

DS063 (v5.5) June 25, 2007 www.xilinx.com 1

Product Specification

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

Features

• High-performance

- 5 ns pin-to-pin logic delays on all pins

-f

CNT to 125 MHz

• Large density range

- 36 to 288 macrocells with 800 to 6,400 usable

gates

• 5V in-system prog rammable

- Endurance of 10,000 program/erase cycles

- Program/erase over full commercial voltage and

temperature range

• Enhanced pin-locking architecture

• Flexible 36V18 Function Block

- 90 product terms drive any or all of 18 macrocells

within Function Block

- Global and product term clocks, output enables,

set and reset signals

- Extensive IEEE Std 1149.1 boundary-scan (JTAG)

support

- Programmable power reduction mode in each

macrocell

- Slew rate control on individual outputs

- User programmable ground pin capability

- Extended pattern security features for design

protection

- High-drive 24 mA outputs

- 3.3V or 5V I/O capability

- Advanced CMOS 5V FastFLASH™ technology

- Supports parallel programming of multiple XC9500

devices

Family Overview

The XC9500 CPLD family provides advanced in-system

programming and test capabilities for high performance,

general purpose logic integration. All devices are in-system

programmable for a minimum of 10,000 program/erase

cycles. Ex ten sive IE EE 1149.1 (JTAG) bou ndary-scan s up-

port is also included on all family members.

As shown in Table 1, logic density of the XC9500 devices

ranges from 800 to over 6,400 usable g ates wi th 36 t o 288

regist ers, respec tively. Multi ple package op tions and a sso-

ciated I/O capacity are shown in Table 2. The XC9500 fam-

ily is fully pin-compatible allowing easy design migration

across multiple density options in a given package footprint.

The XC9500 architectural features address the require-

ments of in-system programmability. Enhanced pin-locking

capability avoids costly board rework. An expanded JTAG

instruction set allows version control of programming pat-

terns and in-system debugging. In-system programming

throughout the full device operating range and a minimum

of 10,000 program/erase cycles provide worry-free recon-

figurations and system field upgrades.

Adva nced sys tem featur es includ e output s lew rate control

and user-programmable ground pins to help reduce system

noise. I /Os may be c onfig ured for 3.3V or 5 V opera tion. A ll

outputs provide 24 mA drive.

XC9500 In-System Programmable

CPLD Family

DS063 (v5.5 ) June 25, 2007 00Product Specification

Table 1: XC95 00 Devic e Family

XC9536 XC9572 XC95108 XC95144 XC95216 XC95288

Macrocells 36 72 108 144 216 288

Usable Gates 800 1,600 2,400 3,200 4,800 6,400

Registers 36 72 108 144 216 288

TPD (ns) 5 7.5 7.5 7.5 10 15

TSU (ns) 3.5 4.5 4.5 4.5 6.0 8.0

TCO (ns) 4.0 4.5 4.5 4.5 6.0 8.0

fCNT (MHz)(1) 100 125 125 125 111.1 92.2

fSYSTEM (MHz)(2) 100 83.3 83.3 83.3 66.7 56.6

1. fCNT = Operating frequency for 16-bit counters.

2. fSYSTEM = Internal operating frequency for general purpose system designs spanning multiple FBs.

XC9500 In-System Programmable CPLD Family

2www.xilinx.com DS063 (v5.5) June 25, 2007

Product Specification

Architecture Description

Each XC950 0 device is a subsys tem consisting of mu ltiple

Function B lock s (FBs) and I/O B lock s (IOB s) fully inter con-

nected by the Fast CONNECT™ switch matrix. The IOB

provides buffering for device inputs and outputs. Each FB

provides programmable logic capability with 36 inputs and

18 outpu ts. The Fast CO NNECT swit ch matrix conne cts all

FB outputs and input signals to the FB inputs. For each FB,

12 to 18 outputs (depending on package pin-count) and

Table 2: Available Packages and Device I/O Pins (not including dedicated JTAG pins)

XC9536 XC9572 XC95108 XC95144 XC95216 XC95288

44-Pin VQFP 34-----

44-Pin PLCC 34 34 - - - -

48-Pin CSP 34-----

84-Pin PLCC -6969---

100-P in TQFP - 72 81 81 - -

100-P in PQF P - 72 81 81 - -

160-P in PQF P - - 108 133 133 -

208-P in HQFP - - - - 166 168

352-P in BGA - - - - 166(2) 192

1. Most packages available in Pb-Free option. See individual data sheets for more details.

2. 352-pin BGA package is being discontinued for the XC95216. See XCN07010 for details.

XC9500 In-System Programmable CPLD Family

DS063 (v5.5) June 25, 2007 www.xilinx.com 3

Product Specification

associ ated outp ut enabl e sign als driv e direc tly to the IOBs .

See Figure 1.

Function Block

Each Function Block, as shown in Figure 2, is comprised of

18 independent macrocells, each capable of implementing

a combinatorial or registered function. The FB also receives

global clock, output enable, and set/reset signals. The FB

generate s 18 o utputs that driv e the Fa st CONNECT s witc h

matrix. These 18 outputs and their corresponding output

enable signals also drive the IOB.

Logic within the FB is implemented using a sum-of-products

representation. Thirty-six inputs provide 72 true and com-

plement signals into the programmable AND-array to form

90 product terms. Any number of these product terms, up to

the 90 avai la bl e, c an be a ll oca ted to ea ch macr ocel l by th e

product term allocator.

Each FB (except for the XC9536) supports local feedback

paths that allow any number of FB out puts to drive into its

own programmable AND-array without going outside the

FB. These paths are used for creating very fast counters

and state ma chines wher e all state registe rs are within th e

same FB.

Figure 1: XC9500 Architecture

Note: Function block outputs (indicated by the bold lines) drive the I/O blocks directly.

In-System Programming Controller

JTAG

Controller

I/O

Blocks

Function

Block 1

Macrocells

1 to 18

Macrocells

1 to 18

Macrocells

1 to 18

Macrocells

1 to 18

JTAG Port

I/O/GTS

I/O/GSR

I/O/GCK

I/O

2 or 4

I/O

DS063_01_110501

Function

Block 2

Function

Block 3

Function

Block N

Fast CONNECT II Switch Matrix

XC9500 In-System Programmable CPLD Family

4www.xilinx.com DS063 (v5.5) June 25, 2007

Product Specification

Figure 2: XC9500 Function Block

Macrocell 18

Macrocell 1

Programmable

AND-Array

Product

Term

Allocators

From

Fast CONNECT II

Switch Matrix

DS063_02_110501

To Fast CONNECT II

Switch Matrix

To I/O Blocks

OUT

Global

Set/Reset

PTOE

Global

Clocks

XC9500 In-System Programmable CPLD Family

DS063 (v5.5) June 25, 2007 www.xilinx.com 5

Product Specification

Macrocell

Each XC9500 m acroce ll may be individ ually c onfigur ed for

a combinatorial or registered function. The macrocell and

associated FB logic is shown in Figure 3.

Five direc t product terms from the AND-array are availabl e

for use as primary data inputs (to the OR and XOR gates) to

implement combinatorial functions, or as control inputs

including clock, set/reset, and output enable. The product

term allocator associated with each macrocell selects how

the five direct terms are used.

The macrocell register can be configured as a D-type or

T-type flip-flop, or it may be bypassed for combinatorial

operation. Each register supports both asynchronous set

and reset operations. During power-up, all user registers

are initi aliz ed to the user -d efined pre lo ad state (defa ul t to 0

if unspecified).

Figure 3: XC9500 Macrocell Within Function Block

DS063_03_110501

Fast CONNECTII

Switch Matrix

Additional

Product

Terms

(from other

macrocells)

Global

Set/Reset

Global

Clocks

Additional

Product

Terms

(from other

macrocells)

I/O Blocks

OUT

PTOE

D/T Q

Product

Term

Allocator

Product Term Set

Product Term Clock

Product Term Reset

Product Term OE

XC9500 In-System Programmable CPLD Family

6www.xilinx.com DS063 (v5.5) June 25, 2007

Product Specification

All global control signals are available to each individual

macrocell, including clock, set/reset, and output enable sig-

nals. As shown in Figure 4, the macrocell register clock

originates from either of three global clocks or a product

term clock. Both true and complement polarities of a GCK

pin can be use d wi thin the d ev ice. A GSR in put i s a lso pr o-

vided to allow user registers to be set to a user-defined

state.

Figure 4: Macrocell Clock and Set/Reset Capability

D/T

Macrocell

DS063_04_110501

I/O/GSR

Product Term Set

Product Term Clock

Product Term Reset

Global Set/Reset

Global Clock 1

Global Clock 2

Global Clock 3

I/O/GCK3

I/O/GCK2

I/O/GCK1

XC9500 In-System Programmable CPLD Family

DS063 (v5.5) June 25, 2007 www.xilinx.com 7

Product Specification

Product Term Allocator

The product term allocator controls how the five direct prod-

uct term s are as sign ed to ea ch mac rocel l. For e xampl e, all

five direct terms can drive the OR function as shown in

Figure 5.

The product term allocator can re-assign other product

terms within the FB to increase the logic capacity of a mac-

rocell beyond five direct terms. Any macrocell requiring

additional product terms can access uncommitted product

terms in other macrocells within the FB. Up to 15 product

terms can be available to a single macrocell with only a

small incremental delay of TPTA, as shown in Figure 6.

Note that the incremental delay affects only the product

terms in other macrocells. The timing of the direct product

terms is not changed.

Figure 5: Macrocell Logic Using Direct Product Term

Product Term

Allocator

Macrocell

Product Term

Logic

DS063_05_110501

Figure 6: Product Term Allocation With 15 Product

Terms

Macrocell Logic

With 15

Product Terms

Product Term

Allocator

Product Term

Allocator

DS063_06_110501

Product Term

Allocator

XC9500 In-System Programmable CPLD Family

8www.xilinx.com DS063 (v5.5) June 25, 2007

Product Specification

The product term allocator can re-assign product terms

from any macrocell within the FB by combining partial sums

of produc ts over se veral macroc ells, as shown in Figure 7.

In this e xam pl e, th e i nc remen tal del ay i s only 2*TPTA. All 9 0

product terms are available to any macrocell, with a maxi-

mum incremental delay of 8*TPTA.

Figure 7: Product Term Allocation Over Several

Macrocells

Macrocell Logic

With 18

Product Terms

Macrocell Logic

With 2

Product Terms

Product Term

Allocator

Product Term

Allocator

DS063_07 _110501

Product Term

Allocator

Product Term

Allocator

XC9500 In-System Programmable CPLD Family

DS063 (v5.5) June 25, 2007 www.xilinx.com 9

Product Specification

The internal logic of the product term allocator is shown in

Figure 8.

Figure 8: Product Term Allocator Logic

D/T Q

From Upper

Macrocell

To Upper

Macrocell

Product Term Set

Product Term Clock

Product Term Reset

Global Set/Reset

Global Clocks

Product Term OE

Product Term

Allocator

To Lower

Macrocell

From Lower

Macrocell

DS063_08_110501

XC9500 In-System Programmable CPLD Family

10 www.xilinx.com DS063 (v5.5) June 25, 2007

Product Specification

Fast CONNECT Switch Matrix

The Fast CONNECT switch m atrix connects signals to the

FB inputs, as shown in Figure 9. All IOB outputs (corre-

sponding to user pin inputs) and all FB outputs drive the

Fast CONNECT matrix. Any of these (up to a FB fan-in limit

of 36) may be selected, through user programming, to drive

each FB with a uniform delay.

The Fast CONNECT sw itch matrix is c apable of combining

multiple internal connections into a single wired-AND output

before driving the destination FB. This provides additional

logic capability and increases the effective logic fan-in of the

destination FB without any additional timing delay. This

capability is available for internal connections originating

from FB outputs only. It is automatically invoked by the

develop men t software wher e appl icab le .

Figure 9: Fast CONNECT Switch Matrix

DS063_09_110501

Function Block

Fast CONNECT

Switch Matrix

(36)

I/O

Function Block

Wired-AND

Capability

I/O Block

(36)

I/O

D/T Q

XC9500 In-System Programmable CPLD Family

DS063 (v5.5) June 25, 2007 www.xilinx.com 11

Product Specification

I/O Block

The I/O Block (IOB) interfaces between the internal logic

and the device user I/O pins. Each IOB includes an input

buffer, output driver, output enable selection multiplexer,

and user programmable ground control. See Figure 10 for

details.

The input buffer is compatible with standard 5V CMOS, 5V

TTL, and 3. 3V signal levels. The inp ut buf fer uses th e internal

5V voltage supply (VCCINT) to ensure th at the input thresh-

olds are constant and do not vary with the VCCIO voltage.

The output enable may be generated from one of four

options: a product term signal from the macrocell, any of the

global O E signals, always [1], or always [0]. There a re two

global output enables for devices with up to 144 macrocells,

and four global output enables for the rest of the devices.

Both polarities of any of the global 3-state control (GTS)

pins may be used within the device..

Figure 10: I/O Block and Output Enable Capability

I/O Block

Macrocell

DS063_10_092203

Product Term OE PTOE

Switch Matrix

OUT

(Inversion in

AND-array)

Global OE 1

To other

Macrocells

Slew Rate

Control

Global OE 2

Available in

XC95216

and XC95288

Global OE 3

Global OE 4

I/O/GTS1

I/O

I/O/GTS2

I/O/GTS3

I/O/GTS4

To Fast CONNECT

User-

Programmable

Ground

Pull-up

Resistor*

VCCIO

XC9500 In-System Programmable CPLD Family

12 www.xilinx.com DS063 (v5.5) June 25, 2007

Product Specification

Each output has independent slew rate control. Output

edge rates may be slowed down to reduce system noise

(with an additional time delay of TSLEW) through program-

ming. See Figure 11.

Each IOB provides user programmable ground pin capabil-

ity . This allows device I/O pins to be configured as additional

ground pins. By tying strategically located programmable

ground pins to the external ground connection, system

noise generated from large numbers of simultaneous

switching outputs may be reduced.

A control pull-up resistor (typically 10K ohms) is attached to

each dev ice I/O pin to p revent th em from floating wh en the

device is not in normal user operation. This resistor is active

during devic e programming mod e and sy stem power-up. It

is also activ ate d for an eras ed dev i ce. The resis to r is deac -

tivated during normal operation.

The output driver is capable of supplying 24 mA output

drive. A ll ou tput driver s i n th e de vi ce may be co nfi gur ed for

either 5V TTL levels or 3.3V levels by connecting the device

output volta ge supply (VCCIO) to a 5V or 3. 3V voltage sup-

ply. Figure 12 shows how the X C9500 devic e can be u sed

in 5V only and mixed 3.3V/5V systems.

Pin-Locking Capability

The capability to lock the user defined pin assignments dur-

ing design changes depends on the ability of the architec-

ture to adapt to unex pected cha nge s. T he X C950 0 devic es

have architectural features that enhance the ability to

accept design changes while maintaining the same pinout.

The XC9500 architecture pr ovides maximum routing within

the Fast CONNECT switch matrix, and incorporates a flexi-

ble Function Block that allows block-wide allocation of avail-

able product terms. This provides a high level of confidence

of maintaining both input and output pin assignments for

unexp ected des ig n chan ges .

For extensive design changes requiring higher logic capac-

ity than is available in the initially chosen device, the new

design may be able to fit into a larger pin-compatible device

using th e same pin assignments. Th e same board may be

used with a higher density device without the expense of

board rework

Figure 11: Output slew-Rate for (a) Rising and (b) Falling Outputs

Figure 12: XC9500 Devices in (a) 5V Systems and (b) Mixed 5V/3.3V Systems

Time

1.5V

Standard

Output

Voltage

(a)

Slew-Rate Limited

Time

Output

Voltage

(b)

Standard

Slew-Rate Limited

SLEW

1.5V

DS063_11_110501

IN OUT

GND

(b)

3.3V

XC9500

CPLD

CCINT

CCIO

3.3V

3.6V

3.3V

DS063_12_110501

3.3V

5V TTL or

5V CMOS or

IN OUT

GND

(a)

5V TTL

XC9500

CPLD

CCINT

CCIO

–4V

3.6V

3.3V

5V TTL or

5V CMOS or

XC9500 In-System Programmable CPLD Family

DS063 (v5.5) June 25, 2007 www.xilinx.com 13

Product Specification

In-System Programming

XC9500 dev ic es are pr og ramm ed i n- sys tem v ia a standar d

4-pin JTAG protocol, as shown in Figure 13. In-system pro-

gramming offers quick and efficient design iterations and

eliminates package handling. The Xilinx development sys-

tem provides the programming data sequence using a Xilinx

download cable, a third-party JTAG development system,

JTAG-compatible board tester, or a simple microprocessor

interface that emulates the JTAG instruction sequence.

All I/Os are 3-stated and pulled high by the IOB resistors

during in-system programming. If a particular signal must

remain Low during this time, then a pulldown resistor may

be added to the pin.

External Programming

XC9500 devices can also be programmed by the Xilinx

HW130 devi ce pro gramm er as well as third-party pr ogram-

mers. This provides the added flexibility of using pre-pro-

grammed d evices during m anufacturing, wi th an in-system

programmable option for future enhancements.

Endurance

All XC9 500 CPLDs provid e a minimum en durance level of

10,000 in-system program/erase cycles. Each device meets

all functional, performance, and data retention specifica-

tions within this endurance limit.

IEEE 1149.1 Boundary-Scan (JTAG)

XC9500 devices fully support IEEE 1149.1 boundary-scan

(JTAG). EXTEST, SAMPLE/PRELOAD, BYPASS, USER-

CODE, INTEST, IDCODE, and HIGHZ instructions are sup-

ported in each device. For ISP operations, five additional

instructions are added; the ISPEN, FERASE, FPGM, FVFY,

and ISPEX instructions are fully compliant extensions of the

1149.1 instruction set.

The TMS and TCK pins have dedicated pull-up resistors as

specified by the IEEE 1149.1 standard.

Boundary Scan Description Language (BSDL) files for the

XC9500 are included in the development system and are

available on the Xilinx FTP site.

Design Security

XC9500 devices incorporate advanced data security fea-

tures which fully protect the programming data against

unauthorized reading or inadvertent device erasure/repro-

gramming. Table 3 shows the four different security settings

available.

The read sec urity bits ca n be se t by the user to prev ent the

internal programming pattern from being read or copied.

When set, they also inhibit further program operations but

allow device erase. Erasing the entire device is the only way

to reset the read security bit.

The write security bits provide added protection against

accidental device erasure or reprogramming when the

JTAG pins are subject to noise, such as during system

power-up. Once set, the write-protection may be deacti-

vated when the device needs to be reprogrammed with a

valid pattern.

Table 3: Data Security Options

Read Security

Default Set

Write Security

Default Read Allowed

Program/Erase

Allowed

Read Inhibited

Program Inhibited

Erase Allowed

Set Read Allowed

Program/Erase

Inhibited

Read Inhibited

Program/Erase

Inhibited

XC9500 In-System Programmable CPLD Family

14 www.xilinx.com DS063 (v5.5) June 25, 2007

Product Specification

Low Power Mode

All XC9500 devices offer a low-power mode for individual

macrocel ls or acr os s all macro cells . T his fea tur e al lo ws th e

device power to be signifi cantl y reduc ed .

Each individual macrocell may be programmed in

low-power mode by the user. Performance-critical parts of

the application can remain in standard power mode, while

other parts of the application may be programmed for

low-power operation to reduce the overall power dissipa-

tion. Macrocells programmed for low-power mode incur

additional delay (TLP) in pin-to-pin combinatorial delay as

well as register setup time. Product term clock to output and

product term output enable delays are unaffected by the

macrocell power-setting.

Timing Model

The uniformity of the XC9500 architecture allows a simpli-

fied timing model for the entire device. The basic timing

model, shown in Figure 14, is valid for macrocell functions

that u se the di rect p roduct t erms only, with standard power

setting, a nd standard slew rate se tting. Table 4 s hows how

each of the key timing parameters is affected by the product

term allo cator (if nee ded), low-po wer settin g, and slew-li m-

ited setting.

The product term allocation time depends on the logic span

of the macro ce ll fu nct ion , whic h is defined as one less tha n

the maximum number of allocators in the product term path.

If only dir ect p roduct ter ms are us ed, the n the log ic span is

0. The example in Figure 6 shows that up to 15 product

terms are available with a span of 1. In the case of Figure 7,

the 18 product term function has a span of 2.

Detailed timing information may be derived from the full tim-

ing m ode l show n i n Figure 15. The values and explanations

for each parameter are given in the individual device data

sheets.

Figure 13: In-System Programming Operation (a) Solder Device to PCB and (b) Program Using Download Cable

X5902

GND

(a) (b)

XC9500 In-System Programmable CPLD Family

DS063 (v5.5) June 25, 2007 www.xilinx.com 15

Product Specification

Figure 14: Basic Timing Model

Figure 15: Detailed Timing Model

Combinatorial

Logic

Propagation Delay = T

(a)

Combinatorial

Logic

Setup Time = T

PSU

PCO

Clock to Out Time = T

(b)

D/T Q

Combinatorial

Logic

Internal System Cycle Time = T

SYSTEM

DS063_14_110501

(d)

D/T Q

Combinatorial

Logic

Setup Time = T

PSU

Clock to Out Time = T

PCO

(c)

P-Term Clock

Path

D/T Q

Combinatorial

Logic

All resources within FB using local Feedback

Internal Cycle Time = T

CNT

(e)

D/T Q

TIN

TLOGILP S*TPTA

Pin Feedback

TPDI

TSUI TCOI

THI

TAOI

TRAI

TOUT

TSLEW

TEN

DS063_15_110501

TLOGI

TPTCK

TPTSR

TPTTS

TGCK

TGSR

TGTS

Macrocell

XC9500 In-System Programmable CPLD Family

16 www.xilinx.com DS063 (v5.5) June 25, 2007

Product Specification

Power-Up Characte ri stics

The XC9500 devices are well behaved un der all operating

conditio ns. Du ring po wer-u p each X C95 00 devic e emp loys

internal circuitry which keeps the device in the quiescent

state until the VCCINT supply voltage is at a safe level

(approximately 3.8V). During this time, all device pins and

JTAG pins ar e di sa ble d a nd all d ev ic e o utp uts are dis ab le d

with the IOB pull-up resistors (~10K ohms) enabled, as

shown in Table 5. Wh en the su pply vo ltage reach es a saf e

level, all user registers become initialized (typically within

100 μs for 9536, 95144, 200 μs for 95216, and 300 μs for

95288), and the device is immediately available for opera-

tion, as shown in Figure 16.

If the device is in the erased state (before any user pattern

is programmed), the device outputs remain disabled with

the IOB pull-up resistors enabled. The JTAG pins are

enabled to allow the device to be programmed at any time.

If the device is programmed, the device inputs and out puts

take on their configured states for normal operation. The

JTAG pins are enabled to allow device erasure or bound-

ary-scan tests at any time.

Development System Support

The XC9500 CPLD family is fully supported by the develop-

ment systems available from Xilinx and the Xilinx Alliance

Program vendors.

The desi gner can cr eate the de sign usi ng ABEL, sc hemat-

ics, equations, VHDL, or Verilog in a variety of software

front-end tools. The development system can be used to

implement the design and generate a JEDEC bitmap which

can be used to program the XC9500 device. Each develop-

ment system includes JTAG download software that can be

used to program the devices via the standard JTAG inter-

face and a download cable.

FastFLASH Techno log y

An advanced CMOS Flash process is use d to fabricate all

XC9500 devices. Specifically developed for Xilinx in-system

programmable CPLDs, the FastFLASH process provides

high performance logic capability, fast prog ramming times,

and endurance of 10,000 program/erase cycles.

Figure 16: Device Behavior During Power-up

VCCINT

Power

3.8 V

(Typ)

Power

Quiescent

State

Quiescent

State

User Operation

Initialization of User Registers

DS063_16_110501

3.8V

(Typ)

Table 4: Timing Model Parameters

Parameter Description Product Te rm

Allocator(1) Macrocell

Low-Power Setting

Output

Slew-Limited

Setting

TPD Propagation Delay + TPTA * S+ T

LP + TSLEW

TSU Global Clock Setup Time + TPTA * S+ T

LP –

TCO Global Clo ck- to- out put - - + TSLEW

TPSU Product Term Clock Setup Time + TPTA * S+ T

LP -

TPCO Product Term Clock-to-output - - + TSLEW

TSYSTEM Internal System Cycle Period + TPTA * S+ T

LP -

Notes:

1. S = the logic span of the function, as defined in the text.

Table 5: XC95 00 Devic e Charac teris tic s

Device Circuitry Quiescent State Erased Device Operation Valid User Operation

IOB Pull-up Resistors Enabled Enabled Disabled

Device Outputs Disabled Disabled As Configured

XC9500 In-System Programmable CPLD Family

DS063 (v5.5) June 25, 2007 www.xilinx.com 17

Product Specification

Warranty Disclai mer

THESE PRODUCTS ARE SUBJECT TO THE TERMS OF THE XI LINX LIMITED WARRANTY WHICH CA N BE VIEWED

AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF THE

PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED ON THE

THEN-CURRENT XILINX DATA SHEET FOR THE PRODUCTS. PRODUCTS ARE NOT DESIGNED TO BE FAIL-SAFE

AND ARE NOT WARRANTED FOR USE IN APPLICATIONS THAT POSE A RISK OF PHYSICAL HARM OR LOSS OF

LIFE. USE OF PRODUCTS IN SUCH APPLICATIONS IS FULLY AT THE RISK OF CUSTOMER SUBJECT TO

APPLICABLE LAWS AND REGULATIONS.

Additional Information

XC9500 Data sheets and application notes. Packages

Revision Hist ory

The following table shows the revision history for this document.

Device Inputs and Clocks Disabled Disabled As Configured

Function Block Disabled Disabled As Configured

JTAG Controller Disabled Enabled Enabled

Table 5: XC95 00 Devic e Charac teris tic s

Device Circuitry Quiescent State Erased Device Operation Valid User Operation

Date Version Revision

3.0 12/14/98 Revised datasheet to reflect new AC characteristics and Internal Timing Parmeters.

4.0 02/10/99 Corrected Figure 3.

5.0 09/15/99 Added -10 speed grade to XC95288.

5.1 09/22/03 Minor edits.

5.2 02/16/04 Corrected statement on GTS inputs on page 10. Added links to additional information.

5.3 04/15/05 Update to PDF attributes only. No changes to documentation.

5.4 04/03 /06 A dd ed Warranty Disclaim er. Added note on Pb-Free packa ges .

5.5 06/25/07 Change to Table 2, listing discontinuance of 352-pin BGA package for the XC95216. See

XCN07010 for details.