LM5111-1MYX/NOPB - NATIONAL SEMICONDUCTOR

LM5111

LM5111 Dual 5A Compound Gate Driver

Literature Number: SNVS300F

LM5111

May 26, 2011

Dual 5A Compound Gate Driver

General Description

The LM5111 Dual Gate Driver replaces industry standard

gate drivers with improved peak output current and efficiency.

Each “compound” output driver stage includes MOS and bipo-

lar transistors operating in parallel that together sink more

than 5A peak from capacitive loads. Combining the unique

characteristics of MOS and bipolar devices reduces drive cur-

rent variation with voltage and temperature. Under-voltage

lockout protection is also provided. The drivers can be oper-

ated in parallel with inputs and outputs connected to double

the drive current capability. This device is available in the

SOIC-8 package or the thermally enhanced MSOP8-EP

package.

Features

■Independently drives two N-Channel MOSFETs

■Compound CMOS and bipolar outputs reduce output

current variation

■5A sink/3A source current capability

■Two channels can be connected in parallel to double the

drive current

■Independent inputs (TTL compatible)

■Fast propagation times (25 ns typical)

■Fast rise and fall times (14 ns/12 ns rise/fall with 2 nF load)

■Available in dual non-inverting, dual inverting and

combination configurations

■Supply rail under-voltage lockout protection (UVLO)

■LM5111-4 UVLO configured to drive PFET through

OUT_A and NFET through OUT_B

■Pin compatible with industry standard gate drivers

Typical Applications

■Synchronous Rectifier Gate Drivers

■Switch-mode Power Supply Gate Driver

■Solenoid and Motor Drivers

Packages

■SOIC-8

■Thermally Enhanced MSOP8-EP

Connection Diagram

20112301

SOIC-8, eMSOP-8

LM5111 Dual 5A Compound Gate Driver

Ordering Information

Order Number Package Type NSC Package Drawing Supplied As

LM5111-1M SOIC-8 M08A Shipped in anti-static units, 95 Units/Rail

LM5111-1MX SOIC-8 M08A 2500 shipped in Tape & Reel

LM5111-2M SOIC-8 M08A Shipped in anti-static units, 95 Units/Rail

LM5111-2MX SOIC-8 M08A 2500 shipped in Tape & Reel

LM5111-3M SOIC-8 M08A Shipped in anti-static units, 95 Units/Rail

LM5111-3MX SOIC-8 M08A 2500 shipped in Tape & Reel

LM5111-1MY MSOP8-EP MUY08A 1000 shipped in Tape & Reel

LM5111-1MYX MSOP8-EP MUY08A 3500 shipped in Tape & Reel

LM5111-2MY MSOP8-EP MUY08A 1000 shipped in Tape & Reel

LM5111-2MYX MSOP8-EP MUY08A 3500 shipped in Tape & Reel

LM5111-3MY MSOP8-EP MUY08A 1000 shipped in Tape & Reel

LM5111-3MYX MSOP8-EP MUY08A 3000 shipped in Tape & Reel

LM5111-4M SOIC-8 M08A Shipped in anti-static units, 95 Units/Rail

LM5111-4MX SOIC-8 M08A 2500 shipped in Tape & Reel

LM5111-4MY MSOP8-EP MUY08A 1000 shipped in Tape & Reel

LM5111-4MYX MSOP8-EP MUY08A 3500 shipped in Tape & Reel

Pin Descriptions

Pin Name Description Application Information

1 NC No Connect

2 IN_A ‘A’ side control input TTL compatible thresholds.

3 VEE Ground reference for both inputs and

outputs

Connect to power ground.

4 IN_B ‘B’ side control input TTL compatible thresholds.

5 OUT_B Output for the ‘B’ side driver. Voltage swing of this output is from VCC to VEE. The output

stage is capable of sourcing 3A and sinking 5A.

6 VCC Positive output supply Locally decouple to VEE.

7 OUT_A. Output for the ‘A’ side driver. Voltage swing of this output is from VCC to VEE. The output

stage is capable of sourcing 3A and sinking 5A.

8 NC No Connect

EP (MSOP8–EP Package) It is recommended that the exposed pad on the bottom of the

package be soldered to ground plane on the PC board to aid

thermal dissipation.

Configuration Table

Part Number “A” Output Configuration “B” Output Configuration Package

LM5111-1M/-1MX/-1MY/-1MYX Non-Inverting (Low in UVLO) Non-Inverting (Low in UVLO) SOIC-8, MSOP8-EP

LM5111-2M/-2MX/-2MY/-2MYX Inverting (Low in UVLO) Inverting (Low in UVLO) SOIC-8, MSOP8-EP

LM5111-3M/-3MX/-3MY/-3MYX Inverting (Low in UVLO) Non-Inverting (Low in UVLO) SOIC-8, MSOP8-EP

LM5111-4M/-4MX/-4MY/-4MYX Inverting (High in UVLO) Non-Inverting (Low in UVLO) SOIC-8, MSOP8-EP

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LM5111

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

VCC to VEE −0.3V to 15V

IN to VEE −0.3V to 15V

Storage Temperature Range, (TSTG)−55°C to +150°C

Maximum Junction Temperature,

(TJ(max)) +150°C

Operating Junction Temperature +125°C

ESD Rating 2kV

Electrical Characteristics

TJ = −40°C to +125°C, VCC = 12V, VEE = 0V, No Load on OUT_A or OUT_B, unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Units

VCC Operating Range VCC−VEE 3.5 14 V

VCCR VCC Under Voltage Lockout

(rising)

VCC−VEE 2.3 2.9 3.5 V

VCCH VCC Under Voltage Lockout

Hysteresis

230 mV

ICC VCC Supply Current (ICC) IN_A = IN_B = 0V (5111-1) 1 2

IN_A = IN_B = VCC (5111-2) 1 2

IN_A = VCC, IN_B = 0V (5111-3) 1 2

CONTROL INPUTS

VIH Logic High 2.2 V

VIL Logic Low 0.8 V

VthH High Threshold 1.3 1.75 2.2 V

VthL Low Threshold 0.8 1.35 2.0 V

HYS Input Hysteresis 400 mV

IIL Input Current Low IN_A=IN_B=VCC (5111-1-2-3) −1 0.1 1

µA

IIH Input Current High IN_B=VCC (5111-3) 10 18 25

IN_A=IN_B=VCC (5111-2) −1 0.1 1

IN_A=IN_B=VCC (5111-1) 10 18 25

IN_A=VCC (5111-3) -1 0.1 1

OUTPUT DRIVERS

ROH Output Resistance High IOUT = −10 mA (Note 2) 30 50 Ω

ROL Output Resistance Low IOUT = + 10 mA (Note 2) 1.4 2.5 Ω

ISource Peak Source Current OUTA/OUTB = VCC/2,

200 ns Pulsed Current 3 A

ISink Peak Sink Current OUTA/OUTB = VCC/2,

200 ns Pulsed Current 5 A

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LM5111

Symbol Parameter Conditions Min Typ Max Units

SWITCHING CHARACTERISTICS

td1 Propagation Delay Time Low to

High, IN rising (IN to OUT)

CLOAD = 2 nF, see Figure 1 25 40 ns

td2 Propagation Delay Time High to

Low, IN falling (IN to OUT)

CLOAD = 2 nF, see Figure 1 25 40 ns

trRise Time CLOAD = 2 nF, see Figure 1 14 25 ns

tfFall Time CLOAD = 2 nF, see Figure 1 12 25 ns

LATCHUP PROTECTION

AEC - Q100, Method 004 TJ = 150°C 500 mA

THERMAL RESISTANCE

θJA Junction to Ambient,

0 LFPM Air Flow

SOIC-8 Package

MSOP8-EP Package 170

60 °C/W

θJC Junction to Case SOIC-8 Package

MSOP8-EP Package 70

4.7 °C/W

Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the

device is intended to be functional. For guaranteed specifications and test conditions, see the Electrical Characteristics.

Note 2: The output resistance specification applies to the MOS device only. The total output current capability is the sum of the MOS and Bipolar devices.

Timing Waveforms

20112305

(a)

20112306

(b)

FIGURE 1. (a) Inverting, (b) Non-Inverting

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LM5111

Typical Performance Characteristics

Supply Current vs Frequency

20112310

Supply Current vs Capacitive Load

20112311

Rise and Fall Time vs Supply Voltage

20112312

Rise and Fall Time vs Temperature

20112313

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LM5111

Rise and Fall Time vs Capacitive Load

20112314

Delay Time vs Supply Voltage

20112315

Delay Time vs Temperature

20112316

RDSON vs Supply Voltage

20112317

UVLO Thresholds and Hysteresis vs Temperature

20112318

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LM5111

Block Diagram

20112303

Block Diagram of LM5111

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LM5111

Detailed Operating Description

LM5111 dual gate driver consists of two independent and

identical driver channels with TTL compatible logic inputs and

high current totem-pole outputs that source or sink current to

drive MOSFET gates. The driver output consist of a com-

pound structure with MOS and bipolar transistor operating in

parallel to optimize current capability over a wide output volt-

age and operating temperature range. The bipolar device

provides high peak current at the critical threshold region of

the MOSFET VGS while the MOS devices provide rail-to-rail

output swing. The totem pole output drives the MOSFET gate

between the gate drive supply voltage VCC and the power

ground potential at the VEE pin.

The control inputs of the drivers are high impedance CMOS

buffers with TTL compatible threshold voltages. The LM5111

pinout was designed for compatibility with industry standard

gate drivers in single supply gate driver applications.

The input stage of each driver should be driven by a signal

with a short rise and fall time. Slow rising and falling input

signals, although not harmful to the driver, may result in the

output switching repeatedly at a high frequency.

The two driver channels of the LM5111 are designed as iden-

tical cells. Transistor matching inherent to integrated circuit

manufacturing ensures that the AC and DC peformance of the

channels are nearly identical. Closely matched propagation

delays allow the dual driver to be operated as a single with

inputs and output pins connected. The drive current capability

in parallel operation is precisely 2X the drive of an individual

channel. Small differences in switching speed between the

driver channels will produce a transient current (shoot-

through) in the output stage when two output pins are con-

nected to drive a single load. Differences in input thresholds

between the driver channels will also produce a transient cur-

rent (shoot-through) in the output stage. Fast transition input

signals are especially important while operating in a parallel

configuration. The efficiency loss for parallel operation has

been characterized at various loads, supply voltages and op-

erating frequencies. The power dissipation in the LM5111

increases be less than 1% relative to the dual driver configu-

ration when operated as a single driver with inputs/ outputs

connected.

An Under Voltage Lock Out (UVLO) circuit is included in the

LM5111 , which senses the voltage difference between VCC

and the chip ground pin, VEE. When the VCC to VEE voltage

difference falls below 2.8V both driver channels are disabled.

The UVLO hysteresis prevents chattering during brown-out

conditions and the driver will resume normal operation when

the VCC to VEE differential voltage exceeds approximately

3.0V.

The LM5111-1, -2 and -3 devices hold both outputs in the low

state in the under-voltage lockout (UVLO) condition. The

LM5111-4 is distinguished from the LM5111-3 by the active

high output state of OUT_A during UVLO. When VCC is less

than the UVLO threshold voltage, OUT_A of the LM5111-4

will be locked in the high state while OUT_B will be disabled

in the low state. This configuration allows the LM5111-4 to

drive a PFET through OUT_A and an NFET through OUT_B

with both FETs safely turned off during UVLO.

The LM5111 is available in dual non-inverting (-1), dual In-

verting (-2) and the combination inverting plus non-inverting

(-3, -4) configurations. All configurations are offered in the

SOIC-8 and MSOP8-EP plastic packages.

Layout Considerations

Attention must be given to board layout when using LM5111.

Some important considerations include:

1. A Low ESR/ESL capacitor must be connected close to

the IC and between the VCC and VEE pins to support high

peak currents being drawn from VCC during turn-on of the

MOSFET.

2. Proper grounding is crucial. The drivers need a very low

impedance path for current return to ground avoiding

inductive loops. The two paths for returning current to

ground are a) between LM5111 VEE pin and the ground

of the circuit that controls the driver inputs, b) between

LM5111 VEE pin and the source of the power MOSFET

being driven. All these paths should be as short as

possible to reduce inductance and be as wide as possible

to reduce resistance. All these ground paths should be

kept distinctly separate to avoid coupling between the

high current output paths and the logic signals that drive

the LM5111. A good method is to dedicate one copper

plane in a multi-layered PCB to provide a common

ground surface.

3. With the rise and fall times in the range of 10 ns to 30 ns,

care is required to minimize the lengths of current

carrying conductors to reduce their inductance and EMI

from the high di/dt transients generated by the LM5111.

4. The LM5111 footprint is compatible with other industry

standard drivers including the TC4426/27/28 and

UCC27323/4/5.

5. If either channel is not being used, the respective input

pin (IN_A or IN_B) should be connected to either VEE or

VCC to avoid spurious output signals.

Thermal Performance

INTRODUCTION

The primary goal of thermal management is to maintain the

integrated circuit (IC) junction temperature (TJ) below a spec-

ified maximum operating temperature to ensure reliability. It

is essential to estimate the maximum TJ of IC components in

worst case operating conditions. The junction temperature is

estimated based on the power dissipated in the IC and the

junction to ambient thermal resistance θJA for the IC package

in the application board and environment. The θJA is not a

given constant for the package and depends on the printed

circuit board design and the operating environment.

DRIVE POWER REQUIREMENT CALCULATIONS IN

LM5111

The LM5111 dual low side MOSFET driver is capable of

sourcing/sinking 3A/5A peak currents for short intervals to

drive a MOSFET without exceeding package power dissipa-

tion limits. High peak currents are required to switch the

MOSFET gate very quickly for operation at high frequencies.

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LM5111

20112307

FIGURE 2.

The schematic above shows a conceptual diagram of the

LM5111 output and MOSFET load. Q1 and Q2 are the switch-

es within the gate driver. RG is the gate resistance of the

external MOSFET, and CIN is the equivalent gate capacitance

of the MOSFET. The gate resistance Rg is usually very small

and losses in it can be neglected. The equivalent gate ca-

pacitance is a difficult parameter to measure since it is the

combination of CGS (gate to source capacitance) and CGD

(gate to drain capacitance). Both of these MOSFET capaci-

tances are not constants and vary with the gate and drain

voltage. The better way of quantifying gate capacitance is the

total gate charge QG in coloumbs. QG combines the charge

required by CGS and CGD for a given gate drive voltage

VGATE.

Assuming negligible gate resistance, the total power dissi-

pated in the MOSFET driver due to gate charge is approxi-

mated by

PDRIVER = VGATE x QG x FSW

Where

FSW = switching frequency of the MOSFET.

For example, consider the MOSFET MTD6N15 whose gate

charge specified as 30 nC for VGATE = 12V.

The power dissipation in the driver due to charging and dis-

charging of MOSFET gate capacitances at switching frequen-

cy of 300 kHz and VGATE of 12V is equal to

PDRIVER = 12V x 30 nC x 300 kHz = 0.108W.

If both channels of the LM5111 are operating at equal fre-

quency with equivalent loads, the total losses will be twice as

this value which is 0.216W.

In addition to the above gate charge power dissipation, - tran-

sient power is dissipated in the driver during output transi-

tions. When either output of the LM5111 changes state,

current will flow from VCC to VEE for a very brief interval of time

through the output totem-pole N and P channel MOSFETs.

The final component of power dissipation in the driver is the

power associated with the quiescent bias current consumed

by the driver input stage and Under-voltage lockout sections.

Characterization of the LM5111 provides accurate estimates

of the transient and quiescent power dissipation components.

At 300 kHz switching frequency and 30 nC load used in the

example, the transient power will be 8 mW. The 1 mA nominal

quiescent current and 12V VGATE supply produce a 12 mW

typical quiescent power.

Therefore the total power dissipation

PD = 0.216 + 0.008 + 0.012 = 0.236W.

We know that the junction temperature is given by

TJ = PD x θJA + TA

Or the rise in temperature is given by

TRISE = TJ − TA = PD x θJA

For SOIC-8 package θJA is estimated as 170°C/W for the

conditions of natural convection. For MSOP8-EP θJA is typi-

cally 60°C/W.

Therefore for SOIC TRISE is equal to

TRISE = 0.236 x 170 = 40.1°C

CONTINUOUS CURRENT RATING OF LM5111

The LM5111 can deliver pulsed source/sink currents of 3A

and 5A to capacitive loads. In applications requiring continu-

ous load current (resistive or inductive loads), package power

dissipation, limits the LM5111 current capability far below the

5A sink/3A source capability. Rated continuous current can

be estimated both when sourcing current to or sinking current

from the load. For example when sinking, the maximum sink

current can be calculated as:

where RDS(on) is the on resistance of lower MOSFET in the

output stage of LM5111.

Consider TJ(max) of 125°C and θJA of 170°C/W for an SO-8

package under the condition of natural convection and no air

flow. If the ambient temperature (TA) is 60°C, and the RDS(on)

of the LM5111 output at TJ(max) is 2.5Ω, this equation yields

ISINK(max) of 391mA which is much smaller than 5A peak

pulsed currents.

Similarly, the maximum continuous source current can be

calculated as

where VDIODE is the voltage drop across hybrid output stage

which varies over temperature and can be assumed to be

about 1.1V at TJ(max) of 125°C. Assuming the same param-

eters as above, this equation yields ISOURCE(max) of 347mA.

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LM5111

Physical Dimensions inches (millimeters) unless otherwise noted

NOTES: UNLESS OTHERWISE SPECIFIED

1. STANDARD LEAD FINISH TO BE 200 MICROINCHES/5.08 MICROMETERS MINIMUM LEAD/TIN(SOLDER) ON COPPER.

2. DIMENSION DOES NOT INCLUDE MOLD FLASH.

3. REFERENCE JEDEC REGISTRATION MS-012, VARIATION AA, DATED MAY 1990.

8-Lead SOIC Package

NS Package Number M08A

8-Lead Exposed Pad MSOP Package

NS Package Number MUY08A

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LM5111

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LM5111

Notes

LM5111 Dual 5A Compound Gate Driver

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