UVLO
VEE
IN_A
VCC
VCC
OUT_A
VEE
OUT_B
VEE
IN_B
LM5111
www.ti.com
SNVS300G –JULY 2004–REVISED MARCH 2013
LM5111 Dual 5A Compound Gate Driver
Check for Samples: LM5111
1FEATURES DESCRIPTION
The LM5111 Dual Gate Driver replaces industry
2• Independently Drives Two N-Channel standard gate drivers with improved peak output
MOSFETs current and efficiency. Each “compound” output driver
• Compound CMOS and Bipolar Outputs Reduce stage includes MOS and bipolar transistors operating
Output Current Variation in parallel that together sink more than 5A peak from
capacitive loads. Combining the unique
• 5A Sink/3A Source Current Capability characteristics of MOS and bipolar devices reduces
• Two Channels can be Connected in Parallel to drive current variation with voltage and temperature.
Double the Drive Current Under-voltage lockout protection is also provided.
• Independent Inputs (TTL Compatible) The drivers can be operated in parallel with inputs
and outputs connected to double the drive current
• Fast Propagation Times (25 ns Typical) capability. This device is available in the SOIC
• Fast Rise and Fall Times (14 ns/12 ns Rise/Fall package or the thermally enhanced VSSOP package.
with 2 nF Load)
• Available in Dual Non-Inverting, Dual Inverting TYPICAL APPLICATIONS
and Combination Configurations • Synchronous Rectifier Gate Drivers
• Supply Rail Under-Voltage Lockout Protection • Switch-mode Power Supply Gate Driver
(UVLO) • Solenoid and Motor Drivers
• LM5111-4 UVLO Configured to Drive PFET
through OUT_A and NFET through OUT_B PACKAGES
• Pin Compatible with Industry Standard Gate • SOIC-8
Drivers • Thermally Enhanced VSSOP
Block Diagram
Figure 1. Block Diagram of LM5111
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2004–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
OUT A
1
2
3
4 5
6
7
8
NC
IN_A
VEE
IN_B
NC
VCC
OUT_B
LM5111
SNVS300G –JULY 2004–REVISED MARCH 2013
www.ti.com
Connection Diagram
Figure 2. 8-Lead SOIC or VSSOP
PIN DESCRIPTIONS
Pin Name Description Application Information
1 NC No Connect
2 IN_A ‘A’ side control input TTL compatible thresholds.
Ground reference for both inputs and
3 VEE Connect to power ground.
outputs
4 IN_B ‘B’ side control input TTL compatible thresholds.
Voltage swing of this output is from VCC to VEE. The output
5 OUT_B Output for the ‘B’ side driver. stage is capable of sourcing 3A and sinking 5A.
6 VCC Positive output supply Locally decouple to VEE.
Voltage swing of this output is from VCC to VEE. The output
7 OUT_A. Output for the ‘A’ side driver. stage is capable of sourcing 3A and sinking 5A.
8 NC No Connect It is recommended that the exposed pad on the bottom of the
EP (VSSOP Package) package be soldered to ground plane on the PC board to aid
thermal dissipation.
Configuration Table
Part Number “A” Output Configuration “B” Output Configuration Package
LM5111-1M/-1MX/-1MY/-1MYX Non-Inverting (Low in UVLO) Non-Inverting (Low in UVLO) SOIC, VSSOP
LM5111-2M/-2MX/-2MY/-2MYX Inverting (Low in UVLO) Inverting (Low in UVLO) SOIC, VSSOP
LM5111-3M/-3MX/-3MY/-3MYX Inverting (Low in UVLO) Non-Inverting (Low in UVLO) SOIC, VSSOP
LM5111-4M/-4MX/-4MY/-4MYX Inverting (High in UVLO) Non-Inverting (Low in UVLO) SOIC, VSSOP
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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SNVS300G –JULY 2004–REVISED MARCH 2013
Absolute Maximum Ratings(1)(2)
VCC to VEE −0.3V to 15V
IN to VEE −0.3V to 15V
Storage Temperature Range, (TSTG)−55°C to +150°C
Maximum Junction Temperature, (TJ(max)) +150°C
Operating Junction Temperature +125°C
ESD Rating 2kV
(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is intended to be functional. For guaranteed specifications and test conditions, see the Electrical Characteristics.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
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LM5111
SNVS300G –JULY 2004–REVISED MARCH 2013
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Electrical Characteristics
TJ=−40°C to +125°C, VCC = 12V, VEE = 0V, No Load on OUT_A or OUT_B, unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
VCC Operating Range VCC−VEE 3.5 14 V
VCCR VCC Under Voltage Lockout (rising) VCC−VEE 2.3 2.9 3.5 V
VCCH VCC Under Voltage Lockout 230 mV
Hysteresis
ICC IN_A = IN_B = 0V (5111-1) 1 2
VCC Supply Current (ICC) IN_A = IN_B = VCC (5111-2) 1 2 mA
IN_A = VCC, IN_B = 0V (5111-3) 1 2
CONTROL INPUTS
VIH Logic High 2.2 V
VIL Logic Low 0.8 V
VthH High Threshold 1.3 1.75 2.2 V
VthL Low Threshold 0.8 1.35 2.0 V
HYS Input Hysteresis 400 mV
IIL Input Current Low IN_A=IN_B=VCC (5111-1-2-3) −1 0.1 1
IIH IN_B=VCC (5111-3) 10 18 25
IN_A=IN_B=VCC (5111-2) −1 0.1 1 µA
Input Current High IN_A=IN_B=VCC (5111-1) 10 18 25
IN_A=VCC (5111-3) -1 0.1 1
OUTPUT DRIVERS
ROH Output Resistance High IOUT =−10 mA(1) 30 50 Ω
ROL Output Resistance Low IOUT = + 10 mA(1) 1.4 2.5 Ω
ISource OUTA/OUTB = VCC/2,
Peak Source Current 3 A
200 ns Pulsed Current
ISink OUTA/OUTB = VCC/2,
Peak Sink Current 5 A
200 ns Pulsed Current
SWITCHING CHARACTERISTICS
td1 Propagation Delay Time Low to CLOAD = 2 nF 25 40 ns
High, IN rising (IN to OUT) See Figure 3 and Figure 4
td2 Propagation Delay Time High to CLOAD = 2 nF 25 40 ns
Low, IN falling (IN to OUT) See Figure 3 and Figure 4
trCLOAD = 2 nF
Rise Time 14 25 ns
See Figure 3 and Figure 4
tfCLOAD = 2 nF
Fall Time 12 25 ns
See Figure 3 and Figure 4
LATCHUP PROTECTION
AEC - Q100, Method 004 TJ= 150°C 500 mA
THERMAL RESISTANCE
θJA Junction to Ambient, SOIC Package 170 °C/W
0 LFPM Air Flow VSSOP Package 60
θJC SOIC Package 70
Junction to Case °C/W
VSSOP Package 4.7
(1) The output resistance specification applies to the MOS device only. The total output current capability is the sum of the MOS and
Bipolar devices.
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46 8 10 12 14 16
SUPPLY VOLTAGE (V)
17.5
20
22.5
25
27.5
30
32.5
TIME (ns)
tD2
tD1
TA = 25°C
CL = 2200pF
100 1k 10k
CAPACITIVE LOAD (pF)
0
10
20
30
40
50
TIME (ns)
tr
tf
TA = 25°C
VCC = 12V
-75 -50 -25 0 25 50 75 100 125 150 175
10
12
14
16
18
20
TIME (ns)
TEMPERATURE (°C)
tr
tf
VCC = 12V
CL = 2200pF
46910 12 13 16
10
14
16
18
20
TIME (ns)
SUPPLY VOLTAGE (V)
12
57811 14 15
tr
tf
TA = 25°C
CL = 2200pF
110 100 1000
FREQUENCY (kHz)
0.1
1
10
100
SUPPLY CURRENT (mA)
VCC = 15V
VCC = 10V
VCC = 5V
TA = 25°C
CL = 2200pF
100
1
1k
100
10k
CAPACITIVE LOAD (pF)
0.1
10
1000
SUPPLY CURRENT (mA)
f = 500kHz
f = 100kHz
f = 10kHz
TA = 25°C
VCC = 12V
LM5111
SNVS300G –JULY 2004–REVISED MARCH 2013
www.ti.com
Typical Performance Characteristics
Supply Current vs Frequency Supply Current vs Capacitive Load
Figure 5. Figure 6.
Rise and Fall Time vs Supply Voltage Rise and Fall Time vs Temperature
Figure 7. Figure 8.
Rise and Fall Time vs Capacitive Load Delay Time vs Supply Voltage
Figure 9. Figure 10.
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-75 -50 -25 0 25 50 75 100 125 150 175
1.600
1.900
2.200
2.500
2.800
3.100
UVLO THRESHOLDS (V)
TEMPERATURE (°C)
0.150
0.210
0.270
0.330
0.450
0.390
HYSTERESIS (V)
VCCR
VCCF
VCCH
-75 -50 -25 0 25 50 75 100 125 150 175
17.5
20
22.5
25
27.5
30
32.5
TIME (ns)
TEMPERATURE (°C)
tD2
tD1
VCC = 12V
CL = 2200pF
03 6 9 12 15 18
SUPPLY VOLTAGE (V)
0.75
1.25
1.75
2.25
2.75
3.25
ROL (:)
15
25
45
55
65
35
ROH (:)
ROH
ROL
TA = 25°C
IOUT = 10mA
LM5111
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SNVS300G –JULY 2004–REVISED MARCH 2013
Typical Performance Characteristics (continued)
Delay Time vs Temperature RDSON vs Supply Voltage
Figure 11. Figure 12.
UVLO Thresholds and Hysteresis vs Temperature
Figure 13.
Detailed Operating Description
LM5111 dual gate driver consists of two independent and identical driver channels with TTL compatible logic
inputs and high current totem-pole outputs that source or sink current to drive MOSFET gates. The driver output
consist of a compound structure with MOS and bipolar transistor operating in parallel to optimize current
capability over a wide output voltage and operating temperature range. The bipolar device provides high peak
current at the critical threshold region of the MOSFET VGS while the MOS devices provide rail-to-rail output
swing. The totem pole output drives the MOSFET gate between the gate drive supply voltage VCC and the power
ground potential at the VEE pin.
The control inputs of the drivers are high impedance CMOS buffers with TTL compatible threshold voltages. The
LM5111 pinout was designed for compatibility with industry standard gate drivers in single supply gate driver
applications.
The input stage of each driver should be driven by a signal with a short rise and fall time. Slow rising and falling
input signals, although not harmful to the driver, may result in the output switching repeatedly at a high
frequency.
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LM5111
SNVS300G –JULY 2004–REVISED MARCH 2013
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The two driver channels of the LM5111 are designed as identical cells. Transistor matching inherent to integrated
circuit manufacturing ensures that the AC and DC peformance of the channels are nearly identical. Closely
matched propagation delays allow the dual driver to be operated as a single with inputs and output pins
connected. The drive current capability in parallel operation is precisely 2X the drive of an individual channel.
Small differences in switching speed between the driver channels will produce a transient current (shoot-through)
in the output stage when two output pins are connected to drive a single load. Differences in input thresholds
between the driver channels will also produce a transient current (shoot-through) in the output stage. Fast
transition input signals are especially important while operating in a parallel configuration. The efficiency loss for
parallel operation has been characterized at various loads, supply voltages and operating frequencies. The
power dissipation in the LM5111 increases be less than 1% relative to the dual driver configuration when
operated as a single driver with inputs/ outputs connected.
An Under Voltage Lock Out (UVLO) circuit is included in the LM5111, which senses the voltage difference
between VCC and the chip ground pin, VEE. When the VCC to VEE voltage difference falls below 2.8V both driver
channels are disabled. The UVLO hysteresis prevents chattering during brown-out conditions and the driver will
resume normal operation when the VCC to VEE differential voltage exceeds approximately 3.0V.
The LM5111-1, -2 and -3 devices hold both outputs in the low state in the under-voltage lockout (UVLO)
condition. The LM5111-4 is distinguished from the LM5111-3 by the active high output state of OUT_A during
UVLO. When VCC is less than the UVLO threshold voltage, OUT_A of the LM5111-4 will be locked in the high
state while OUT_B will be disabled in the low state. This configuration allows the LM5111-4 to drive a PFET
through OUT_A and an NFET through OUT_B with both FETs safely turned off during UVLO.
The LM5111 is available in dual non-inverting (-1), dual Inverting (-2) and the combination inverting plus non-
inverting (-3, -4) configurations. All configurations are offered in the SOIC and VSSOP plastic packages.
Layout Considerations
Attention must be given to board layout when using LM5111. Some important considerations include:
1. A Low ESR/ESL capacitor must be connected close to the IC and between the VCC and VEE pins to support
high peak currents being drawn from VCC during turn-on of the MOSFET.
2. Proper grounding is crucial. The drivers need a very low impedance path for current return to ground
avoiding inductive loops. The two paths for returning current to ground are a) between LM5111 VEE pin and
the ground of the circuit that controls the driver inputs, b) between LM5111 VEE pin and the source of the
power MOSFET being driven. All these paths should be as short as possible to reduce inductance and be as
wide as possible to reduce resistance. All these ground paths should be kept distinctly separate to avoid
coupling between the high current output paths and the logic signals that drive the LM5111. A good method
is to dedicate one copper plane in a multi-layered PCB to provide a common ground surface.
3. With the rise and fall times in the range of 10 ns to 30 ns, care is required to minimize the lengths of current
carrying conductors to reduce their inductance and EMI from the high di/dt transients generated by the
LM5111.
4. The LM5111 footprint is compatible with other industry standard drivers including the TC4426/27/28 and
UCC27323/4/5.
5. If either channel is not being used, the respective input pin (IN_A or IN_B) should be connected to either VEE
or VCC to avoid spurious output signals.
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VHIGH
Q2
VGATE
RG
Q1
VTRIG CIN
LM5111
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SNVS300G –JULY 2004–REVISED MARCH 2013
Thermal Performance
INTRODUCTION
The primary goal of thermal management is to maintain the integrated circuit (IC) junction temperature (TJ) below
a specified maximum operating temperature to ensure reliability. It is essential to estimate the maximum TJof IC
components in worst case operating conditions. The junction temperature is estimated based on the power
dissipated in the IC and the junction to ambient thermal resistance θJA for the IC package in the application board
and environment. The θJA is not a given constant for the package and depends on the printed circuit board
design and the operating environment.
DRIVE POWER REQUIREMENT CALCULATIONS IN LM5111
The LM5111 dual low side MOSFET driver is capable of sourcing/sinking 3A/5A peak currents for short intervals
to drive a MOSFET without exceeding package power dissipation limits. High peak currents are required to
switch the MOSFET gate very quickly for operation at high frequencies.
Figure 14.
The schematic above shows a conceptual diagram of the LM5111 output and MOSFET load. Q1 and Q2 are the
switches within the gate driver. RGis the gate resistance of the external MOSFET, and CIN is the equivalent gate
capacitance of the MOSFET. The gate resistance Rg is usually very small and losses in it can be neglected. The
equivalent gate capacitance is a difficult parameter to measure since it is the combination of CGS (gate to source
capacitance) and CGD (gate to drain capacitance). Both of these MOSFET capacitances are not constants and
vary with the gate and drain voltage. The better way of quantifying gate capacitance is the total gate charge QG
in coloumbs. QGcombines the charge required by CGS and CGD for a given gate drive voltage VGATE.
Assuming negligible gate resistance, the total power dissipated in the MOSFET driver due to gate charge is
approximated by
PDRIVER = VGATE x QGx FSW
where
• FSW = switching frequency of the MOSFET (1)
For example, consider the MOSFET MTD6N15 whose gate charge specified as 30 nC for VGATE = 12V.
The power dissipation in the driver due to charging and discharging of MOSFET gate capacitances at switching
frequency of 300 kHz and VGATE of 12V is equal to
PDRIVER = 12V x 30 nC x 300 kHz = 0.108W. (2)
If both channels of the LM5111 are operating at equal frequency with equivalent loads, the total losses will be
twice as this value which is 0.216W.
In addition to the above gate charge power dissipation, - transient power is dissipated in the driver during output
transitions. When either output of the LM5111 changes state, current will flow from VCC to VEE for a very brief
interval of time through the output totem-pole N and P channel MOSFETs. The final component of power
dissipation in the driver is the power associated with the quiescent bias current consumed by the driver input
stage and Under-voltage lockout sections.
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ISOURCE (MAX) := TJ(MAX) - TA
TJA · VDIODE
ISINK (MAX) := TJ(MAX) - TA
TJA · RDS (ON)
LM5111
SNVS300G –JULY 2004–REVISED MARCH 2013
www.ti.com
Characterization of the LM5111 provides accurate estimates of the transient and quiescent power dissipation
components. At 300 kHz switching frequency and 30 nC load used in the example, the transient power will be 8
mW. The 1 mA nominal quiescent current and 12V VGATE supply produce a 12 mW typical quiescent power.
Therefore the total power dissipation
PD= 0.216 + 0.008 + 0.012 = 0.236W. (3)
We know that the junction temperature is given by
TJ= PDxθJA + TA(4)
Or the rise in temperature is given by
TRISE = TJ−TA= PDxθJA (5)
For SOIC package, θJA is estimated as 170°C/W for the conditions of natural convection. For VSSOP, θJA is
typically 60°C/W.
Therefore for SOIC TRISE is equal to
TRISE = 0.236 x 170 = 40.1°C (6)
CONTINUOUS CURRENT RATING OF LM5111
The LM5111 can deliver pulsed source/sink currents of 3A and 5A to capacitive loads. In applications requiring
continuous load current (resistive or inductive loads), package power dissipation, limits the LM5111 current
capability far below the 5A sink/3A source capability. Rated continuous current can be estimated both when
sourcing current to or sinking current from the load. For example when sinking, the maximum sink current can be
calculated as:
where
• RDS(on) is the on resistance of lower MOSFET in the output stage of LM5111 (7)
Consider TJ(max) of 125°C and θJA of 170°C/W for an SO-8 package under the condition of natural convection
and no air flow. If the ambient temperature (TA) is 60°C, and the RDS(on) of the LM5111 output at TJ(max) is
2.5Ω, this equation yields ISINK(max) of 391mA which is much smaller than 5A peak pulsed currents.
Similarly, the maximum continuous source current can be calculated as
where
• VDIODE is the voltage drop across hybrid output stage which varies over temperature and can be assumed to
be about 1.1V at TJ(max) of 125°C (8)
Assuming the same parameters as above, this equation yields ISOURCE(max) of 347mA.
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SNVS300G –JULY 2004–REVISED MARCH 2013
REVISION HISTORY
Changes from Revision F (March 2013) to Revision G Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 10
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PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LM5111-1M/NOPB ACTIVE SOIC D 8 95 Green (RoHS
& no Sb/Br) SN | CU SN Level-1-260C-UNLIM -40 to 125 5111
-1M
LM5111-1MX NRND SOIC D 8 2500 TBD Call TI Call TI -40 to 125 5111
-1M
LM5111-1MX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) SN | CU SN Level-1-260C-UNLIM -40 to 125 5111
-1M
LM5111-1MY/NOPB ACTIVE MSOP-
PowerPAD DGN 8 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM SJKB
LM5111-1MYX/NOPB ACTIVE MSOP-
PowerPAD DGN 8 3500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM SJKB
LM5111-2M/NOPB ACTIVE SOIC D 8 95 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 5111
-2M
LM5111-2MX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) SN | CU SN Level-1-260C-UNLIM -40 to 125 5111
-2M
LM5111-2MY/NOPB ACTIVE MSOP-
PowerPAD DGN 8 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM SJLB
LM5111-2MYX/NOPB ACTIVE MSOP-
PowerPAD DGN 8 3500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM SJLB
LM5111-3M NRND SOIC D 8 95 TBD Call TI Call TI -40 to 125 5111
-3M
LM5111-3M/NOPB ACTIVE SOIC D 8 95 Green (RoHS
& no Sb/Br) SN | CU SN Level-1-260C-UNLIM -40 to 125 5111
-3M
LM5111-3MX NRND SOIC D 8 2500 TBD Call TI Call TI -40 to 125 5111
-3M
LM5111-3MX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) SN | CU SN Level-1-260C-UNLIM -40 to 125 5111
-3M
LM5111-3MY/NOPB ACTIVE MSOP-
PowerPAD DGN 8 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM SJNB
LM5111-3MYX/NOPB ACTIVE MSOP-
PowerPAD DGN 8 3500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM SJNB
LM5111-4M/NOPB ACTIVE SOIC D 8 95 Green (RoHS
& no Sb/Br) SN | CU SN Level-1-260C-UNLIM 5111
-4M
LM5111-4MX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM 5111
-4M
PACKAGE OPTION ADDENDUM
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Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LM5111-4MY/NOPB ACTIVE MSOP-
PowerPAD DGN 8 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM SSYB
LM5111-4MYX/NOPB ACTIVE MSOP-
PowerPAD DGN 8 3500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM SSYB
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
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Addendum-Page 3
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LM5111-1MX SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LM5111-1MX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LM5111-1MY/NOPB MSOP-
Power
PAD
DGN 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LM5111-1MYX/NOPB MSOP-
Power
PAD
DGN 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LM5111-2MX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LM5111-2MY/NOPB MSOP-
Power
PAD
DGN 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LM5111-2MYX/NOPB MSOP-
Power
PAD
DGN 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LM5111-3MX SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LM5111-3MX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LM5111-3MY/NOPB MSOP-
Power
PAD
DGN 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LM5111-3MYX/NOPB MSOP- DGN 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Sep-2013
Pack Materials-Page 1
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
Power
PAD
LM5111-4MX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LM5111-4MY/NOPB MSOP-
Power
PAD
DGN 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LM5111-4MYX/NOPB MSOP-
Power
PAD
DGN 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM5111-1MX SOIC D 8 2500 367.0 367.0 35.0
LM5111-1MX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LM5111-1MY/NOPB MSOP-PowerPAD DGN 8 1000 210.0 185.0 35.0
LM5111-1MYX/NOPB MSOP-PowerPAD DGN 8 3500 367.0 367.0 35.0
LM5111-2MX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LM5111-2MY/NOPB MSOP-PowerPAD DGN 8 1000 210.0 185.0 35.0
LM5111-2MYX/NOPB MSOP-PowerPAD DGN 8 3500 367.0 367.0 35.0
LM5111-3MX SOIC D 8 2500 367.0 367.0 35.0
LM5111-3MX/NOPB SOIC D 8 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Sep-2013
Pack Materials-Page 2
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM5111-3MY/NOPB MSOP-PowerPAD DGN 8 1000 210.0 185.0 35.0
LM5111-3MYX/NOPB MSOP-PowerPAD DGN 8 3500 367.0 367.0 35.0
LM5111-4MX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LM5111-4MY/NOPB MSOP-PowerPAD DGN 8 1000 210.0 185.0 35.0
LM5111-4MYX/NOPB MSOP-PowerPAD DGN 8 3500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Sep-2013
Pack Materials-Page 3
MECHANICAL DATA
DGN0008A
www.ti.com
MUY08A (Rev A)
BOTTOM VIEW
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