THROTTLE CONTROL H-BRIDGE
33932
ORDERING INFORMATION
Device
(Add R2 Suffix for
Tape and Reel)
Temperature
Range (TA)Package
MC33932VW -40 to 125 °C 44 HSOP
MC33932EK 54 SOICW-EP
VW SUFFIX (PB-FREE)
98ARH98330A
44-PIN HSOP
WITH PROTRUDING
HEAT SINK
EK SUFFIX (PB-FREE)
98ASA99334D
54-PIN SOICW-EP
Document Number: MC33932
Rev. 5.0, 10/2012
Freescale Semiconductor
Technical Data
© Freescale Semiconductor, Inc., 2009-2012. All rights reserved.
5.0 A Throttle Control H-Bridge
The 33932 is a monolithic H-Bridge Power IC in a robust thermally
enhanced package. The 33932 has two independent monolithic
H-Bridge Power ICs in the same package. They are designed primarily
for automotive electronic throttle control, but are applicable to any low
voltage DC servo motor control application within the current and
voltage limits stated in this specification.
Each H-Bridge in the 33932 is able to control inductive loads with
currents up to 5.0 A peak. RMS current capability is subject to the
degree of heatsinking provided to the device package. Internal peak-
current limiting (regulation) is activated at load currents above 6.5 A
±1.5 A. Output loads can be pulse-width modulated (PWM-ed) at
frequencies up to 11 kHz. A load current feedback feature provides a
proportional (0.24% of the load current) current output suitable for
monitoring by a microcontroller’s A/D input. A Status Flag output
reports under-voltage, over-current, and over-temperature fault
conditions.
Two independent inputs provide polarity control of two half-bridge
totem pole outputs. Two independent disable inputs are provided to
force the H-Bridge outputs to tri-state (high-impedance off state).
Features
•8.0 to 28 V continuous operation (transient operation from 5.0 to
40 V)
•235 m maximum RDS(ON) at 150 °C (each H-Bridge MOSFET)
• 3.0 and 5.0 V TTL / CMOS logic compatible inputs
• Output short-circuit protection (short to VPWR or GND)
• Over-current limiting (regulation) via internal constant-off-time
PWM
• Temperature dependant current limit threshold reduction
• All inputs have an internal source/sink to define the default
(floating input) states
• Sleep mode with current draw < 50 µA (each half with inputs
floating or set to match default logic states)
SFA
FBA
IN1
IN2
D1
EN/D2
VPWRA
CCPA
OUT1
OUT2
PGNDA
AGNDA
MCU
33932
V
PWR
V
DD
MOTOR
OUT3
OUT4
MOTOR
SFB
IN4
IN3
FBB
D3
EN/D4
PGNDB
AGNDB
VPWRB
CCPB
V
PWR
V
DD
Figure 1. MC33932 Simplified Application Diagram
Analog Integrated Circuit Device Data
2Freescale Semiconductor
33932
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VDD
LOGIC SUPPLY
CHARGE
PUMP
GATE DRIVE
AND
PROTECTION
LOGIC CURRENT MIRROR
AND
CONSTANT OFF-TIME
PWM CURRENT REGULATOR
VCP
CCPA
OUT1
OUT2
PGNDA
TO GATES
HS1
LS1
HS2
LS2
VPWRA
VSENSE
ILIM PWM
HS1 HS2
LS1 LS2LS2
IN1
IN2
EN/D2
D1
SFA
FBA
AGNDA
PGND
VDD
LOGIC SUPPLY
CHARGE
PUMP
GATE DRIVE
AND
PROTECTION
LOGIC CURRENT MIRROR
AND
CONSTANT OFF-TIME
PWM CURRENT REGULATOR
VCP
CCPB
PGNDB
TO GATES
HS1
LS1
HS2
LS2
VPWRB
VSENSE
ILIM PWM
HS1 HS2
LS1 LS2LS2
IN3
IN4
EN/D4
D3
SFB
FBB
AGNDB
PGND
OUT3
OUT4
H-Bridge A
H-Bridge B
Figure 2. 33932 Simplified Internal Block Diagram
Analog Integrated Circuit Device Data
Freescale Semiconductor 3
33932
PIN CONNECTIONS
PIN CONNECTIONS
Tab
Tab
H-BRIDGE A
H-BRIDGE B
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
D1
FBA
EN/D2
VPWRA
VPWRA
VPWRA
OUT1
OUT1
OUT1
PGNDA
PGNDA
SFA
IN1
IN2
CCPA
VPWRA
VPWRA
OUT2
OUT2
OUT2
PGNDA
PGNDA
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23 D3
FBB
EN/D4
VPWRB
VPWRB
VPWRB
OUT3
OUT3
OUT3
PGNDB
PGNDB
SFB
IN3
IN4
CCPB
VPWRB
VPWRB
OUT4
OUT4
OUT4
PGNDB
PGNDB
AGNDA
AGNDB
D1
FBA
EN/D2
VPWRA
VPWRA
OUT1
OUT1
PGNDA
PGNDA
SFB
IN3
IN4
CCPB
VPWRB
OUT4
OUT4
PGNDB
PGNDB
SFA
IN1
IN2
CCPA
VPWRA
VPWRA
OUT2
OUT2
PGNDA
PGNDA
D3
FBB
EN/D4
VPWRB
VPWRB
VPWRB
OUT3
OUT3
PGNDB
PGNDB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
AGNDA
AGNDB
44 HSOP
Transparent Top View
54 SOICW-EP
Transparent Top View
Figure 3. 33932 Pin Connections
A functional description of each pin can be found in the Functional Description section beginning on Functional Description.
Table 1. 33932 Pin Definitions
Pin
HSOP
(VW)
Pin
SOICW-EP
(EK)
Pin Name Pin
Function Formal Name Definition
1 3 D1 Logic Input Disable Input 1
(Active High)
When D1 is logic HIGH, both OUT1 and OUT2 are tri-stated.
Schmitt trigger input with ~80 A source so default
condition = disabled.
2 4 FBA Analog
Output
Feedback H-Bridge A load current feedback output provides ground
referenced 0.24% of the high side output current. (Tie to GND
through a resistor if not used.)
3 5 EN/D2 Logic Input Enable Input When EN/D2 is logic HIGH, H-Bridge A is operational. When EN/
D2 is logic LOW, the H-Bridge A outputs are tri-stated and H-
Bridge A is placed in Sleep Mode. (logic input with ~ 80 A sink so
default condition = Sleep Mode.)
4-6, 39, 40 1, 9, 46, 53 VPWRA Power Input Positive Power
Supply
These pins must be connected together physically as close as
possible and directly soldered down to a wide, thick, low
resistance supply plane on the PCB.
7-9 10, 11 OUT1 Power
Output
H-Bridge Output 1 H-Bridge A source of HS1 and drain LS1.
Analog Integrated Circuit Device Data
4Freescale Semiconductor
33932
PIN CONNECTIONS
10, 11, 34,
35
12, 13, 42,
43
PGNDA Power
Ground
Power Ground High-current power ground pins must be connected together
physically as close as possible and directly soldered down to a
wide, thick, low resistance ground plane on the PCB. PGNDA
should be connected to PGNDB with a low-impedance path.
12, 13, 32,
33
15, 16, 39,
40
PGNDB Power
Ground
Power Ground High-current power ground pins must be connected together
physically as close as possible and directly soldered down to a
wide, thick, low resistance ground plane on the PCB. PGNDB
should be connected to PGNDA with a low-impedance path.
14-16 17, 18 OUT4 Power
Output
H-Bridge Output 4 H-Bridge B Source of HS2 and drain of LS2.
17, 18,
26-28
19, 26, 28,
36
VPWRB Power Input Positive Power
Supply
These pins must be connected together physically as close as
possible and directly soldered down to a wide, thick, low
resistance supply plane on the PCB.
19 20 CCPB Analog
Output
Charge Pump
Capacitor
External reservoir capacitor connection for H-Bridge B internal
charge pump; connected to VPWRB. Allowable values are 30 to
100 nF. Note: This capacitor is required for the proper
performance of the device.
20 23 IN4 Logic Input Input 4 Logic input control of OUT4.
21 24 IN3 Logic Input Input 3 Logic input control of OUT3.
22 25 SFB Logic
Output -
Open Drain
Status Flag B
(Active Low)
H-Bridge B open drain active LOW Status Flag output (requires
an external pull-up resistor to VDD. Maximum permissible load
current < 0.5 mA. Maximum VSFLOW < 0.4 V at 0.3 mA. Maximum
permissible pull-up voltage < 7.0 V.)
23 30 D3 Logic Input Disable Input 3
(Active High)
When D3 is logic HIGH, both OUT3 and OUT4 are tri-stated.
Schmitt trigger input with ~80 A source so default condition =
disabled.
24 31 FBB Analog
Output
Feedback B H-Bridge B load current feedback output provides ground
referenced 0.24% of the high side output current. (Tie to GND
through a resistor if not used.)
25 32 EN/D4 Logic Input Enable Input When EN/D4 is logic HIGH, H-Bridge B is operational. When EN/
D4 is logic LOW, the H-Bridge B outputs are tri-stated and H-
Bridge B is placed in Sleep Mode. (logic input with ~ 80A sink so
default condition = Sleep Mode.)
29-31 37, 38 OUT3 Power
Output
H-Bridge Output 3 H-Bridge B Source of HS1 and drain of LS1.
36-38 44, 45 OUT2 Power
Output
H-Bridge Output 2 H-Bridge A source of HS2 and drain of LS2.
41 47 CCPA Analog
Output
Charge Pump
Capacitor
External reservoir capacitor connection for H-Bridge A internal
charge pump; connected to VPWRA. Allowable values are 30 to
100 nF. Note: This capacitor is required for the proper
performance of the device.
42 50 IN2 Logic Input Input 2 Logic input control of OUT2.
43 51 IN1 Logic Input Input 1 Logic input control of OUT1; e.g., when IN1 is logic HIGH, OUT1
is set to VPWRA, and when IN1 is logic LOW, OUT1 is set to
PGNDA. (Schmitt trigger Input with ~ 80 A source so default
condition = OUT1 HIGH.)
Table 1. 33932 Pin Definitions (continued)
Pin
HSOP
(VW)
Pin
SOICW-EP
(EK)
Pin Name Pin
Function Formal Name Definition
Analog Integrated Circuit Device Data
Freescale Semiconductor 5
33932
PIN CONNECTIONS
44 52 SFA Logic
Output -
Open Drain
Status Flag
(Active Low)
H-Bridge A open drain active LOW Status Flag output (requires
an external pull-up resistor to VDD. Maximum permissible load
current < 0.5 mA. Maximum VSFLOW< 0.4 V at 0.3 mA. Maximum
permissible pull-up voltage < 7.0 V.)
TAB 54
27
AGNDA
AGNDB
Analog
Ground
Analog Signal
Ground
The low-current analog signal ground must be connected to
PGND via low-impedance path (<10 m, 0 Hz to 20 kHz).
–2, 6 - 8, 14,
21, 22, 29,
33 - 35, 41,
48, 49
NC None No Connect These pins have no electrical connection or function.
–EP EP Thermal
Pad
Exposed Pad Exposed TAB is also the main heatsinking path for the device and
must be connected to ground.
Table 1. 33932 Pin Definitions (continued)
Pin
HSOP
(VW)
Pin
SOICW-EP
(EK)
Pin Name Pin
Function Formal Name Definition
Analog Integrated Circuit Device Data
6Freescale Semiconductor
33932
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device. These parameters are not production tested.
Ratings Symbol Value Unit
ELECTRICAL RATINGS
Power Supply Voltage
Normal Operation (Steady-state)
Transient Over-voltage(1)
PWR(SS)
PWR(T)
- 0.3 to 28
- 0.3 to 40
V
Logic Input Voltage(2) VIN - 0.3 to 7.0 V
SFA, SFB Output(3) V
SF - 0.3 to 7.0 V
Continuous Output Current(4) IOUT(CONT) 5.0 A
ESD Voltage(5)
Human Body Model
Machine Model
Charge Device Model
Corner Pins
All Other Pins
VESD1
VESD2
± 2000
± 200
±750
±500
V
THERMAL RATINGS
Storage Temperature TSTG - 65 to 150 C
Operating Temperature(6)
Ambient
Junction
TA
TJ
- 40 to 125
- 40 to 150
C
Peak Package Reflow Temperature During Reflow(7), (8) TPPRT Note 8 °C
Approximate Junction-to Case Thermal Resistance(9) RTHJC <1.0 C/W
Notes
1. Device will survive repetitive transient over-voltage conditions for durations not to exceed 500 ms at duty cycle not to exceed 10%.
External protection is required to prevent device damage in case of a reverse battery condition.
2. Exceeding the maximum input voltage on IN1, IN2, IN3, IN4, EN/D2, EN/D4, D1, or D3 may cause a malfunction or permanent damage
to the device.
3. Exceeding the pull-up resistor voltage on the open drain SFA or SFB pin may cause permanent damage to the device.
4. Continuous output current capability is dependent on sufficient package heatsinking to keep junction temperature 150 C.
5. ESD testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 ), Machine Model (CZAP = 200 pF,
RZAP = 0 ), and the Charge Device Model (CDM), Robotic (CZAP = 4.0 pF).
6. The limiting factor is junction temperature, taking into account the power dissipation, thermal resistance, and heat sinking provided. Brief
non-repetitive excursions of junction temperature above 150 C can be tolerated, provided the duration does not exceed 30 seconds
maximum. (Non-repetitive events are defined as not occurring more than once in 24 hours.)
7. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
8. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes
and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
9. Exposed heatsink pad plus the power and ground pins comprise the main heat conduction paths. The actual RJB (junction-to-PC board)
values will vary depending on solder thickness and composition and copper trace thickness and area. Maximum current at maximum
die temperature represents ~16 W of conduction loss heating in the diagonal pair of output MOSFETs. Therefore, the RJA must be
< 5.0 C/W for maximum current at 70 C ambient. Module thermal design must be planned accordingly.
V
V
Analog Integrated Circuit Device Data
Freescale Semiconductor 7
33932
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics
Characteristics noted under conditions 5.0 V VPWR 28 V, - 40 C TA 125C, GND = 0 V, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Specifications given for H-Bridge A apply symmetrically to H-Bridge B.
Characteristic Symbol Min Typ Max Unit
POWER INPUTS (VPWR)
Operating Voltage Range(10)
Steady-state
Transient (t < 500 ms)(11)
VPWR(SS)
VPWR(t)
5.0
–
–
–
28
40
V
Sleep State Supply Current(12)
EN/D2 = Logic [0], IN1, IN2, D1 = Logic [1], and IOUT = 0 A
IPWR(SLEEP)
– – 50
A
Standby Supply Current (Part Enabled)
IOUT = 0 A, VEN = 5.0 V
IPWR(STANDBY)
– – 20
mA
Under-voltage Lockout Thresholds
VPWR(FALLING)
VPWR(RISING)
Hysteresis
VUVLO(ACTIVE)
VUVLO(INACTIVE)
VUVLO(HYS)
4.15
–
150
–
–
200
–
5.0
350
V
V
mV
CHARGE PUMP
Charge Pump Voltage (CP Capacitor = 33 nF), No PWM
VPWR = 5.0 V
VPWR = 28 V
VCP - VPWR
3.5
–
–
–
–
12
V
Charge Pump Voltage (CP Capacitor = 33 nF), PWM = 11 kHz
VPWR = 5.0 V
VPWR = 28 V
VCP - VPWR
3.5
–
–
–
–
12
V
CONTROL INPUTS
Operating Input Voltage (IN1, IN2, D1, EN/D2, IN3, IN4, D3, EN/D4)VI– – 5.5 V
Input Voltage (IN1, IN2, D1, EN/D2, IN3, IN4, D3, EN/D4)
Logic Threshold HIGH
Logic Threshold LOW
Hysteresis
VIH
VIL
VHYS
2.0
–
250
–
–
400
–
1.0
–
V
V
mV
Logic Input Currents, VPWR = 8.0 V
Input EN/D2, EN/D4 (internal pull-downs), VIH = 5.0 V
Inputs IN1, IN2, D1, IN3, IN4, D3 (internal pull-ups), VIL = 0 V
IIN
20
-200
80
-80
200
-20
A
Notes
10. Device specifications are characterized over the range of 8.0 V VPWR 28 V. Continuous operation above 28 V may degrade device
reliability. Device is operational down to 5.0V, but below 8.0 V the output resistance may increase by 50 percent.
11. Device will survive the transient over-voltage indicated for a maximum duration of 500 ms. Transient not to be repeated more than once
every 10 seconds.
12. IPWR(SLEEP) is with Sleep Mode activated and EN/ D2, = logic [0], and IN1, IN2, D1 = logic [1] or with these inputs left floating.
Analog Integrated Circuit Device Data
8Freescale Semiconductor
33932
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
POWER OUTPUTS OUT1, OUT2
Output-ON Resistance(14), ILOAD = 3.0 A
VPWR = 8.0 V, TJ = 25 C
VPWR = 8.0 V, TJ = 150 C
VPWR = 5.0 V, TJ = 150 C
RDS(ON)
–
–
–
120
–
–
–
235
325
m
Output Current Regulation Threshold
TJ < TFB
TJ TFB (Fold back Region - see Figure 9 and Figure 11)(13)
ILIM
5.2
–
6.5
4.2
8.0
–
A
High Side Short-circuit Detection Threshold (Short-circuit to Ground)(13) ISCH 11 13 16 A
Low Side Short-circuit Detection Threshold (Short-circuit to VPWR)(13) ISCL 9.0 11 14 A
Output Leakage Current(15), Outputs off, VPWR = 28 V
VOUT = VPWR
VOUT = Ground
IOUTLEAK
–
-60
–
–
100
–
A
Output MOSFET Body Diode Forward Voltage Drop, IOUT = 3.0 A VF– – 2.0 V
Over-temperature Shutdown(13)
Thermal Limit at TJ
Hysteresis at TJ
TLIM
THYS
175
–
–
12
200
–
C
Current Foldback at TJ(13) TFB 165 –185 C
Current Foldback to Thermal Shutdown Separation(13) TSEP 10 –15 C
HIGH SIDE CURRENT SENSE FEEDBACK
Feedback Current (pin FB sourcing current)(16)
I OUT = 0.0 mA
I OUT = 300 mA
I OUT = 500 mA
I OUT = 1.5 A
I OUT = 3.0 A
I OUT = 6.0 A
I FB
0.0
0.0
0.35
2.86
5.71
11.43
–
270
0.775
3.57
7.14
14.29
50
750
1.56
4.28
8.57
17.15
A
A
mA
mA
mA
mA
STATUS FLAG(17)
Status Flag Leakage Current(18)
V SF = 5.0 V
ISFLEAK
– – 5.0
A
Status Flag SET Voltage(19)
I
SF = 300 µA
VSFLOW
– – 0.4
V
Notes
13. This parameter is Guaranteed By Design.
14. Output-ON resistance as measured from output to VPWR and from output to GND.
15. Outputs switched OFF via D1 or EN/D2.
16. Accuracy is better than 20% from 0.5 A to 6.0 A. Recommended terminating resistor value: RFB = 270 
17. Status Flag output is an open drain output requiring a pull-up resistor to logic VDD.
18. Status Flag Leakage Current is measured with Status Flag HIGH and not SET.
19. Status Flag Set Voltage measured with Status Flag LOW and SET with I SF = 300 A. Maximum allowable sink current from this pin is
< 500 A . Maximum allowable pull-up voltage < 7.0 V.
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 5.0 V VPWR 28 V, - 40 C TA 125C, GND = 0 V, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Specifications given for H-Bridge A apply symmetrically to H-Bridge B.
Characteristic Symbol Min Typ Max Unit
Analog Integrated Circuit Device Data
Freescale Semiconductor 9
33932
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 5.0 V VPWR 28 V, - 40C TA 125C, GND = 0 V, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
TIMING CHARACTERISTICS
PWM Frequency(20) f
PWM – – 11 kHz
Maximum Switching Frequency During Current Limit Regulation(21) f
MAX – – 20 kHz
Output ON Delay(22)
PWR V
t
DON
– – 18
s
Output OFF Delay(22)
PWR V
t
DOFF
– – 12
s
ILIM Output Constant-OFF Time(23) (25) t
A15 20.5 32 s
ILIM Blanking Time(24) (25) t
B12 16.5 27 s
Disable Delay Time(26) t
DDISABLE – – 8.0 s
Output Rise and Fall Time(27) t
F, t
R1.5 3.0 8.0 s
Short-circuit / Over-temperature Turn-OFF (Latch-OFF) Time(28), (29) t
FAULT – – 8.0 s
Power-ON Delay Time(29) t
POD –1.0 5.0 ms
Output MOSFET Body Diode Reverse Recovery Time(29) t
R R 75 100 150 ns
Charge Pump Operating Frequency(29) fCP –7.0 –MHz
Notes
20. The maximum PWM frequency should be limited to frequencies < 11 kHz in order to allow the internal high side driver circuitry time to
fully enhance the high side MOSFETs.
21. The internal current limit circuitry produces a constant-OFF-time Pulse Width Modulation of the output current. The output load’s
inductance, capacitance, and resistance characteristics affect the total switching period (OFF-time + ON-time), and thus the PWM
frequency during current limit.
22. * Output Delay is the time duration from 1.5 V on the IN1 or IN2 input signal to the 20% or 80% point (dependent on the transition direction)
of the OUT1 or OUT2 signal. If the output is transitioning HIGH-to-LOW, the delay is from 1.5 V on the input signal to the 80% point of
the output response signal. If the output is transitioning LOW-to-HIGH, the delay is from 1.5 V on the input signal to the 20% point of the
output response signal. See Figure 4, page 10.
23. The time during which the internal constant-OFF time PWM current regulation circuit has tri-stated the output bridge.
24. The time during which the current regulation threshold is ignored so that the short-circuit detection threshold comparators may have time
to act.
25. Parameter guaranteed by characterization.
26. * Disable Delay Time measurement is defined in Figure 5, page 10.
27. Rise Time is from the 10% to the 90% level and Fall Time is from the 90% to the 10% level of the output signal with VPWR
RLOAD = 3.0 ohm. See Figure 6, page 10.
28. Load currents ramping up to the current regulation threshold become limited at the ILIM value (see Figure 7). The short-circuit currents
possess a di/dt that ramps up to the ISCH or ISCL threshold during the ILIM blanking time, registering as a short-circuit event detection and
causing the shutdown circuitry to force the output into an immediate tri-state latch-OFF (see Figure 8). Operation in Current Limit mode
may cause junction temperatures to rise. Junction temperatures above ~160 C will cause the output current limit threshold to “fold back”,
or decrease, until ~175 C is reached, after which the tLIM thermal latch-OFF will occur. Permissible operation within this fold back region
is limited to non-repetitive transient events of duration not to exceed 30 seconds (see Figure 9).
29. Parameter is Guaranteed By Design.
V = 14
V = 14
= 14 V,
Analog Integrated Circuit Device Data
10 Freescale Semiconductor
33932
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TIMING DIAGRAMS
5.0
VPWR
0
0
TIME
1.5 V 1.5 V
20%
80%
tDON
VOUT1, 2 (V) VIN1, IN2 (V)
tDOFF
Figure 4. Output Delay Time
0V
5.0 V
V
VOUT1, 2 VD1, EN/D2 (V)
TIME
1.5 V
tDDISABLE
90%
IO = 100 mA
Figure 5. Disable Delay Time
.
90% 90%
10% 10%
VOUT1, 2 (V)
tFtR
VPWR
0
TIME
Figure 6. Output Switching Time
ISC Short-circuit Detection Threshold
IOUT, CURRENT (A)
tB
5.0
tA
9.0
0.0
ILIM
6.5
tB = ILIM Blanking Time
t
A
= Constant-OFF Time (OUT1 and OUT2 Tri-stated)
Overload Condition
tON TIME
Figure 7. Current Limit Blanking Time and Constant-OFF Time
ISC Short-circuit Detection Threshold
IOUT, CURRENT (A)
5.0
9.0
0.0
ILIM
6.5
Hard Short Occurs
tFAULT
Short-circuit Condition
tB(~16 s)
tB
TIME
SF set Low
OUT1, OUT2 Tri-stated,
Analog Integrated Circuit Device Data
Freescale Semiconductor 11
33932
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
Figure 8. Short-circuit Detection Turn-OFF Time tFAULT
.
Current Limit Threshold Foldback.
ILIM, CURRENT (A)
6.5
4.2
t
LIM
t
FB
t
HYS
t
SEP
t
LIM
Thermal Shutdown
Operation within this region must be
limited to non-repetitive events not to
exceed 30 s per 24 hr.
Figure 9. Output Current Limiting Foldback Region
Analog Integrated Circuit Device Data
12 Freescale Semiconductor
33932
FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 33932 has two identical H-Bridge drivers in the same
package. The only connection that is shared internally is the
Analog Ground (AGND). This description is given for the H-
Bridge A half of the total device. However, the H-Bridge B half
will exhibit identical behavior.
Numerous protection and operational features (speed,
torque, direction, dynamic breaking, PWM control, and
closed-loop control) make the 33932 a very attractive, cost-
effective solution for controlling a broad range of small DC
motors. The 33932 outputs are capable of supporting peak
DC load currents of up to 5.0 A from a 28 V VPWR source. An
internal charge pump and gate drive circuitry are provided
that can support external PWM frequencies up to 11 kHz.
The 33932 has an analog feedback (current mirror) output
pin (the FB pin) that provides a constant-current source
ratioed to the active high side MOSFETs’ current. This can be
used to provide “real time” monitoring of output current to
facilitate closed-loop operation for motor speed/torque
control, or for the detection of open load conditions.
Two independent inputs, IN1 and IN2, provide control of
the two totem-pole half-bridge outputs. Two independent
disable inputs, D1 and EN/D2, provide the means to force the
H-bridge outputs to a high-impedance state (all H-bridge
switches OFF). The EN/D2 pin also controls an enable
function that allows the IC to be placed in a power-conserving
Sleep mode.
The 33932 has output current limiting (via constant OFF-
time PWM current regulation), output short-circuit detection
with latch-OFF, and over-temperature detection with latch-
OFF. Once the device is latched-OFF due to a fault condition,
either of the disable inputs (D1 or EN/D2), or VPWR must be
“toggled” to clear the status flag.
Current limiting (Load Current Regulation) is
accomplished by a constant-OFF time PWM method using
current limit threshold triggering. The current limiting scheme
is unique in that it incorporates a junction temperature-
dependent current limit threshold. This means that the
current limit threshold is “reduced to around 4.2 A” as the
junction temperature increases above 160 °C. When the
temperature is above 175 °C, over-temperature shutdown
(latch-OFF) will occur. This combination of features allows
the device to continue operating for short periods of time (< 30
seconds) with unexpected loads, while still retaining
adequate protection for both the device and the load.
FUNCTIONAL PIN DESCRIPTION
POWER GROUND AND ANALOG GROUND
(PGND AND AGND)
The power and analog ground pins should be connected
together with a very low-impedance connection.
POSITIVE POWER SUPPLY (VPWR)
VPWR pins are the power supply inputs to the device. All
VPWR pins must be connected together on the printed circuit
board with as short as possible traces, offering as low an
impedance as possible between pins.
STATUS FLAG (SF)
This pin is the device fault status output. This output is an
active LOW open drain structure requiring a pull-up resistor
to VDD. The maximum VDD is < 7.0 V. Refer to Table 5, Truth
Table, for the SF Output status definition.
INPUT 1,2 AND DISABLE INPUT 1
(IN1, IN2, AND D1)
These pins are input control pins used to control the
outputs. These pins are 3.0 V/ 5.0 V CMOS-compatible
inputs with hysteresis. IN1 and IN2 independently control
OUT1 and OUT2, respectively. D1 input is used to tri-state
disable the H-Bridge outputs.
When D1 is SET (D1 = logic HIGH) in the disable state,
outputs OUT1 and OUT2 are both tri-state disabled; however,
the rest of the device circuitry is fully operational and the
supply IPWR(STANDBY) current is reduced to a few mA. Refer
to Table 3, Static Electrical Characteristics.
H-BRIDGE OUTPUT (OUT1, OUT2)
These pins are the outputs of the H-bridge with integrated
free-wheeling diodes. The bridge output is controlled using
the IN1, IN2, D1, and EN/D2 inputs. The outputs have PWM
current limiting above the ILIM threshold. The outputs also
have thermal shutdown (tri-state latch-OFF) with hysteresis
as well as short circuit latch-OFF protection.
A disable timer (time t
B) is incorporated to distinguish
between load currents that are higher than the ILIM threshold
and short circuit currents. This timer is activated at each
output transition.
CHARGE PUMP CAPACITOR (CCP)
This pin is the charge pump output pin and connection for
the external charge pump reservoir capacitor. The allowable
value is from 30 to 100 nF. This capacitor must be connected
from the CCP pin to the VPWR pin. The device cannot
operate properly without the external reservoir capacitor.
Analog Integrated Circuit Device Data
Freescale Semiconductor 13
33932
FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
ENABLE INPUT/DISABLE INPUT 2 (EN/D2)
The EN/D2 pin performs the same function as D1 pin,
when it goes to a logic LOW the outputs are immediately tri-
stated. It is also used to place the device in a Sleep mode so
as to consume very low currents. When the EN/D2 pin
voltage is a logic LOW state, the device is in the Sleep mode.
The device is enabled and fully operational when the EN pin
voltage is logic HIGH. An internal pull-down resistor
maintains the device in Sleep mode in the event EN is driven
through a high-impedance I/O or an unpowered
microcontroller, or the EN/D2 input becomes disconnected.
FEEDBACK (FB)
The 33932 has a feedback output (FB) for “real time”
monitoring of H-Bridge high side output currents to facilitate
closed-loop operation for motor speed and torque control.
The FB pin provides current sensing feedback of the
H-Bridge high side drivers. When running in the forward or
reverse direction, a ground-referenced 0.24% of load current
is output to this pin. Through the use of an external resistor to
ground, the proportional feedback current can be converted
to a proportional voltage equivalent and the controlling
microcontroller can “read” the current proportional voltage
with its analog-to-digital converter (ADC). This is intended to
provide the user with only first-order motor current feedback
for motor torque control. The resistance range for the linear
operation of the FB pin is 100 < RFB < 300 .
If PWM-ing is implemented using the disable pin input
(only D1), a small filter capacitor (~1.0 µF) may be required
in parallel with the RFB resistor to ground for spike
suppression
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
MC33932 - Functional Block Diagram
Analog Control & Protection H-Bridge Output Drivers
Analog Control & Protection
H-Bridge
Output Drivers
Gate Control Logic
Fault Logic
OUT1 - OUT2
Logic and Control
Protection Logic Control
Input Logic Control
Temperature Sense Charge Pump
Voltage Regulation
Current Sense
MCU Interface
Figure 10. Functional Internal Block Diagram
ANALOG CONTROL AND PROTECTION
CIRCUITRY:
An on-chip voltage regulator supplies the internal logic.
The charge pump provides gate drive for the H-Bridge
MOSFETs. The Current and Temperature sense circuitry
provides detection and protection for the output drivers.
Output under-voltage protection shuts down the MOSFETS.
GATE CONTROL LOGIC:
The 33932 is a monolithic H-Bridge Power IC designed
primarily for any low-voltage DC servo motor control
application within the current and voltage limits stated for the
device. Two independent inputs provide polarity control of
two half-bridge totem-pole outputs. Two independent disable
inputs are provided to force the H-Bridge outputs to tri-state
(high-impedance off-state).
H-BRIDGE OUTPUT DRIVERS: OUT1 AND OUT2
The H-Bridge is the power output stage. The current flow
from OUT1 to OUT2 is reversible and under full control of the
user by way of the Input Control Logic. The output stage is
designed to produce full load control under all system
conditions. All protective and control features are integrated
into the control and protection blocks. The sensors for current
and temperature are integrated directly into the output
MOSFET for maximum accuracy and dependability.
Analog Integrated Circuit Device Data
14 Freescale Semiconductor
33932
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Figure 11. Operating States
Analog Integrated Circuit Device Data
Freescale Semiconductor 15
33932
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS
LOGIC COMMANDS
Table 5. Truth Table
The tri-state conditions and the status flag are reset using D1 or D2. The truth table uses the following notations: L = LOW, H =
HIGH, X = HIGH or LOW, and Z = High-impedance. All output power transistors are switched off.
Device State
Input Conditions Status Outputs
EN/D2 D1 IN1 IN2 SF OUT1 OUT2
Forward H L H L H H L
Reverse H L L H H L H
Freewheeling Low H L L L H L L
Freewheeling High HL HHHHH
Disable 1 (D1) H H X X L Z Z
IN1 Disconnected H L Z X H H X
IN2 Disconnected H L X Z H X H
D1 Disconnected H Z X X L Z Z
Under-voltage Lockout(30) H X X X L Z Z
Over-temperature(31) H X X X L Z Z
Short-circuit(31) H X X X L Z Z
Sleep mode EN/D2 L X X X H Z Z
EN/D2 disconnected Z X X X H Z Z
Notes
30. In the event of an under-voltage condition, the outputs tri-state and status flag is SET logic LOW. Upon under-voltage
recovery, status flag is reset automatically or automatically cleared and the outputs are restored to their original operating
condition.
31. When a short-circuit or over-temperature condition is detected, the power outputs are tri-state latched-OFF independent of
the input signals and the status flag is latched to logic LOW. To reset from this condition requires the toggling of either D1,
EN/D2, or VPWR.
OUT1 OUT2
PGND
VPWR VPWR
PGND
LOAD
Load
Current
Forward
OFF
ON
ON
OFF
OUT1 OUT2
PGND
OFF
ON
ON
OFF
VPWR VPW R
PGND
LOAD
Load
Current
Reverse
OUT1 OUT2
PGND
VPWR VPWR
PGND
LOAD
Load
Current
High-Side Recirculation
(Forward)
ON
OFF
ON
OFF
OUT1 OUT2
PGND
VPWR VPWR
PGND
LOAD
Load
Current
Low-Side Recirculation
(Forward)
ON ON
OFF OFF
Figure 12. 33932 Power Stage Operation
Analog Integrated Circuit Device Data
16 Freescale Semiconductor
33932
FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSTIC FEATURES
PROTECTION AND DIAGNOSTIC FEATURES
SHORT-CIRCUIT PROTECTION
If an output short-circuit condition is detected, the power
outputs tri-state (latch-OFF) independent of the input (IN1
and IN2) states, and the fault status output flag (SF) is SET
to logic LOW. If the D1 input changes from logic HIGH to logic
LOW, or if the EN/D2 input changes from logic LOW to logic
HIGH, the output bridge will become operational again and
the fault status flag will be reset (cleared) to a logic HIGH
state.
The output stage will always switch into the mode defined
by the input pins (IN1, IN2, D1, and EN/D2), provided the
device junction temperature is within the specified operating
temperature range.
INTERNAL PWM CURRENT LIMITING
The maximum current flow under normal operating
conditions should be less than 5.0 A. The instantaneous load
currents will be limited to ILIM via the internal PWM current
limiting circuitry. When the ILIM threshold current value is
reached, the output stages are tri-stated for a fixed time (T
A)
of 20 µs typical. Depending on the time constant associated
with the load characteristics, the output current decreases
during the tri-state duration until the next output ON cycle
occurs.
The PWM current limit threshold value is dependent on the
device junction temperature. When - 40 °C < TJ < 160 °C, ILIM
is between the specified minimum/maximum values. When
TJ exceeds 160 °C, the ILIM threshold decreases to 4.2 A.
Shortly above 175 °C the device over-temperature circuit will
detect tLIM and an over-temperature shutdown will occur. This
feature implements a graceful degradation of operation
before thermal shutdown occurs, thus allowing for
intermittent unexpected mechanical loads on the motor’s
gear-reduction train to be handled.
Important Die temperature excursions above 150 C are
permitted only for non-repetitive durations < 30 seconds.
Provision must be made at the system level to prevent
prolonged operation in the current-foldback region.
OVER-TEMPERATURE SHUTDOWN AND
HYSTERESIS
If an over-temperature condition occurs, the power outputs
are tri-stated (latched-OFF) and the fault status flag (SF) is
SET to logic LOW.
To reset from this condition, D1 must change from logic
HIGH to logic LOW, or EN/D2 must change from logic LOW
to logic HIGH. When reset, the output stage switches ON
again, provided that the junction temperature is now below
the over-temperature threshold limit minus the hysteresis.
Important Resetting from the fault condition will clear the
fault status flag. Powering down and powering up the device
will also reset the 33932 from the fault condition.
OUTPUT AVALANCHE PROTECTION
If VPWR were to become an open circuit, the outputs
would likely tri-state simultaneously due to the disable logic.
This could result in an unclamped inductive discharge. The
VPWR input to the 33932 should not exceed 40 V during this
transient condition, to prevent electrical overstress of the
output drivers.This can be accomplished with a zener clamp
or MOV, and/or an appropriately valued input capacitor with
sufficiently low ESR (see Figure 13).
OUT1
OUT2
I/Os
AGND PGND
Bulk
Low ESR
Cap.
VPWR
100nF
M
VPWR
9
Figure 13. Avalanche Protection
Analog Integrated Circuit Device Data
Freescale Semiconductor 17
33932
TYPICAL APPLICATIONS
INTRODUCTION
TYPICAL APPLICATIONS
INTRODUCTION
A typical application schematic is shown in Figure 14. For
precision high-current applications in harsh, noisy
environments, the VPWR by-pass capacitor may need to be
substantially larger.
VDD
LOGIC SUPPLY
CHARGE
PUMP
GATE DRIVE
AND
PROTECTION
LOGIC CURRENT MIRRORS
AND
CONSTANT OFF-TIME
PWM CURRENT REGULATOR
VCP
CCPA OUT1
OUT2
AGNDA
TO GATES
HS1
LS1
HS2
LS2
VPWRA
VSENSE
ILIM PWM
HS1 HS2
LS1 LS2LS2
IN1
IN2
EN/D2
D1
SFA
FBA
PGNDA
+5.0 V
RFB
270
STATUS
FLAG
TO
ADC
1.0 F
33 nF
VPWR
100 nF
100 F
M
PGND
Figure 14. 33932 Typical Application Schematic 1/2 Device
Analog Integrated Circuit Device Data
18 Freescale Semiconductor
33932
PACKAGING
PACKAGE DIMENSIONS
PACKAGING
PACKAGE DIMENSIONS
For the most current package revision, visit www.freescale.com and perform a keyword search using the 98Axxxxxxxxx listed
below. Dimensions shown are provided for reference ONLY.
VW SUFFIX
44-PIN
98ARH98330A
REVISION B
VW SUFFIX
44-PIN
98ARH98330A
REVISION B
Analog Integrated Circuit Device Data
Freescale Semiconductor 19
33932
PACKAGING
PACKAGE DIMENSIONS
EK SUFFIX
54-PIN
98ASA99334D
REVISION C
Analog Integrated Circuit Device Data
20 Freescale Semiconductor
33932
PACKAGING
PACKAGE DIMENSIONS
EK SUFFIX
54-PIN
98ASA99334D
REVISION C
Analog Integrated Circuit Device Data
Freescale Semiconductor 21
33932
PACKAGING
PACKAGE DIMENSIONS
EK SUFFIX
54-PIN
98ASA99334D
REVISION C
Analog Integrated Circuit Device Data
22 Freescale Semiconductor
33932
PACKAGING
PACKAGE DIMENSIONS
Analog Integrated Circuit Device Data
Freescale Semiconductor 23
33932
ADDITIONAL DOCUMENTATION
PACKAGE DIMENSIONS
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM
Introduction
This thermal addendum is provided as a supplement to the MC33932 technical datasheet. The addendum provides thermal
performance information that may be critical in the design and development of system applications. All electrical, application, and
packaging information is provided in the datasheet.
Package and Thermal Considerations
The MC33932 is offered in a 54-pin SOICW-EP and a 44-pin HSOP single die package. There is a single heat source (P), a
single junction temperature (TJ), and thermal resistance (RJA). This thermal addendum is specific to the 54-pin SOICW-EP
package.
TJ=RJA .P
The stated values are solely for a thermal performance comparison of one package to another in a standardized environment.
This methodology is not meant to, and will not predict the performance of a package in an application-specific environment.
Stated values were obtained by measurement and simulation according to the standards listed below.
Table 6. Table of Thermal Resistance Data
Rating Value Unit Notes
Junction to Ambient
Natural Convection
Single Layer board (1s) RJA 58.8 °C/W (32),(33)
Junction to Ambient
Natural Convection
Four layer board (2s2p) RJA 24.4 °C/W (32),(34)
Junction to Board RJB 7.0 °C/W (35)
Junction to Case (bottom / flag) RJC (bottom) 0.36 °C/W (38)
Junction to Case (top) RJC (top) 18 °C/W (36)
Junction to Package Top Natural Convection JT 2.0 °C/W (37)
Notes
32. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature,
ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
33. Per JEDEC JESD51-2 with the single layer board (JESD51-3) horizontal.
34. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.
35. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top
surface of the board near the package.
36. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).
37. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per
JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.
38. Thermal resistance between the die and the case bottom / flag surface (simulated) (flag bottom side fixed to ambient temperature).
Analog Integrated Circuit Device Data
24 Freescale Semiconductor
33932
THERMAL ADDENDUM
PACKAGE DIMENSIONS
Figure 15. Transient Thermal Resistance RJA MC33932EK on 2s2p Test Board
Analog Integrated Circuit Device Data
Freescale Semiconductor 25
33932
REFERENCE SECTION
PACKAGE DIMENSIONS
REFERENCE SECTION
Table 7. Thermal Analysis Reference Documents
Reference Description
AN4146 Thermal Modeling and Simulation of 12V Gen3 eXtreme Switch Devices with SPICE
BASICTHERMALWP Basic Principles of Thermal Analysis for Semiconductor Systems
Analog Integrated Circuit Device Data
26 Freescale Semiconductor
33932
REVISION HISTORY
REVISION HISTORY
REVISION DATE DESCRIPTION
1.0 8/2007 • Initial Release
2.0 8/2008 • Added parameters (TBD) for Change Pump Voltages in Table 3
3.0 11/2008 • Changed maximum RDS(ON) from 225 to 235 m
• Changed Peak Package Reflow Temperature During Reflow(7), (8)
• Changed Approximate Junction-to Case Thermal Resistance(9)
4.0 6/2012 • Added PC33932EK to the Ordering Information Table
• Added EK ordering information
• Form and style corrections
• Added note 25
• Added Thermal Addendum and Reference Document sections
• Added 98ASA99334D package drawing
• Minor corrections throughout the spec
5.0 10/2012 • PC33932EK changed to MC33932EK and released to production
• Document level changed from Advance Information to Technical Data
• Changed SOIC to SOICW-EP
Analog Integrated Circuit Device Data
Freescale Semiconductor 27
33932
REVISION HISTORY
Document Number: MC33932
Rev. 5.0
10/2012
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