Crystal Oscillator Topics - Cypress Semiconductor

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Crystal Oscillator Topics

Introduction

A PLL-base d frequency synthes izer uses a referen ce inp ut to

generate output clocks. The reference can be pro vided by a

quartz crystal or an external clock source. The accuracy and

stability of the output clocks in a PLL-based frequency syn-

thesizer are directly proportional to those of the reference.

Thus, it is important to provide a stable, accurate, and appro-

priate reference input. This application note describes the

recommend ed reference inputs for Cypres s’s PLL-based f re-

quency synthesizers, and concludes with an error budget

analysis.

Pleas e note that this application note applies only to Cypress

Frequency Synthesizers and not t o Cypre ss Clock Buffers.

Please note that this application note does not apply to the

ICD6233 (one-time programmable clock oscillator), the

CY2305/8/9 Zero Delay Buffers or the CY7B991/2 and

CY7B9910/20 (RoboClock and RoboCl ock Jr.). For applica-

tions assistance on CY7B991/2 and CY7B9910/20, see the

application note “Everything You Need to Know About

CY7B991/2 (RoboClock) But Were Afraid to Ask.” For a ppli-

cation assistance on the CY2305/8/9, refer to the application

notes

Cypress’s PLL-Based Frequency Synthesizers

Figure 1

shows the block diagram of a typical PLL-based f re-

quency synthesizer. Note that the reference input to all PLLs

comes from an on-chip crystal oscillator, which is the archi-

tecture of all Cypress clock generat ors.

Figure 2

shows the circuitry of the on-chip crystal oscillator

(a.k.a. Pierce oscillator ), which is formed by components R,

G, Ci and Co, wh ere G is a li near inverter. For t his circuit to

produce an electrical clock, a quartz crystal needs to be con-

nected betw een the XTALIN and XTALOUT pins.

The equivalent cir cui t of a Quartz crystal is shown in

Figure

. Co is the s hunt or stati c capacitance of the cry stal. R1 is

the motional resistance, L1 is the motional inductance, and

C1 is the motional capacitance of the crystal. R1, L1 and C1

are determined by the mechanical properties of the crystal

(they are in the motional arm of the crystal and their circuit

ef fe cts o nly e xis t when the crystal is oscillating). The e ffective

reactance curve of t he cry stal is shown in

Figure 4

REFERENCE

CRYSTAL

OSCILLATOR

XTALIN

XTALOUT PLLs DIVIDERS OUTPUTS

INTERNAL TO DEVICE

Figure 1. Typical PLL-based Frequency Synthesizer

XTALIN XTALOUT

INTERNAL TO DEVICE

CiCo

Figure 2. On-Chip Crystal Oscillator Circuitry

R1 L1 C1

Figure 3. Equivalent Circuit of a Quartz Crystal

Inductive

Capacitive

Frequency

Reactance

Area of parallel

resonance

crystal bandwidth

Figure 4. Crystal Reactance v/s Frequency

Crystal Oscillator Topics

When connected as a feedback element in a oscillator circuit

that has a no phase shift (O°), the crystal oscillates at the

series resonating f requency (fs) given by

Eq. 1

A Pierce oscillator has a 180° phas e s h i ft o n the amplifier and

needs another 180° p hase shift from the feedback element.

The feedback element in this case is a crystal along with a

capacitive load, and the frequency of oscillation of the crystal

(and oscillator circuit) is in the “area of parallel resonance”.

The actual value of the crystal oscillator parallel resonating

fre quency is dependent on the capacitive load ing seen by th e

crystal and is given by

Eq. 2

where

= Capacitive loading seen by the crystal.

For e xample, a 14.318 MHz parallel reso nant crystal tuned to

a Cload = 18 pF will oscillate at 14.318 MHz (not including

tolerance) when it is placed in a Pierce oscillator (parallel os-

cillator) circuit whi ch offers a capaciti ve loading CL=18 pF. If

the capacitive loading seen by the crystal in the Pierce oscil-

lator circuit were different from the rated Cload, the change in

frequency from the rated frequency is given in

Equation 3

Eq. 3

p(rated)

= frequency rati ng of crystal

p(actual)

= actual frequency of oscillation in oscillator circuit

load

= C apacitive loading rating of crystal

= Capacitiv e loading seen by crystal in oscillator circuit .

If a series resonant crystal (which is simply a crystal whose

rated frequency is fs) is used in a Pierce oscillator circuit, the

frequency of oscillation will be higher than the rated frequency

by about 0.02% or 200 ppm. The actual value of frequency

can be calculated from

Equation 2

Crystals Recommended for Cypress Clock

Generators

Figure 5

shows the required connection of a crystal to an

on-chip oscillator of a PLL-based f requency synthesizer. For

best results, a fundamental mode, parallel resonant crystal

should be used. The load capacitance of this crystal (Cload)

must match the load capacitance of the oscillator circuitry

(CL), as seen by the crystal. As shown in

Figure 5

, under

normal AC conditions, Co will be in series with Ci2. Thus,

Eq. 4

CL = 17 pF. However, if parasit ics are accounted for,

Eq. 5

where ,

which results in CL = 18 pF.

Hence, fundamental mode, parallel-resonant crystals with

Cload = 17 to 18 pF should be used for be st re sul ts w ith C y-

press clock generators. If the Cload of the crystal does not

equal 17 or 18 pF, the output frequency will be somewhat

different from the target. Also, since capa citors Ci2 and Co are

2Π

--------------------------=

+()

----------------------------- 1+







prated

()

–

p actual

()

p rated

()

----------------------------------------------------------

------- 1

Cload

------------------------------- 1

+()

--------------------------–







XTALIN XTALOUT

Co=34 pF

RbG2

Die

Clock

Cload

CRYSTAL

Ci2=34 pF

Parasitic

Capaci tance ≈ 2 pF Parasitic

Capac itance ≈ 2 pF

INTERNAL TO DEVICE

Recomm ended if

Cload > 18 pF

Cext

Figure 5. Using a Crystal as Reference

CLC0Ci2

⋅

C0Ci2

------------------------=

oeq

i2eq

⋅

oeq

i2eq

----------------------------------=

oeq

2pF

i2eq

Crystal Oscillator Topics

on-chip, no additional external components are required for

operation, pro vided a crystal with matched Cload is used.

A Patch for Crystals with an U nmatched Cload

As shown in

Figure 5

, Cypress recommends the addition of

an ex tern al capac it or, Cex t, on or c lose to the XTALOUT pin to

compensate for a Cload > 18 pF. Co and Cext are in parall el,

which, under AC conditions, are in series with Ci2. Solv ing th e

followi ng equatio n for Cext, which accounts for parasitics,

Eq. 6

give s the value of the external capacitor required. For a crys-

tal with Cload=20 pF, Cext = 9 pF would be required.

Note that for Cload < 17 pF, solving

Equatio n 7

(d oes not ac-

count for parasitics) for Cext resu lts in a nega tive capacitance

value.

Eq. 7

Thus, there is no patch available, and the user needs to in-

stead use a crystal with Cload = 17 to 1 8 pF. Us ing a capac itor

in se ries with the XTALIN or XT ALOUT p in will redue the Cload

seen by the crystal, but will ca use start-up pr o blems. This is

because the crystal n eeds to h ave a DC voltage across it to

start os cillations. And if a capacitor is u sed in serie s with t he

XTALIN and XTALOUT pins, this capacitor wil l block any DC

voltage nor mall y applied to the crystal on start-up.

Using a Series Resonant Crystal

In general, using a series resonant crystal with a parallel res-

onant cir cuit will introduce an error on the outp ut frequencies

of t he device. For Cypress’s on-chip oscillator, using a series

re sonant crystal will typically ad d a 50 0 ppm (.05%) error on

the output frequencies. For some a ppli cations, such as ti me

keeping, choosing the right crystal t ype is cru cial. For exam-

ple, a 50 ppm error in the reference frequency produces a real

time clocking error of 2 minutes per month. Thus, the user

must ensure that proper crystals are used w ith Cypress clock

generators.

Special Case: 32.768 kHz Cr ystal

The CY2291 and CY2295 offer intern al parallel resonant os-

cillation circuitry that c an p rodu ce a 32.768-kHz signal, which

is commonly used as a real time clock. Since the internal

circuitry does not have a biasing resistor on-chip, a 10-MΩ

re sistor must be pl a ced in parallel to the 32.7 68-kHz crystal,

as shown in

Figure 6

. Perf or ming the calculations based on

Equation 4

and

Equation 5

results in a crystal requirem ent of

Cload = 12 to 13 pF. If the crystal has Cloa d > 13 pF, then a Cext,

as c al cul at ed fr om

Equation 6

, is needed. If the Cload of the

crystal is le ss than 12 or 13 pF, a capacitor cannot be placed

in series with the 32XIN or 32XOUT pin, as ex plained before.

Using an External Signal Source

Frequently, a fr equency synthesizer is dr iven by an external

signal source rather than a crystal. In this case, the external

clock should be driven in on the XTALIN pin, and the XTA-

LOUT pin must be left floating. Cypress also recommends

using a small c oupling capacitor in seri es with t he sig nal , as

shown i n

Figure 7

. Such a capacitor pr ovides the benefits of

reduced lo ading of the signal source a nd restoration of duty

cycle, as explained below.

Reduced Loading

As shown in

Figure 7

, the two internal capacitors are each 34

pF. Without the coupling capacitor Ci1, the frequency source

is effectively driving Ceff=34 pF (not accounting for parasit-

i2eq

oeq

ext

)

+⋅

i2eq

oeq

ext

)

---------------------------------------------------------=

ext

)

+⋅

ext

+()+

----------------------------------------------=

32XIN 32XOUT

Co=20 pF

TO 32K

OUTPUT

32.768 kHz CRYSTA L

Cload = 12 or 13 pF

Ci2=20 pF

Recommended if

Cload > 13 pF

Cext

10 MΩ

Parasitic

Capacita nce ≈ 2 pF Parasitic

Capacitance ≈ 2 pF

INTERNAL TO DEVICE

Figure 6. Using a 32.768 kHz Crystal

Crystal Oscillator Topics

ics), where Ceff is the effective l oad capacitance seen by the

driver. Ceff is redu ced by the addition of Ci1 in series with Ci2.

Now,

Eq. 8

For example, Ci1=22 pF and Ci2=34 pF results in Ceff=13.4

pF. In this case, Ceff is red uced by 62%, which results in re-

duced loading of the frequency source, reduced power sup ply

noise, and thus im proved signal transition ti mes.

While the load is reduced, so is the amplitude of the signal at

XTAL I N ac cor ding to the foll owing equation:

Eq. 9

Using the same numbers, as in the example above, and set-

ting the input voltage Vi1=5Vpp results in Vi2 = 2Vpp. However ,

the reduction in amplitude is not a problem since the linear

inverter , G1, helps bias and re-amplify the signal. Specifically ,

the DC level of Vin equals the DC level of Vout, and thus the

DC level is biased to VDD/2 (CMOS threshold level). Further-

more, the amplifier circuit, consisting of G1 and feedback re-

si st or R b, results in an AC gain of the signal.

Restoration of Duty Cycle

Typically a waveform at XTALOUT, with a duty cycle of

35–65%, can have the duty cy cle restored close to 50%. This

restoration can be seen on the output of G2, in

Figure 7

which is typically the XBUF pin on most devices.

Both the matched character istics of G1 and G2, and the R-C

components work to restore the duty cycle, the mechanism

being an AC gain and their effect on DC biasing, a s previously

mentioned. However, duty cycle regulation is reduced by G1

saturati ng near VDD or ground. To keep G1 in the linear re-

gion , Ci1 should not be too large. A smaller Ci1 reduces signal

amplitude, thus impro ving linearity.

Coupling Capacitor Value

For Vi1=5Vpp applied to a Cypress device, a capacitor value

of Cil=22 to 24 pF, placed as close to the XTALIN pin as pos-

sible, is recommende d. Using Ci1=22 to 24 pF pro vides 2Vpp

around an average DC level of VDD/2 at X TALI N, a s well a s

re duced loading and restored duty cycle.

Cypress clock generators requi re Vi2=2Vpp . Thus for 5V input

signal (Vi1=5Vpp), Vi2=2Vpp, and Ci2=34 pF, so lving

Equation

results in Ci1 ≈ 22 pF. Accounting for para sitics by substi tut-

ing Ci2eq=36 pF f or Ci2=34 pF, t h e result is Ci1=24 pF.

For a 3.3V input signal (Vi1=3.3Vpp), V i2=2Vpp, and Ci2=34 p F,

solving

Equation 8

results in Ci1 ≈ 5 2 pF. Accounting for par-

asiti cs results in Ci1 ≈ 55 pF.

General Error Budget Analysis

As in any good design, an error budg et should be calc ulated.

Several sources of err or must be taken into account.

• Reference source frequency tolerance (ppm); specified by

manufacturer of reference

• Reference source temperature stability (ppm); specified by

manufacturer of reference

• Cryst al Oscillator process variat ion (ppm); specif ied by

clock chip manufacturer

• Crystal Oscillator supply voltage and temperature stability

(ppm); specified by clock chip manufacturer

The following example uses typical error values for crystals

and Cypress clock devices.

Vi1

Frequency

Source

(5 Volt)

Ceff Ci1

22 pF

Vi2 XTALIN XTALOUT

Ci2=34 pF

Co=34 pF

RbG2

PLL

Parasitic

Capaci tance ≈ 2 pF Parasitic

Capa citanc e ≈ 2 pF

INTERNAL TO DEVICE

Vin Vout

Figure 7. Using an External Driver as Referen ce

eff

⋅

------------------------=

------------------------

Crystal Oscillator Topics

of any circuitry othe r than circui try embodi ed in a Cy press Semi conductor p roduct. Nor does it convey or im ply any li cense under patent or other rights. Cypress Semicondu ctor does not authori ze

its products for use as critic al components in life-support sy stems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

Summary

In s ummary, Cypress recommends th e following for our clock

generators. For designs that use a crystal f or the input refer-

ence, the crystal should be parallel resonant, and have Cload

= 17 to 18 pF. If Cload > 1 8 pF, then use an e xternal ca pacitor,

as shown in

Figure 5

, with Cext calculat ed from

Equatio n 6

. If

Cload < 17 pF, then instead use a crystal with Cload = 17 to 18

pF.

For designs using the 32.768-kHz circuitry, a parallel reso-

nant crystal with Cload = 12 to 13 pF must be used. A 10-MΩ

biasing resistor must be placed in parallel with the crystal.

5V designs using an external clock source must AC couple

the clock input with a 22 - to 24-pF capacitor in series with the

clock source. 3.3V designs should use a 52- to 55-pF cou-

plin g capacitor instead.

For layout recommendations on Cypress clock devices,

please read the application notes: “Jit ter in P LL -B ased S ys-

tems: Causes, Effects, and Sol utions,” and “Layout and Ter-

mination Techniques for Cypress Clock Generators” and, if

available, the application note corresponding to the specific

device.

Example: Addition of Relevant Sources of Error

Sourc e of Error E rror in

ppm

Reference Source, Crystal

Frequency tolerance ±50 ppm

Temperatur e stability ±30 ppm

Crystal Oscillator in Cypress Clock Ge nerator

Process Var iation ±20 ppm

Voltage and Temper ature sta bility ±05 ppm

Total ±105 ppm