IRFD9220, SiHFD9220
www.vishay.com Vishay Siliconix
S12-0617-Rev. D, 26-Mar-12 1Document Number: 91141
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Power MOSFET
FEATURES
• Dynamic dV/dt Rating
• Repetitive Avalanche Rated
• For Automatic Insertion
•End Stackable
•P-Channel
• Fast Switching
• Ease of Paralleling
• Material categorization: For definitions of compliance
please see www.vishay.com/doc?99912
Note
*Lead (Pb)-containing terminations are not RoHS-compliant.
Exemptions may apply.
DESCRIPTION
Third generation Power MOSFETs from Vishay provide the
designer with the best combination of fast switching,
ruggedized device design, low on-resistance and
cost-effectiveness.
The 4 pin DIP package is a low cost machine-insertable
case style which can be stacked in multiple combinations on
standard 0.1" pin centers. The dual drain serves as a thermal
link to the mounting surface for power dissipation levels up
to 1 W.
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. VDD = - 50 V, starting TJ = 25 °C, L = 17.8 mH, Rg = 25 , IAS = - 3 A (see fig. 12).
c. ISD - 3.9 A, dI/dt 95 A/μs, VDD VDS, TJ 150 °C.
PRODUCT SUMMARY
VDS (V) - 200
RDS(on) ()V
GS = - 10 V 1.5
Qg (Max.) (nC) 15
Qgs (nC) 3.2
Qgd (nC) 8.4
Configuration Single
S
G
D
P-Channel MOSFET
HVMDIP
D
SG
Available
RoHS*
COMPLIANT
ORDERING INFORMATION
Package HVMDIP
Lead (Pb)-free IRFD9220PbF
SiHFD9220-E3
SnPbIRFD9220
SiHFD9220
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)
PARAMETER SYMBOL LIMIT UNIT
Drain-Source Voltage VDS - 200 V
Gate-Source Voltage VGS ± 20
Continuous Drain Current VGS at - 10 V TA = 25 °C ID
- 0.56
ATA = 100 °C - 0.36
Pulsed Drain CurrentaIDM - 4.5
Linear Derating Factor 0.0083 W/°C
Single Pulse Avalanche EnergybEAS 80 mJ
Avalanche CurrentaIAR - 0.56 A
Repetitive Avalanche EnergyaEAR 0.10 mJ
Maximum Power Dissipation TA = 25 °C PD1.0 W
Peak Diode Recovery dV/dtcdV/dt - 5.0 V/ns
Operating Junction and Storage Temperature Range TJ, Tstg - 55 to + 150 °C
Soldering Recommendations (Peak Temperature) for 10 s 300d
IRFD9220, SiHFD9220
www.vishay.com Vishay Siliconix
S12-0617-Rev. D, 26-Mar-12 2Document Number: 91141
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
d. 1.6 mm from case.
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width 300 μs; duty cycle 2 %.
THERMAL RESISTANCE RATINGS
PARAMETER SYMBOL TYP. MAX. UNIT
Maximum Junction-to-Ambient RthJA - 120 °C/W
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Static
Drain-Source Breakdown Voltage VDS VGS = 0 V, ID = - 250 μA - 200 - - V
VDS Temperature Coefficient VDS/TJ Reference to 25 °C, ID = - 1 mA - - 0.22 - V/°C
Gate-Source Threshold Voltage VGS(th) VDS = VGS, ID = - 250 μA - 2.0 - - 4.0 V
Gate-Source Leakage IGSS V
GS = ± 20 V - - ± 100 nA
Zero Gate Voltage Drain Current IDSS
VDS = - 200 V, VGS = 0 V - - - 100 μA
VDS = - 160 V, VGS = 0 V, TJ = 125 °C - - - 500
Drain-Source On-State Resistance RDS(on) V
GS = - 10 V ID = - 0.34 Ab--1.5
Forward Transconductance gfs VDS = - 50 V, ID = - 0.35 Ab0.55 - - S
Dynamic
Input Capacitance Ciss VGS = 0 V,
VDS = - 25 V,
f = 1.0 MHz, see fig. 5
- 340 -
pFOutput Capacitance Coss - 110 -
Reverse Transfer Capacitance Crss -33-
Total Gate Charge Qg
VGS = - 10 V ID = - 2.1 A, VDS = - 160 V,
see fig. 6 and 13b
--15
nC Gate-Source Charge Qgs --3.2
Gate-Drain Charge Qgd --8.4
Turn-On Delay Time td(on)
VDD = - 100 V, ID = - 3.9 A,
Rg = 18 , RD = 24 , see fig. 10b
-8.8-
ns
Rise Time tr -27-
Turn-Off Delay Time td(off) -7.3-
Fall Time tf -19-
Internal Drain Inductance LD Between lead,
6 mm (0.25") from
package and center of
die contact
-4.0-
nH
Internal Source Inductance LS-6.0-
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current ISMOSFET symbol
showing the
integral reverse
p - n junction diode
--- 0.56
A
Pulsed Diode Forward CurrentaISM --- 4.5
Body Diode Voltage VSD TJ = 25 °C, IS = - 0.56 A, VGS = 0 Vb--- 6.3V
Body Diode Reverse Recovery Time trr TJ = 25 °C, IF = - 3.9 A, dI/dt = 100 A/μsb- 150 300 ns
Body Diode Reverse Recovery Charge Qrr - 0.97 2.0 μC
D
S
G
S
D
G
IRFD9220, SiHFD9220
www.vishay.com Vishay Siliconix
S12-0617-Rev. D, 26-Mar-12 3Document Number: 91141
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Fig. 1 - Typical Output Characteristics, TA = 25 °C
Fig. 2 - Typical Output Characteristics, TA = 150 °C
Fig. 3 - Typical Transfer Characteristics
Fig. 4 - Normalized On-Resistance vs. Temperature
20 μs PULSE WIDTH
TA = 25 °C
20 μs PULSE WIDTH
TA = 150 °C
IRFD9220, SiHFD9220
www.vishay.com Vishay Siliconix
S12-0617-Rev. D, 26-Mar-12 4Document Number: 91141
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 8 - Maximum Safe Operating Area
TA = 25 °C
TJ = 150 °C
SINGLE PULSE
IRFD9220, SiHFD9220
www.vishay.com Vishay Siliconix
S12-0617-Rev. D, 26-Mar-12 5Document Number: 91141
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Fig. 9 - Maximum Drain Current vs. Ambient Temperature
Fig. 10 - Switching Time Test Circuit
Fig. 11 - Switching Time Waveforms
Fig. 12 - Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
I
D
, Drain Current (A)
T
A
, Ambient Temperature (°C)
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
R
D
V
GS
R
g
D.U.T.
- 10 V
+
-
V
DS
V
DD
VGS
10 %
90 %
VDS
td(on) trtd(off) tf
Thermal Response (Z
thJA
)
t
1
, Rectangular Pulse Duration (s)t
1
, Rectangular Pulse Duration (s)
IRFD9220, SiHFD9220
www.vishay.com Vishay Siliconix
S12-0617-Rev. D, 26-Mar-12 6Document Number: 91141
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Fig. 13 - Unclamped Inductive Test Circuit Fig. 14 - Unclamped Inductive Waveforms
Fig. 15 - Maximum Avalanche Energy vs. Drain Current
Fig. 16 - Basic Gate Charge Waveform Fig. 17 - Gate Charge Test Circuit
R
g
I
AS
0.01 W
t
p
D.U.T.
L
VDS
+
-V
DD
- 10 V
Vary t
p
to obtain
required I
AS
IAS
VDS
VDD
VDS
tp
QGS QGD
QG
VG
Charge
- 10 V
D.U.T.
- 3 mA
VGS
VDS
IGID
0.3 µF
0.2 µF
50 kΩ
12 V
Current regulator
Current sampling resistors
Same type as D.U.T.
+
-
IRFD9220, SiHFD9220
www.vishay.com Vishay Siliconix
S12-0617-Rev. D, 26-Mar-12 7Document Number: 91141
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Fig. 18 - For P-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91141.
P.W. Period
dI/dt
Diode recovery
dV/dt
Body diode forward drop
Body diode forward
current
Driver gate drive
Inductor current
D = P.W.
Period
+
-
-
-
-
+
+
+
Peak Diode Recovery dV/dt Test Circuit
• dV/dt controlled by Rg
• D.U.T. - device under test
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
Rg
• Compliment N-Channel of D.U.T. for driver
VDD
• ISD controlled by duty factor “D”
Note
Note
a. VGS = - 5 V for logic level and - 3 V drive devices
VGS = - 10 Va
D.U.T. lSD waveform
D.U.T. VDS waveform
VDD
Re-applied
voltage
Ripple ≤ 5 % ISD
Reverse
recovery
current
Document Number: 91361 www.vishay.com
Revision: 06-Sep-10 1
Package Information
Vishay Siliconix
HVM DIP (High voltage)
Note
1. Package length does not include mold flash, protrusions or gate burrs. Package width does not include interlead flash or protrusions.
INCHES MILLIMETERS
DIM. MIN. MAX. MIN. MAX.
A 0.310 0.330 7.87 8.38
E 0.300 0.425 7.62 10.79
L 0.270 0.290 6.86 7.36
ECN: X10-0386-Rev. B, 06-Sep-10
DWG: 5974
0.248 [6.29]
0.240 [6.10]
0.197 [5.00]
0.189 [4.80]
0.024 [0.60]
0.020 [0.51]
0.160 [4.06]
0.140 [3.56]
0.180 [4.57]
0.160 [4.06]
4 x
0.100 [2.54] typ.
AL
0.045 [1.14]
0.035 [0.89]
2 x
0.043 [1.09]
0.035 [0.89]
0.094 [2.38]
0.086 [2.18]
0.017 [0.43]
0.013 [0.33]
0° to 15°
2 x
E min.
E max.
0.133 [3.37]
0.125 [3.18]
Legal Disclaimer Notice
www.vishay.com Vishay
Revision: 08-Feb-17 1Document Number: 91000
Disclaimer
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“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
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particular product with the properties described in the product specification is suitable for use in a particular application.
Parameters provided in datasheets and / or specifications may vary in different applications and performance may vary over
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including but not limited to the warranty expressed therein.
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