DSPIC30F4013-20I/PT - Microchip Technology

dsPIC30F3014/4013

Data Sheet

High-Performance, 16-Bit

Digital Signal Controllers

Information contained in this publication regarding device

applications a nd the like is p ro vid ed only f or yo ur c o n ve nience

and may be supers eded by updates. It is y our res po nsibilit y to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accur on,

dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICST ART,

PRO MATE, PowerSmart, rfPIC and SmartShunt are

registered trademarks of Microchip Technology Incorporated

in the U.S.A. and other countries.

AmpLab, FilterLab, Migratable Memory, MX DEV, MXLAB,

SEEV AL, SmartSensor and The Embedded Control Solutions

Company are registered trademarks of Microchip Technology

Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,

ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,

In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active

Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PIC kit,

PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,

PowerInf o, PowerMate, PowerTool, REAL ICE, rfLAB,

rfPICDEM, Select Mode, Smart Serial, SmartTel, Total

Endurance, UNI/O, WiperLock and ZENA are trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrit y of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violat ion of the Digital Millennium Copyright Act. If suc h a c t s

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

T empe, Arizona, Gresham, Oregon and Mountain View , California. The

Company’s quality system processes and procedures are for its PIC®

MCUs and dsPIC DSCs, KEELOQ® code hopping devices, Serial

EEPROMs, microperipherals, nonvolatile memory and analog

products. In addition, Microchip’s quality system for the design and

manufacture of development systems is ISO 9001:2000 certified.

dsPIC30F3014/4013

High-Performance Modified RISC CPU:

• Modified Harvard architecture

• C compiler optimized in struction set architecture

• Flexible addressing modes

• 83 base instructions

• 24-bit wide instructions, 16-bit wide data path

• Up to 48 Kbytes on-chip Flash program space

• 2 Kbytes of on-chip data RAM

• 1 Kbyte of nonvolatile data EEPROM

• 16 x 16-bit working register array

• Up to 30 MIPS operation:

- DC to 40 MHz external clock input

- 4 MHz-10 MHz oscillator input with

PLL active (4x, 8x, 16x)

• Up to 33 interrupt sources:

- 8 user selectable priority levels

- 3 external interrupt sources

- 4 processor traps

DSP Features:

• Dual data fetch

• Modulo and Bit-Reversed modes

• Two 40-bit wide accumulators with optional

saturati on log ic

• 17-bit x 17-bit single-cycle hardware

fractional/integer multiplier

• All DSP instructions are single cycle

- Multiply-Accumulate (MAC) operation

• Single-cycle ±16 shift

Peripheral Feat ures:

• High-current sink/source I/O pins: 25 mA/25 mA

• Up to five 16-bit timers/counters; optionally pair

16-bit timers into 32-bit timer modules

• Up to four 16-bit Capture input functions

• Up to four 16-bit Compare/PWM output functions

• Data Converter Interface (DCI) supports common

audio Codec protocols, including I2S and AC’97

• 3-wire SPI module (supports 4 Frame modes)

•I

2C™ module supports Multi-Master/Slave mode

and 7-bit/10-bit addressing

• Up to two addressable UART modules with FIFO

buffers

• CAN bus module compliant with CAN 2.0B

standard

Analog Features:

• 12-bit Analog-to-Digital Converter (ADC) with:

- 200 ksps co nve rsion rate

- Up to 13 input channels

- Conversion available during Sleep and Idle

• Programmable Low-Voltage Detection (PLVD)

• Programmable Brown-out Reset

Special Microcontroller Features:

• Enhanced Flash program memory:

- 10,000 erase/write cycle (min.) for

industrial temperature range, 100K (typical)

• Data EEPROM memory:

- 100,000 erase/wri t e cycle (min.) for

industrial temperature range, 1M (typical)

• Self-reprogrammable under software control

• Power-on Reset (POR), Power-up Timer (PWR T)

and Oscillator Start-up Timer (OST)

• Flexible Watchdog Timer (WDT) with on-chip

low-power RC oscillator for reliable operation

• Fail- Safe Cloc k Mo nito r operation:

- Detects clock failure and switches to on-chip

low-power RC oscillator

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046). For more information on the device

instruction set and programming, refer to the “dsPIC30F/

33F Programmer’s Reference Manual” (DS70157).

dsPIC30F3014/4013 High-Performance, 16-Bit

Digital Signal Controllers

dsPIC30F3014/4013

Special Microcontroller Features (Cont.):

• Programmable code protection

• In-Circuit Serial Programming™ (ICSP™)

• Selectable Power Management modes:

- Sleep, Idle and Alternate Clock modes

CMOS Technology:

• Low-power, high-speed Flash technology

• Wide operating voltage range (2.5V to 5.5V)

• Industrial and Extended temperature ranges

• Low-power consumption

dsPIC30F3014/4013 Controller Family

Pin Diagrams

Device Pins Program Mem ory SRAM

Bytes EEPROM

Bytes Timer

16-bit Input

Cap

Output

Comp/

Std PWM

Codec

Interface A/D 12-bit

200 Ksp s

UART

SPI

I2C™

CAN

Bytes Instructions

ds PIC30F3014 40/44 24K 8K 2048 1024 3 2 2 - 13 ch 2 1 1 0

ds P I C 30 F 4 013 40/44 48K 16K 2048 1024 5 4 4 A C ’ 9 7 , I 2S13 ch 2 111

PGD/EMUD/AN7/RB7

PGC/EMUC/AN6/OCFA/RB6

RF0

RF1

RD2

IC1/INT1/RD8

AN8/RB8

dsPIC30F3014

MCLR

VDD

Vss

IC2/INT2/RD9

EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14

EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13

OSC2/CLKO/RC15

OSC1/CLKI

AN9/RB9

AN10/RB10

AN11/RB11

AN12/RB12

EMUD2/OC2/RD1

AVDD

AVss

RD3

Vss

VDD

EMUC3/SCK1/RF6

U1RX/SDI1/SDA/RF2

EMUD3/U1TX/SDO1/SCL/RF3

EMUC2/OC1/RD0

VDD

U2RX/CN17/RF4

U2TX/CN18/RF5

AN4/CN6/RB4

AN2/SS1/LVDIN/CN4/RB2

AN1/VREF-/CN3/RB1

AN0/VREF+/CN2/RB0

AN5/CN7/RB5

INT0/RA11

Vss

AN3/CN5/RB3

40-Pin PDIP

dsPIC30F3014/4013

Pin Diagrams (Continued)

Note: For descriptions of individual pins, see Section 1.0 “Device Overview”.

EMUD3/U1TX/SDO1/SCL/RF3

EMUC3/SCK1/RF6

IC1/NT1/RD8

RD2

VDD

EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14

VSS

RD3

IC2/INT2/RD9

INT0/RA11

AN3/CN5/RB3

AN2/SS1/LVDIN/CN4/RB2

AN1/VREF-/CN3/RB1

AN0/VREF+/CN2/RB0

MCLR

AVDD

AVSS

AN9/RB9

AN10/RB10

AN12/RB12

EMUC2/OC1/RD0

EMUD2/OC2/RD1

VDD

VSS

RF0

RF1

U2RX/CN17/RF4

U2TX/CN18/RF5

U1RX/SDI1/SDA/RF2

AN4/CN6/RB4

AN5/CN7/RB5

PGC/EMUC/AN6/OCFA/RB6

PGD/EMUD/AN7/RB7

AN8/RB8

VDD

VSS

OSC1/CLKI

OSC2/CLKO/RC15

EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13

dsPIC30F3014

44-Pin TQFP

AN11/RB11

dsPIC30F3014/4013

Pin Diagrams (Continued)

Note: For descriptions of individual pins, see Sect ion 1.0 “Device Overview”.

44-Pin QFN

dsPIC30F3014

EMUD3/U1TX/SDO1/SCL/RF3

EMUC3/SCK1/RF6

IC1/INT1/RD8

RD2

VDD

EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14

EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13

VSS

RD3

IC2/INT2/RD9

INT0/RA11

AN4/CN6/RB4

AN5/CN7/RB5

PGC/EMUC/AN6/OCFA/RB6

PGD/EMUD/AN7/RB7

AN8/RB8

OSC2/CLKO/RC15

VDD

VSS

OSC1/CLKI

EMUC2/OC1/RD0

EMUD2/OC2/RD1

VDD

VSS

RF0

RF1

U2RX/CN17/RF4

U2TX/CN18/RF5

U1RX/SDI1/SDA/RF2

AN12/RB12

AN3/CN5/RB3

AN2/SS1/LVDIN/CN4/RB2

AN1/VREF-/CN3/RB1

AN0/VREF+/CN2/RB0

MCLR

AN11/RB11

AVDD

AVSS

AN9/RB9

AN10/RB10

NC 44

330

232

dsPIC30F3014/4013

Pin Diagrams (Continued)

Note: For descriptions of individual pins, see Section 1.0 “Device Overview”.

PGD/EMUD/AN7/RB7

PGC/EMUC/AN6/OCFA/RB6

C1RX/RF0

C1TX/RF1

OC3/RD2

IC1/INT1/RD8

AN8/RB8

dsPIC30F4013

MCLR

VDD

VSS

IC2/INT2/RD9

EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14

EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13

OSC2/CLKO/RC15

OSC1/CLKI

AN9/CSCK/RB9

AN10/CSDI/RB10

AN11/CSDO/RB11

AN12/COFS/RB12

EMUD2/OC2/RD1

AVDD

AVSS

OC4/RD3

VSS

VDD

EMUC3/SCK1/RF6

U1RX/SDI1/SDA/RF2

EMUD3/U1TX/SDO1/SCL/RF3

EMUC2/OC1/RD0

VDD

U2RX/CN17/RF4

U2TX/CN18/RF5

AN4/IC7/CN6/RB4

AN2/SS1/LVDIN/CN4/RB2

AN1/VREF-/CN3/RB1

AN0/VREF+/CN2/RB0

AN5/IC8/CN7/RB5

INT0/RA11

VSS

AN3/CN5/RB3

40-Pin PD IP

EMUD3/U1TX/SDO1/SCL/RF3

EMUC3/SCK1/RF6

IC1/INT1/RD8

OC3/RD2

VDD

EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14

VSS

OC4/RD3

IC2/INT2/RD9

INT0/RA11

AN3/CN5/RB3

AN2/SS1/LVDIN/CN4/RB2

AN1/VREF-/CN3/RB1

AN0/VREF+/CN2/RB0

MCLR

AVDD

AVSS

AN9/CSCK/RB9

AN10/CSDI/RB10

AN12/COFS/RB12

EMUC2/OC1/RD0

EMUD2/OC2/RD1

VDD

VSS

C1RX/RF0

C1TX/RF1

U2RX/CN17/RF4

U2TX/CN18/RF5

U1RX/SDI1/SDA/RF2

AN4/IC7/CN6/RB4

AN5/IC8/CN7/RB5

PGC/EMUC/AN6/OCFA/RB6

PGD/EMUD/AN7/RB7

AN8/RB8

VDD

VSS

OSC1/CLKI

OSC2/CLKO/RC15

EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13

dsPIC30F4013

44-Pin TQFP

AN11/CSDO/RB11

dsPIC30F3014/4013

Pin Diagrams (Continued)

For descriptions of individual pins, see Section 1.0 “Device Overvi ew ”.

44-Pin QFN

330

232

dsPIC30F4013

EMUD3/U1TX/SDO1/SCL/RF3

EMUC3/SCK1/RF6

IC1/NT1/RD8

OC3/RD2

VDD

EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14

EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13

VSS

OC4/RD3

IC2/INT2/RD9

INT0/RA11

AN4/IC7/CN6/RB4

AN5/IC8/CN7/RB5

PGC/EMUC/AN6/OCFA/RB6

PGD/EMUD/AN7/RB7

AN8/RB8

OSC2/CLKO/RC15

VDD

VSS

OSC1/CLKI

EMUC2/OC1/RD0

EMUD2/OC2/RD1

VDD

VSS

C1RX/RF0

C1TX/RF1

U2RX/CN17/RF4

U2TX/CN18/RF5

U1RX/SDI1/SDA/RF2

AN12/COFS/RB12

AN3/CN5/RB3

AN2/SS1/LVDIN/CN4/RB2

AN1/VREF-/CN3/RB1

AN0/VREF+/CN2/RB0

MCLR

AN11/CSDO/RB11

AVDD

AVSS

AN9/CSCK/RB9

AN10/CSDI/RB10

© 2007 Microchip Technology Inc. DS70138E-page 7
dsPIC30F3014/4013
Table of Contents
1.0 Device Overview ......................................................................................................................................................................... 9
2.0 CPU Architecture Overview ....................................................................................................................................................... 13
3.0 Memory O rganization ................................................................................................................................................................ 23
4.0 Address G enerator Units ........................................................................................................................................................... 35
5.0 Flash Pro g ram Memory ............................. ............................ ........................... ......................................................................... 41
6.0 Data EEPR OM Mem o ry  ............................... ........................... ..................... ............................................................................. 47
7.0 I/O Ports ........................... ............................ ........................... ........................... ....................................................................... 51
8.0 Interrupts ................................................................................................................................................................................... 55
9.0 Timer1 Module  .......................................................................................................................................................................... 63
10.0 Timer2/3 Module  ...... .. .. .. .... .. ..... .. .... .. .. .. .. ....... .. .. .. .... .. .. .. ....... .. .. .. .... .. .. ..... .... .. .. .. .. .... ..... ............................................................ 67
11.0 Timer4/5 Module   ......... .. .. .... ..... .. .. .... .. .. .. .. ....... .. .. .. .... .. .. ....... .. .. .. .. .... .. ..... .. .... .. .. .. .. ....... ............................................................ 73
12.0 Input Capture Module ... .. .... .. ....... .. .. .... .. .. ....... .. .... .. .. .... .. ....... .. .. .... .. .. ....... .. .... .. .. .... .. ....... .......................................................... 77
13.0 Output Compa re Module ......................... ..................... ............................ ..................... ............................................................ 81
14.0 I2C™ Module  ............................................................................................................................................................................ 85
15.0 SP I Module ................................................................................................................................................................................ 93
16.0 U nivers al Asynchr onous Receiver  Transmi tter (UART) Module  ............................................................................................... 97
17.0 CAN Module ............................................................................................................................................................................ 105
18.0 Data Converter Interface (DCI) Module ........................................................ .... .... .... ......... .... .... .............................................. 115
19.0 12-bit Analog- to-Digital Converter (ADC) Module . .................................................................................................................. 125
20.0 System Inte g ration  .................................. ............................ ........................... ......................................................................... 135
21.0 Instruction Set Summary ......................................................................................................................................................... 153
22.0 Development Support .............................................................................................................................................................. 161
23.0 Electrical Characteristics ......................................................................................................................................................... 165
24.0 Packagin g  In fo rmation ............................... ............................ ..................... ............................................................................. 203
Index ................................................................................................................................................................................................. 209
The Micro chip Web Site ....... ........................... .................................. ........................... ..................................................................... 215
Customer Change Notification Service .................................. ............. ...... ............. ...... .... ............. .................................................... 215
Customer Support ............................................................................. ...... ...... ............. .... ................................................................... 215
Reader Response ............................................................................................................................................................................. 216
Product Identification System  ........................................................................................................................................................... 217
TO OUR VALUED CUSTOMERS
It is our intention to  provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our pu blications to better s uit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced. 
If you have  any questions o r c omm ents regarding this publication, please c ontact the M arketing Communications Department via
E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We
welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of an y page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet  and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To deter mine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microc hip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include  literature number) you are
using.
Customer Noti fic atio n Syst em
Register on our web site at www.microchip.com to receive the most current information on all of our products.

dsPIC30F3014/4013

NOTES:

dsPIC30F3014/4013

1.0 DEVICE OVERVIEW This document contains specific information for the

dsPIC30F3014/4013 Digital Signal Controller (DSC)

devices. The dsPIC30F3014/4013 devices contain

extensive Digital Signal Processor (DSP) functionality

within a high-performance 16-bit microcontroller (MCU)

architecture. Figure 1-1 and Figure 1-2 show device

block d iagrams for dsPIC 30F3014 and dsPI C30F4013,

respectively.

FIGURE 1-1: dsPIC30F3014 BLOCK DIAGRAM

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046). For more information on the device

instruction set and programming, refer to the “dsPIC30F/

33F Programmer’s Reference Manual” (DS70157).

AN8/RB8

AN9/RB9

AN10/RB10

AN11/RB11

Power-up

Timer

Oscillator

St art-up Timer

POR/BOR

Reset

Watchdog

Timer

Instruction

Decode and

Control

OSC1/CLKI

MCLR

, V

AN4/CN6/RB4

AN12/RB12

Low-Voltage

Detect

UART1,

Timing

Generation

AN5/CN7/RB5

PCH PCL

Program Counter

ALU<16>

X Data Bus

C™

DCI

PGC/EMUC/AN6/OCFA/RB6

PGD/EMUD/AN7/RB7

PCU

12-bit ADC

Timers

U2TX/CN18/RF5

EMUC3/SCK1/RF6

Input

Capture

Module

Output

Compare

Module

EMUD1/SOSCI/T2CK/U1ATX/

PORTB

RF0

RF1

U1RX/SDI1/SDA/RF2

EMUD3/U1TX/SDO1/SCL/RF3

PORTD

16 16

16 x 16

W Reg Array

Divide

Unit

Engine

DSP

Decode

ROM Latch

Y Data Bus

Effective A ddress

X RAGU

X WAGU

Y AGU AN0/V

REF

+/CN2/RB0

AN1/V

REF

-/CN3/RB1

AN2/SS1/LVDIN/CN4/RB2

AN3/CN5/RB3

OSC2/CLKO/RC15

U2RX/CN17/RF4

, A V

UART2

PORTC

PORTF

Interrupt

Controller

PSV & Table

Data Access

Control Block

Stack

Control

Logic

Loop

Control

Logic

Data LatchData Latch

Y Data

(1 Kbyte)

RAM X Data

(1 Kbyte)

RAM

Address

Latch Address

Latch

Control Signals

to Various Blocks

EMUC2/OC1/RD0

EMUD2/OC2/RD1

RD2

RD3

IC1/INT1/RD8

IC2/INT2/RD9

SPI1

Address Latch

Program Memory

(24 Kbytes)

Data Latch

Data EEPROM

(1 Kbyte)

CN1/RC13

EMUC1/SOSCO/T1CK/U1ARX/

CN0/RC14

PORTA

INT0/RA11

dsPIC30F3014/4013

FIGURE 1-2: dsPIC30F4013 BLOCK DIAGRAM

AN8/RB8

AN9/CSCK/RB9

AN10/CSDI/RB10

AN11/CSDO/RB11

Power-up

Timer

Oscillator

S tart-up Timer

POR/BOR

Reset

Watchdog

Timer

Instruction

Decode &

Control

OSC1/CLKI

MCLR

, V

AN4/IC7/CN6/RB4

AN12/COFS/RB12

Low-Voltage

Detect

Timing

Generation

AN5/IC8/CN7/RB5

PCH PCL

Program Counter

ALU<16>

X Data Bus

PGC/EMUC/AN6/OCFA/RB6

PGD/EMUD/AN7/RB7

PCU

U2TX/CN18/RF5

EMUC3/SCK1/RF6

EMUD1/SOSCI/T2CK/U1ATX/

PORTB

C1RX/RF0

C1TX/RF1

U1RX/SDI1/SDA/RF2

EMUD3/U1TX/SDO1/SCL/RF3

PORTD

16 16

16 x 16

W Reg Array

Divide

Unit

Engine

DSP

Decode

ROM Latch

Y Data Bus

Effective Address

X RAGU

X WAGU

Y AGU AN0/V

REF

+/CN2/RB0

AN1/V

REF

-/CN3/RB1

AN2/SS1/LVDIN/CN4/RB2

AN3/CN5/RB3

OSC2/CLKO/RC15

U2RX/CN17/RF4

, A V

PORTC

PORTF

Interrupt

Controller

PSV & Table

Data Access

Control Block

Stack

Control

Logic

Loop

Control

Logic

Data LatchData Latch

Y Data

(1 Kbyte)

RAM X Data

(1 Kbyte)

RAM

Address

Latch Address

Latch

Control Signals

to Various Blocks

EMUC2/OC1/RD0

EMUD2/OC2/RD1

OC3/RD2

OC4/RD3

IC1/INT1/RD8

IC2/INT2/RD9

Address Latch

Program Memory

(48 Kbytes)

Data Latch

Data EEPROM

(1 K byte )

CN1/RC13

EMUC1/SOSCO/T1CK/U1ARX/

CN0/RC14

PORTA

INT0/RA11

UART1,

C™

DCI

12-bit ADC

Timers

Input

Capture

Module

Output

Compare

Module

UART2

SPI1

CAN1

dsPIC30F3014/4013

Table 1-1 provides a brief description of device I/O

pinouts and the functions that may be multiplexed to a

port pin. Multiple functions may exist on one port pin.

When multiplexing occurs, the peripheral module’s

functional requirements may force an override of the

data direction of the port pin.

TABLE 1-1: PINOUT I/O DESCRIPTIONS

Pin Name Pin

Type Buffer

Type Description

AN0- AN12 I Analog Analog input channels. AN6 and AN7 are also used for de vi ce

programm i ng data and clock inputs, res pectively.

AVDD P P Positive sup pl y f or a nalog modu le .

AVSS P P Groun d re fe re nce for analog module.

CLKI

CLKO

ST/CMOS

—

Ext ernal clock so urce input. Always associ ated with OSC1 pin

function.

Oscillat or crystal ou tp ut . Co nnects to crys tal or resonator in

Crystal Oscillator mode. Optionally functions as CLKO in RC

and EC modes. Always associa te d wi th O SC 2 pin function.

CN0- C N7, CN 17-CN18 I ST Input change notifi cat i on inputs. Can be soft w ar e pr ogramm ed

for internal weak pu l l-ups on a ll in puts.

COFS

CSCK

CSDI

CSDO

I/O

—

Data Conve rter In terface Frame Synchr oni z at io n pin.

Data Conve rter In terface Serial C l ock in put / out p ut pin .

Data Converter In te rface Serial data input pi n.

Data Conve rter Inte rface Serial data out put pin.

C1RX

C1TX I

OST

—CAN1 bus receive pin.

CAN1 bus transm it pin.

EMUD

EMUC

EMUD1

EMUC1

EMUD2

EMUC2

EMUD3

EMUC3

I/O

ICD Prim ar y C o mmunica t io n C hannel data input/output pi n.

ICD Primary Communication Channel clock input/output pin.

ICD Secondary Communication Channel data input/output pin.

ICD Seco ndary Com m unicati on Ch annel cloc k i nput/output pi n.

ICD Tertiary Communication Channel data input/output pin.

ICD Tertiary C om munica t i on Chan nel clock inpu t / outpu t pin.

ICD Quat er nary Comm unication C hannel data input/output pin.

ICD Quaternary Communication Channel clock input/output pin.

IC1, IC2, IC7 , IC8 I ST Capture inputs 1 , 2 , 7 an d 8.

INT0

INT1

INT2

External interrup t 0.

External interrup t 1.

External interrup t 2.

LVDIN I Analog Low-Voltage Detect Reference Voltage Input pin.

MCLR I/P ST Master Cl ear (Rese t) in put or program m i ng voltage input . Thi s

pin is an active-low Reset to the device.

OCFA

OC1-OC4 I

OST

—Compare Fau lt A i nput (for Com pare ch annels 1, 2, 3 and 4).

Compare outputs 1 throug h 4.

OSC1

OSC2

I/O

ST/CMOS

—

Oscillator c ry stal input. ST buffer when configured in RC mode;

CMOS ot he rwise.

Oscillat or crystal ou tp ut . Co nnects to crys tal or resonator in

Crystal Oscillator mode. Optionally functions as CLKO in RC

and EC modes.

PGD

PGC I/O

IST

ST In-Circu it Seri al Pro gr am m ing™ data input/outp ut pin.

In-Circu it Seri al Pro gram ming clock inp ut pin.

Legend: CMOS = CMOS compatible input or output Analog = Analog input

ST = Schmitt Trigger input with CMOS levels O = Output

I = Input P = Power

dsPIC30F3014/4013

RA11 I/O ST PORTA is a bidirectional I/O port.

RB0-RB12 I/O ST PORTB is a bidirectional I/O port.

RC13-RC15 I/O ST PORTC is a bidirectional I/O port.

RD0-RD3, RD8, RD9 I/O ST PORTD is a bidirectional I/O port.

RF0-R F5 I/O ST PORTF is a bidirectional I/O po rt.

SCK1

SDI1

SDO1

SS1

I/O

—

Synchro nous serial cl ock input/output for SPI1.

SPI1 data in.

SPI1 data out.

SPI1 slave sy nchroniz at io n.

SCL

SDA I/O

I/O ST

ST Synchronous se rial cl oc k in put/outp ut fo r I2C™.

Synchronous serial data input/output for I2C.

SOSCO

SOSCI O

I—

ST/CMOS 32 kHz low-power oscillator cr ystal output.

32 kHz low-power oscillator crystal input. ST buffer when

configur ed i n R C m ode; CMO S otherwise .

T1CK

T2CK I

IST

ST Time r1 e xt ernal cloc k input.

Time r2 e xt ernal cloc k input.

U1RX

U1TX

U1ARX

U1ATX

—

UART1 receive.

UART1 trans m it.

UART1 a lte rn at e receive.

UART1 a lternate transm i t .

VDD P — Positive supply for logic and I/O pins.

VSS P — Ground reference for logic and I/O pins.

VREF+ I Analog Analog voltage r ef er ence (high) in put .

VREF- I Analog Analog voltage r ef er ence (low) input.

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name Pin

Type Buffer

Type Description

Legend: CMOS = CMOS compatible input or output Analog = Analog input

ST = Schmitt Trigger input with CMOS levels O = Output

I = Input P = Power

dsPIC30F3014/4013

2.0 CPU ARCHITECTURE

OVERVIEW

2.1 Core Overview

This section contains a brief overview of the CPU

architecture of the dsPIC30F.

The core has a 24-bit instruction word. The Program

Counter (PC) is 23 bits wide with the Least Significant

bit (LSb) always clear (refer to Section 3.1 “Program

Address Space”), and the Most Significant bit (MSb)

is ign ored du ring no rmal program executi on, ex cept for

certain specialized instructions. Thus, the PC can

address up to 4M instruction words of user program

space. An instruction prefetch mechanism is used to

help maintain throughput. Program loop constructs,

free from loop count management overhead, are

supported using the DO and REPEAT inst ru cti on s, b oth

of which are int errup tib le at any point.

The working register array consists of 16-bit x 16-bit

set registers. One working register (W15) operates as

a software Stack Pointer for interrupts and calls.

The data space is 64 Kbytes (32K words) and is split

into two blocks, referred to as X and Y data memory.

Each block has its own independent Address Genera-

tion Unit (AGU). Most instructions operate solely

through the X memory, AGU, which provides the

appearance of a single, unified data space. The

Multiply-Accumulate (MAC) class of dual source DSP

instructions operate through both the X and Y AGUs,

splitting the data address space into two parts (see

Section 3.2 “Data Address Space”). The X and Y

data space boundary is device-specific and cannot be

alter ed by the user . Each dat a word consis ts of 2 bytes,

and mos t instruction s can address data eith er as words

or bytes.

There are two methods of accessing data stored in

program memory:

• The upper 32 Kbytes of data space memory can

be mappe d into the lowe r hal f (us er space) of pro-

gram space at any 16K program word boundary,

defined by the 8-bi t Program Sp ace Vis ibility Page

(PSVPAG) register. This lets any instruction

access program space as if it were data space,

with a limitation that the access requires an addi-

tional cycle. More over, only t he lower 16 bits of

each instruction word can be accessed using this

method.

• Linear indirect access of 32K word pages within

progra m spac e is also possibl e using any w orking

Table read and write instructions can be used to

access all 24 bits of an instruction word.

Overhead-free circular buffers (Modulo Addressing)

are supported in both X and Y address spaces. This is

primarily intended to remove the loop overhead for

DSP algorithms.

The X AGU also supports Bit-Reversed Addressing on

destination Ef fective Addresses to greatly simplify inp ut

or output data reordering for radix-2 FFT algorithms.

Refer to Section 4.0 “Address Generator Units” for

details on Modulo and Bit-Reversed Addressing.

The core supports Inherent (no operand), Relative,

Literal, Memory Direct, Register Direct, Register

Indirect, Register Offset and Literal Offset Addressing

modes. Instructions are associated with predefined

addressing modes, depending upon their functional

requirements.

For m os t i ns tru c ti o ns , the c or e i s c apa bl e of e xe c ut i ng

a data (or program data) memory read, a working reg-

ister (data) read, a data memory write and a program

(instruction) memory read per instruction cycle. As a

result, 3-operand instructions are supported, allowing

C = A+B operations to be executed in a single cycle.

A DSP engine has been included to significantly

enhance the core arithmetic capab ility and throughput.

It features a high-speed, 17-bit x 17 -bit multiplier , a 40-

bit ALU, two 40-bit saturating accumulators and a 40-

bit bidirectional barrel shifter. Data in the accumulator,

or any working register, can be shifted up to 15 bits

right, or 16 bits left in a single cycle. The DSP instruc-

tions ope rate sea mles sly with all other in struct ions an d

have be en desi gned for o ptimal re al-time p erforma nce.

The MAC class of instructions can concurrently fetch

two data operands from memory while multiplying two

W registers. To enable this concurrent fetching of data

operands, the data space has been split for these

instructions and linear is for all others. This has been

achieved in a transparent and flexible manner by

dedicating certain working registers to each address

spac e for the MAC class of instructions.

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046). For more information on the device

instruction set and programming, refer to the “dsPIC30F/

33F Programmer’s Reference Manual” (DS70157).

dsPIC30F3014/4013

The core does not support a multi-stage instruction

pipeline. However, a single-stage instruction prefetch

mechanism is used, which accesses and partially

decodes instructions a cycle ahead of execution, in

order to maximize available execution time. Most

instructions execute in a single cycle with certain

exceptions.

The core features a vectored exception processing

structure for traps and interrupts, with 62 independent

vectors. The exceptions consist of up to 8 traps (of

which 4 are re served ) a nd 54 interrupts . Ea ch in terru pt

is prioritized based on a us er-assigned priority between

1 and 7 (1 being the lowest priority and 7 being the

highest), in conjunction with a predetermined ‘natural

order’. Traps have fixed priorities ranging from 8 to 15.

2.2 Pr ogrammer’s Model

The programmer’s model is shown in Figure 2-1 and

consists of 16 x 16-bit working registers (W0 through

W15), 2 x 40-bit accumulators (AccA and AccB),

STATUS register (SR), Data Table Page register

(TBLPAG), Program Space Visibility Page register

(PSVPAG), DO and REPEAT registers (DOSTART,

DOEND, DCOUNT and RCOUNT) and Program

Counter (PC). The working registers can act as data,

address or offset registers. All registers are memory

mapped. W0 acts as the W register for file register

addressing.

Some of these registers have a shadow register asso-

ciated with each of them, as shown in Figure 2-1. The

shadow register is used as a temporary h olding register

and can tr ansfer its con tents to or fro m i t s hos t reg is ter

upon the occurrence of an event. None of the shadow

registers are accessible directly. The following rules

apply for transfer of registers into and out of shadows.

•PUSH.S and POP.S

W0, W1, W2, W3, SR (DC, N, OV, Z and C bits

only) are transferred.

•DO instruction

DOSTART, DOEND, DCOUNT shadows are

pushed on loop start and popped on loop end.

When a byte operation is performed on a working

mapped working registers is that both the Least and

Most Significant Bytes can be manipulated through

byte-wide data memory space accesses.

2.2.1 SOFTWARE STACK POINTER/

FRAM E POIN TE R

The dsPIC® DSC devices contain a software stack.

W15 is the dedicated Software Stack Pointer (SP) and

is automatically modified by exception processing and

subrouti ne calls and retur ns. However, W15 can be ref-

erenced by any instruction in the same manner as all

other W registers. This simplifies the reading, writing

and manipulation of the Stack Pointer (e.g., creating

St ac k Frames ).

W15 is initialized to 0x0800 during a Reset. The user

may reprogram the SP during initialization to any

location within data space.

W14 has been dedica ted as a St a ck Frame Pointer, as

defined by the LNK and ULNK instructions. However,

W14 can be referenced by any instruction in the same

manner as all other W registers.

2.2.2 STATUS REGISTER

The dsPIC DSC core has a 16-bit STATUS register

(SR), the Least Significant Byte (LSB) of which is

referred to as the SR Low byte (SRL) and the Most

Significant Byte (MSB) as the SR High byte (SRH). See

Figure 2-1 for SR layout.

SRL contains all the MCU ALU operation status flags

(includ ing the Z bit ), as well as the CPU Inter rupt Prior-

ity Level Status bits, IPL<2:0> and the Repeat Active

Status bit, RA. During exception processing, SRL is

concatenated with the MSB of the PC to form a

complete word value which is then stacked.

The upper byte of the STATUS register contains the

DSP adder/subtracter Status bits, the DO Loop Active

bit (DA) and the Digit Carry (DC) Status bit.

2.2.3 PROGRAM COUNT ER

The program counter is 23 bits wide; bit 0 is always

clear. Therefore, the PC can address up to 4M

instruction words.

Note: In order to protect against misaligned

stack accesses, W15<0> is always clear.

dsPIC30F3014/4013

FIGURE 2-1 : P ROGRAMMER’ S MODEL

TABPAG

PC22 PC0

7 0

D0D15

Program Counter

Data Table Page Address

STATUS Register

Working Registers

DSP Operand

Registers

W10

W11

W12/DSP Offset

W13/DSP Write-Back

W14/Frame Pointer

W15/Stack Pointer

DSP Address

Registers

AD39 AD0AD31

DSP

Accumulators AccA

AccB

PSVPAG

7 0Program Space Visibility Page Address

OA OB SA SB

RCOUNT

15 0

REPEAT Loop Counter

DCOUNT

15 0

DO Loop Counter

DOSTART

22 0

DO Loop Start Address

IPL2 IPL1

SPLIM Stack Pointer Limit Register

AD15

SRL

PUSH.S Shadow

DO Shadow

OAB SAB

15 0Core Configuration Register

Legend

CORCON

DA DC RA N

TBLPAG

PSVPAG

IPL0 OV

W0/WREG

SRH

DO Loop End Address

DOEND

dsPIC30F3014/4013

2.3 Di vide Support

The dsPIC DSC devices feature a 16/16-bit signed

fraction al d iv ide ope rati on , as w ell as 32/1 6-b it a nd 1 6/

16-bit signed and unsigned integer divide operations, in

the form of single instruction iterative divides. The

following instructions and data sizes are supported:

1. DIVF – 16/16 signed fractional divide

2. DIV.sd – 32/16 signed divide

3. DIV.ud – 32/16 unsigned divide

4. DIV.s– 16/16 signed divide

5. DIV.u – 16/16 unsigned divide

The 16/16 divides are similar to the 32/16 (same number

of iterations), but the dividend is eithe r zero-extended or

sign-extended during the first iteration.

The divide instructions must be executed within a

REPEAT loop. Any other form of execution (e.g., a

series of discrete divide instructions) will not function

correctly because the instruction flow depends on

RCOUNT. The divid e instruction does not automatica lly

set up the RCOUNT value and it must, therefore, be

explic itly and correctl y specifi ed in the REPEAT instruc-

tion, as shown in Table 2-1 (REPEAT will execute the

target instruction {operand value+1} times). The

REPEAT loop count must be setup for 18 iterations of

the DIV/DIVF instruction. Thus, a complete divide

operation requires 19 cycles.

TABLE 2-1: DIVIDE INSTRUCTIONS

Note: The divide flow is interruptible. However,

the user needs to save the context as

appropriate.

Instruction Function

DIVF Signed fractional divide: Wm/Wn → W0; Rem → W1

DIV.sd Signed divide: (Wm+1:Wm)/Wn → W0; Rem → W1

DIV.s Signed divide: Wm/Wn → W0; Rem → W1

DIV.ud Unsigned divide: (Wm+1:Wm)/Wn → W0; Rem → W1

DIV.u Unsigned divide: Wm/Wn → W0; Rem → W1

dsPIC30F3014/4013

2.4 DSP Engine

The DSP engine consists of a high-speed, 17-bit x

17-bit multiplier, a barrel shifter and a 40-bit adder/

subtracter (with two target accumulators, round and

saturati on log ic).

The DSP engine also has the capability to perform

inherent accumulator-to-accumulator operations,

which require no additional d ata. These in structions are

ADD, SUB and NEG.

The dsPIC30F is a single-cycle instruction flow archi-

tecture, therefore, concurrent operation of the DSP

engine with MCU instruction flow is not possible.

However, some MCU ALU and DSP engine resources

may be used concurrently by the same in struction (e.g.,

ED, EDAC). (See Table 2-2 for DSP instructions.)

The DSP engine has various options selected through

various bits in the CPU Core Configuration register

(CORCON), as listed below:

1. Fractional or integer DSP multiply (IF).

2. Signed or unsigned DSP multiply (US).

3. Conventional or convergent rounding (RND).

4. Automatic saturation on/off for AccA (SATA).

5. Automatic saturation on/off for AccB (SATB).

6. Automatic saturation on/off for writes to data

memory (SATDW).

7. Accumulator Saturation mode selection

(ACCSAT).

A block diagram of the DSP engine is shown in

Figure 2-2.

Note: For CORCON layout, see Table 3-3.

TABLE 2-2: DSP INSTRUCTION SUMMARY

Instruction Algebraic Operation ACC WB?

CLR A = 0 Yes

ED A = (x – y)2No

EDAC A = A + (x – y)2No

MAC A = A + (x * y) Yes

MAC A = A + x2No

MOVSAC No change in A Yes

MPY A = x * y No

MPY.N A = – x * y No

MSC A = A – x * y Yes

dsPIC30F3014/4013

FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM

Zero Backfill

Sign-Extend

Barrel

Shifter

40-bit Accumula tor A

40-bit Accumula tor B Round

Logic

X Data Bus

To/From W Array

Adder

Saturate

Negate

16 16

40 40

Y Data Bus

Carry/Borrow Out

Carry/Borrow In

Multiplier/Scaler

17-bit

dsPIC30F3014/4013

2.4.1 MULTIPLIER

The 17-bit x 17-bit multiplier is capable of signed or

unsign ed ope ration an d can m ultiplex its output u sing a

scaler to support either 1.31 fractional (Q31) or 32-bit

integer results. Unsigned operands are zero-extended

into the 17th bit of the multiplier input value. Signed

operands are sign-extended into the 17th bit of the

multiplier input value. The output of the 17-bit x 17-bit

multiplier/scaler is a 33-bit value, which is sign-

extended to 40 bits. Integer data is inherently repre-

sented as a signed two’ s comp lement val ue, where the

MSB is defined as a sign bit. Generally speaking, the

range of an N-bit two’s complement integer is -2N-1 to

2N-1 – 1. For a 16-bit integer, the data range is -32768

(0x8000) to 32767 (0x7FFF) including ‘0’. For a 32-bit

integer, the data range is -2,147,483,648

(0x8000 0000) to 2,147,483,645 (0x7FFF FFFF).

When the multiplier is configured for fractional multipli-

cation, the data is represented as a two’s complement

fraction , where the M SB is define d as a sign b it and the

radix po int is im plied to lie just a fter the si gn bit (QX f or-

mat). The range of an N-bit two’s complement fraction

with this implied radix point is -1.0 to (1 – 21-N). For a

16-bit fraction, the Q15 data range is -1.0 (0x8000) to

0.999969482 (0x7FFF) including ‘0’ and has a preci-

sion of 3.01518x10-5. In Fractional mode, the 16x16

multipl y ope ration genera tes a 1.31 p rodu ct, whi ch ha s

a precision of 4.65661 x 10-10.

The same multiplier is used to support the MCU multi-

ply instructions, which include integer 16-bit signed,

unsigned and mixed sign multiplies.

The MUL instruction can be directed to use byte or

word-sized operands. Byte operands direct a 16-bit

result, and word operands direct a 32-bit result to the

specified register(s) in the W array.

2.4.2 DATA ACCUMULATORS AND

ADDER/SUBTRACTER

The data accumulator consists of a 40-bit adder/

subtracter with automatic sign extension logic. It can

select one of two accumulators (A or B) as its pre-

accumulation source and post-accumulation destina-

tion. For the ADD and LAC instructions, the data to be

accum ulated or l oaded ca n be optio nally sca led via th e

barrel shifter prior to accu mulation .

2.4.2.1 Adder/Subtracter, Overflow and

Saturation

The adder/subtracter is a 40-bit adder with an optional

zero input into one side and either true or complement

data into the other input. In the case of addition, the

carry/borrow input is active high and the other input is

true data (not complemented), whereas in the case of

subtrac tion, the carry/borrow input is active low and the

other input is complemented. The adder/subtracter

generates overflow Status bits SA/SB and OA/OB,

which are la tched and reflected in the ST ATUS register:

• Overflow from bit 39: this is a catastrophic

overflow in which the sign of the accumulator is

destroyed.

• Overflow into guard bits 32 through 39: this is a

recoverable overflow. This bit is set whenever all

the guard bits are not identical to each other.

The adder has an additional saturation block which

controls accumulat or data satu ration if selec ted. It uses

the result of the adder, the overflow Status bits

described above, and the SATA/B (CORCON<7:6>)

and ACCSAT (CORCON<4>) mode control bits to

determine when and to what value to saturate.

Six STATUS register bits have been provided to

support saturation and overflow. They are:

1. OA:

AccA overflowed into guard bits

2. OB:

AccB overflowed into guard bits

3. SA:

AccA saturated (bit 31 overflow and saturation)

AccA overflowed into guard bits and saturated

(bit 39 over flow and saturation)

4. SB:

AccB saturated (bit 31 overflow and saturation)

AccB overflowed into guard bits and saturated

(bit 39 over flow and saturation)

5. OAB:

Logical OR of OA and OB

6. SAB:

Logical OR of SA and SB

The OA and OB bits are modified each time data

passes through the adder/subtracter. When set, they

indicate that the most recent operation has overflowed

into the accumulator guard bits (bits 32 through 39).

The OA and OB bits can also optionally generate an

arithmetic warning trap when set and the correspond-

ing overflow trap flag enable bit (OVATE, OVBTE) in

the INTCON1 register (refer to Section 8.0 “Inter-

rupts”) is set. This allows the user to take immediate

action, for example, to correct system gain.

dsPIC30F3014/4013

The SA and SB bits are modified each time data

passes through the adder/subtracter but can only be

cleared by the user. When set, they indicate that the

accumula tor has overfl owed it s m aximum range (b it 31

for 32-bit saturation or bit 39 for 40-bit saturation) and

will be saturated if saturation is enabled. When

saturation is not enabled, SA and SB default to bit 39

overflow and, thus, indicate that a catastrophic over-

flow has occurred. If the COVTE bit in the INTCON1

warning trap when saturation is disabled.

The overflow and saturation Status bits can optionally

be viewed in the STATUS register (SR) as the logical

OR of OA an d OB (in bit OAB) and the logical OR of SA

and SB (in bit SAB). Th is allows programm ers to check

one bit in the STATUS register to determine if either

accumulator has overflowed, or one bit to determine if

either a ccum ulator has satu rated. T his w ould be usefu l

for complex number arithmetic which typically uses

both the accu mulators.

The device supports three saturation and overflow

modes:

1. Bit 39 Overflow and Saturation:

When bit 39 overflow and saturation occurs, the

saturation logic load s the maximally positive 9.31

(0x7FFFFFFFFF), or maximally negative 9.31

value (0x8000000000) into the target accumula-

tor. The SA or SB bit is set and remains set until

cleared by the user. This is referred to as ‘super

saturation’ and provides protection against erro-

neous data or unexpected algorithm problems

(e.g., gain calculations).

2. Bit 31 Overflow and Saturation:

When bit 31 overflow and saturation occurs, the

saturation logic then loads the maximally posi-

tive 1.31 value (0x007FFFFFFF), or maximally

negative 1.31 value (0x0080000000) into the

target accumulator. The SA or SB bit is set and

remains set until cleared by the user. When this

Saturation mode is in effect, the guard bits are

not used, so the OA, OB or OAB bits are never

set.

3. Bit 39 Catastrophic Overflow:

The bit 39 overflow Status bit from the adder is

used to set the SA or SB bit which remain set

until cleared by the user. No saturation operation

is performed and the accumulator is allowed to

overflow (destroying its sign). If the COVTE bit in

the INTCON1 register is set, a catastrophic

ove rflow can initiate a trap exception.

2.4.2.2 Accumulator ‘Write-Back’

The MAC class of instructions (with the exception of

MPY, MPY.N, ED and EDAC) can optionally write a

rounded version of the high word (bits 31 through 16)

of the accumulator that is not t argeted by the instruction

into dat a spac e memory. The write is performe d across

the X bus into combined X and Y address space. The

following addressing modes are supported:

1. W13, Registe r Dire ct:

The rounded contents of the non-target

accumulator are written into W13 as a 1.15

fraction.

2. [W13]+=2, Register Indirect with Post-Increment:

The round ed contents of the non- target accumu-

lator are written into the address pointed to by

W13 as a 1.15 fraction. W13 is then

incremented by 2 (fo r a wo rd wr ite).

2.4.2.3 Round Logic

The round logic is a combinational block which per-

forms a conventional (biased) or convergent (unbi-

ased) round function during an accumulator write

(store). The Round mode is determined by the state of

the RND bit in the CORCON register . It generates a 16-

bit, 1.15 data value, which is passed to the data space

write satura tion logic . If rounding is not indica ted by the

instruction, a truncated 1.15 data value is stored and

the least significant word (lsw) is simply discarded.

Conventional rounding takes bit 15 of the accumulator,

zero-extends it and ad ds it to the AC CxH word (bi t s 16

through 31 of the accumulator). If the ACCxL word

(bits 0 through 15 of the accumulator) is between

0x8000 and 0xFFFF (0x8000 included), ACCxH is

incremented. If ACCxL is between 0x0000 and 0x7FFF,

ACCxH is left un ch anged. A conseque nc e of thi s alg o-

rithm is that over a succession of random rounding

operations, the value tends to be biased slightly posi-

tive.

Convergent (or unbiased) rounding operates in the

same manner as conventional rounding, except when

ACCxL equals 0x8000 . If this is the case, the Least Sig-

nificant bit (LSb) (bit 16 of the accumulator) of ACCxH

is examined. If it is ‘1’, ACCxH is incremented. If it is ‘0’,

ACCxH is not modified. Assuming that bit 16 is

ef fecti vely ran dom in nature , this sch eme remove s an y

rounding bias that may accumulate.

The SAC and SAC.R instructions store either a trun-

cated (SAC) or rounded (SAC.R) version of the cont ents

of th e ta rget ac cumu lator t o d ata memo ry vi a th e X bu s

(subject to data saturation, see Section 2.4.2.4 “Data

Space Write Saturation”). Note that for the MAC cl as s

of instructions, the accumulator write-back operation

functions in the same manner, addressing combined

MCU (X and Y) data space though the X bus. For this

class of instructions, the data is always subject to

rounding.

dsPIC30F3014/4013

2.4.2.4 Data Space Write Saturation

In addition to adder/subtracter saturation, writes to data

space may also be saturated but without affecting the

contents of the source accumulator. The data space

write saturation logic block accepts a 16-bit, 1.15

fractional value from the round logic block as its input,

together with overflow status from the original source

(accumulator) and the 16-bit round adder. These are

combined and used to select the appropriate 1.15

fractional value as output to write to data space

memory.

If the SATDW bit in the CORCON register is set, data

(after roundi ng or trun ca tio n) is tes te d for ove rflo w and

adjusted accordingly. For input data greater than

0x007FFF, data written to memory is forced to the

maximum positive 1.15 value, 0x7FFF. For input data

less than 0xFF8000, data written to memory is forced

to the maximum negative 1.15 value, 0x8000. The

Most Sig nific ant bit (MSb) of t he sou rce (bit 39) is use d

to determine the sign of the operand being tested.

If the SATDW bit in the CORCON register is n ot set, the

input data is always passed through unmodified under

all conditions.

2.4.3 BARREL SHIFTER

The barrel shifter is capable of performing up to 16-bit

arithmetic or logic right shifts, or up to 16-bit left shifts

in a single cycle. The source can be either of the two

DSP accumulators, or the X bus (to support multi-bit

shifts of register or memory data).

The sh ifter requires a s ign ed bi nary v al ue to de term in e

both the m agnitude (number of bits) and direction of the

shift op eration. A positive value shifts the o perand right.

A negative value shifts the operand left. A value of ‘0’

does not modify the operand.

The barrel shifter is 40 bits wide, thereby obtaining a

40-bit res ult for DSP shift ope rations an d a 16-bit resu lt

for MCU shift operations. Data from the X bus is

prese nte d to the ba rrel shif ter betwe en bi t pos iti ons 16

to 31 for right shifts, and bit positions 0 to 16 for left

shifts.

dsPIC30F3014/4013

NOTES:

dsPIC30F3014/4013

3.0 MEMORY ORGANIZATION

3.1 Program Address Space

The program address space is 4M instruction words. It

is addressable by a 24-bit value from either the 23-bit

PC, table instruction Effective Address (EA), or data

space EA, when program space is mapped into data

space as defined by Table 3-1. Note that the program

spa ce add ress i s increm ented b y tw o betwee n suc ces-

sive program words in order to provide compatibility

with data space addressing.

FIGURE 3-1: dsPIC30F3 014 PROGRAM

SPACE MEMORY MAP

User program space access is restricted to the lower

4M instruction word address range (0x000000 to

0x7FFFFE) for al l acces se s other than TBLRD/TBLWT,

which use TBLPAG<7> to deter mine user or c onfigura-

tion space access. In Table 3-1, Program Space

Address Construction, bit 23 allows access to the

Device ID, the User ID and the Configuration bits.

Otherwise, bit 23 is always clear.

FIGURE 3-2: dsPIC30F4013 PROGRAM

SPACE MEMORY MAP

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046). For more information on the device

instruction set and programming, refer to the “dsPIC30F/

33F Programmer’s Reference Manual” (DS70157).

Reset – Target Address

User Memory

Space

User Flash

Program Memory

Configuration Memory

Space

(8K instructions)

Reset – GOTO Instruction

Alternate V e ctor Table

Reserved

Interrupt Ve ctor Table

Vector Tables

000000

00007E

000002

000080

Device Configuration

004000

003FFE

Data EEPROM

(1 Kbyte)

800000

F80000

Registers F8000E

F80010

DEVID (2)

FEFFFE

FF0000

FF0002

Reserved

F7FFFE

Reserved

7FFC00

7FFBFE

(Read ‘0’s)

8005FE

800600

UNITID (32 instr.)

8005BE

8005C0

000004

Reserved

7FFFFE

Reserved

000100

0000FE

000084

Reset – Target Address

User Memory

Space

000000

00007E

000002

000080

Device Configuration

User Fl as h

Program Memory

004000

007FFE

Configuration Memory

Space

Data EEPROM

(16K instructions)

(1 Kbyte)

800000

F80000

Registers F8000E

F80010

DEVID (2)

FEFFFE

FF0000

FF0002

Reserved

F7FFFE

Reserved

7FFC00

7FFBFE

(Read ‘0’s)

8005FE

800600

UNITID (32 instr.)

8005BE

8005C0

Reset – GOTO Instruction

000004

Reserved

7FFFFE

Reserved

000100

0000FE

000084

Alterna te Vector Table

Reserved

Interrupt V e ctor Table

Vector Tables

dsPIC30F3014/4013

TABLE 3-1: PROGRAM SPACE ADDRESS CONSTRUCTION

FIGURE 3-3: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION

Access Type Access

Space Program Space Address

<23> <22:16> <15> <14:1> <0>

Instruction Access User 0PC<22:1> 0

TBLRD/TBLWT User

(TBLPAG<7> = 0)TBLPAG<7:0> Data EA<15:0>

TBLRD/TBLWT Configuration

(TBLPAG<7> = 1)TBLPAG<7:0> Data EA<15:0>

Program Space Visibility User 0PSVPAG<7:0> Data EA<14:0>

0Prog ram Count er

23 bits

PSVPAG Reg

8 bits

15 bi ts

Program

Using

Select

TBLPAG Reg

8 bits

16 bit s

Using

Byte

24-bit EA

1/0

Select

User/

Configuration

Table

Instruction

Program

Space

Counter

Using

Space

Select

Visibility

Note: Program sp ace visibility cannot be used to access bits <23:16 > of a word in program memory .

© 2007 Microchip Technology Inc. DS70138E-page 25
dsPIC30F3014/4013
3.1.1 DATA ACCESS FROM PROGRAM 
MEMORY USING TABLE 
INSTRUCTIONS
This arc hit ec ture f etc hes  24 -bi t w ide  prog ram  me mo ry.
Consequently, instructions are always aligned.
However, as the architecture is modified Harvard, data
can also be present in program space.
There are two methods by which program space can
be accessed: via special table instructions, or through
the rema ppi ng of a 16K w ord  prog ram  space page into
the u pp e r  half  o f  da ta space (s ee  Section 3.1.2 “Data
Access from Program Memory Using Program
Space Visibility”). The TBLRDL and TBLWTL instruc-
tions offer a direct method of reading or writing the lsw
of any address within program space, without going
through da ta spac e. The  TBLRDH and TBLWTH instru c-
tions are th e only metho d whereby the upp er 8 bits of a
program space word can be accessed as data.
The PC is incremented by two for each successive
24-bit program word. This allows program memory
addresses to directly map to data space addresses.
Program memory can thus be regarded as two 16-bit
word wide  add res s s p ac es , res id ing  sid e by  si de, each
with the same address range. TBLRDL and TBLWTL
access the space which contains the least significant
data  word,  and TBLRDH and TBLWTH ac cess the sp ac e
which contains the MS Data Byte.
Figure 3-3 shows h ow  th e EA  is  cre ate d fo r table op er-
ations and data space accesses (PSV = 1). Here,
P<23:0> refers to a program space word, whereas
D<15:0> refers to a data space word.
A set of t able inst ruc tions are prov ide d to move by te  or
word-sized data to and from program space. (See
Figure 3-4 and Figure 3-5.)
1. TBLRDL: Table Read Low
Word: Read the lsw of the program address;
P<15:0> maps to D<15:0>.
Byte: Read one of the LSBs of the program
address;
P<7:0> maps to the destination byte when byte
select = 0;
P<15:8> m aps to the d estination byte  when byte
select = 1.
2. TBLWTL: Ta ble  Write Low  (ref er to Section 5.0
“Flash Program Memory” for details on Flash
Programming)
3. TBLRDH: Table Read High
Word: Read the most significant word (msw) of
the program address; P<23:16> maps to D<7:0>;
D<15:8> will always be = 0.
Byte: Read one of the MSBs of the program
address;
P<23:16> maps to the destination byte when
byte select = 0;
The destination byte will always be = 0 when
byte select = 1.
4. TBLWTH: Table W ri te High (refer to Section 5.0
“Flash Program Memory” for details on Flash
Programming)
FIGURE 3-4: PROGRAM DATA TABLE ACCESS (LEAST SIGNIFICANT WORD)
0
8
16
PC Address
0x000000
0x000002
0x000004
0x000006
23
00000000
00000000
00000000
00000000
Progra m Mem or y
‘Pha nto m’ Byte
(read as ‘0’)
TBLRDL.W
TBLRDL.B (Wn<0> = 1)
TBLRDL.B (Wn<0> = 0)

dsPIC30F3014/4013

FIGURE 3-5: PROGRAM DATA TABLE ACCESS (MSB)

3.1.2 DATA ACCESS FROM PROGRAM

MEMORY USING PROGRAM

SPACE VISIBILITY

The upper 32 Kbytes of data space may optionally be

mapped into any 16K word program space page. This

provides transparent access of stored constant data

from X data space without the need to use special

instruc tio ns (i.e ., TBLRDL/H, TBLWTL/H ins tru cti ons).

Program space access through the data space occurs

if the MSb of the data space EA is set and program

space visibility is enabled by setting the PSV bit in the

Core Control register (CORCON). The functions of

CORCON are discussed in Section 2.4 “DSP

Engine”.

Data accesses to this area add an additional cycle to

the instruction being executed, since two program

memory fetch es are requ ire d.

Note that the upper half of addressable data space is

always part of the X data space. Therefore, when a

DSP ope ration uses p rogram sp ace mapp ing to acces s

this m em ory reg ion , Y d ata sp ac e s ho uld ty pic al ly co n-

tain state (variable) data for DSP operations, whereas

X data space should typically contain coefficient

(constant) da ta.

Although each dat a sp ace address, 0x8000 and higher ,

maps directly into a corresponding program memory

address (see Figure 3-6), only the lower 16 bits of the

24-bit program word are used to contain the data. The

upper 8 bits shoul d be progra mmed to forc e an illeg al

instruction to maintain machine robustness. Refer to

the “dsPIC30F/33F Programmer ’s Reference Manual”

(DS70157) for details on instruction encoding.

Note that by incrementing the PC by 2 for each

program memory word, the LS 15 bits of data space

addresses directly map to the LS 15 bits in the corre-

sponding program space addresses. The remaining

bits are prov id ed by the Program Spac e V is ib ili ty Pag e

For instructions that use PSV which are executed

outside a REPEAT loop:

• The following instructions require one instruction

cycle in addition to the specified execution time:

-MAC class of instructions with data operand

prefetch

-MOV instr ucti ons

-MOV.D instructions

• All ot her instructions require two ins truction cycles

in addition to the specified execution time of the

instruction.

For instructions that use PSV which are executed

inside a REPEAT loop:

• The following instances require two instruction

cycl es in addition to th e specified execution time

of the instruction:

- Execution in the first iteration

- Execution in the last iteration

- Execution prior to exiting the loop due to an

interrupt

- Execution upon re-entering the loop after an

interr upt is servi ced

• Any other iteration of the REPEAT loop allows the

instruc tion accessing da t a, using PSV, to execute

in a single cycle.

PC Address

0x000000

0x000002

0x000004

0x000006

00000000

Program Memory

‘Phantom’ Byte

(read as ‘0’)

TBLRDH.W

TBLRDH.B (Wn<0> = 1)

TBLRDH.B (Wn<0> = 0)

Note: PSV acc ess is tempo raril y disabl ed durin g

table reads/wr ites.

dsPIC30F3014/4013

FIGURE 3-6: DATA SPACE WINDOW INTO PROGRAM SPACE OPERATION

23 15 0

PSVPAG(1)

EA<15> =

EA<15> = 1

Data

Space

Data Space Program Space

15 23

0x0000

0x8000

0xFFFF

0x00

0x000100

0x007FFF

Data Read

Upper Half of Dat a

Space is Mapped

into Program Space

0x000200

Address

Concatenation

BSET CORCON,#2 ; PSV bit set

MOV #0x00, W0 ; Set PSVPAG register

MOV W0, PSVPAG

MOV 0x8200, W0 ; Access program memory location

; using a data space access

Note: PSVPAG is an 8-bit register, containing bits <22:15> of the program space address (i.e., it defines

the page in program space to which the upper half of data space is being mapped).

The memory map shown here is for a dsPIC30F4013 device.

dsPIC30F3014/4013

3.2 Data Address Space

The core has two data spaces. The data spaces can be

considered either separate (for some DSP instruc-

tions), o r as o ne u nified linear a ddre ss ran ge (fo r MC U

instruc tions). The dat a spaces are acces s ed usi ng two

Address Generation Units (AGUs) and separate data

paths.

3.2.1 DATA SPACE MEMORY MAP

The data space memory is split into two blocks, X and

Y data space. A key ele me nt of th is archi tec tur e is th at

Y space is a subset of X space, and is fully contained

within X space. In order to provide an apparent Linear

Addressing space, X and Y spaces have contiguous

addresses.

When executing any instruction other than one of the

MAC class of instructions, the X bloc k consists of the 64-

Kbyte data address space (including all Y addresses).

When executing one of the MAC class of instructions,

the X block consists of the 64-Kbyte data address

space excluding the Y address block (for data reads

only). In other words, all other instructions regard the

entire data memory as one composite address space.

The MAC cl ass inst ructions e xtract the Y addre ss spac e

from data space and address it using EAs sourced from

W10 and W11. The remaining X data space is

address ed using W8 an d W9. Both address spaces a re

concurrently accessed only with the MAC class

instructions.

The data space memory map is shown in Figure 3-7.

dsPIC30F3014/4013

FIGURE 3-7: dsPIC30F3014/dsPIC30F4013 DATA SPACE MEMORY MAP

0x0000

0x07FE

0x0BFE

0xFFFE

LSB

Address

16 bits

LSBMSB

MSB

Address

0x0001

0x07FF

0x0BFF

0xFFFF

0x8001 0x8000

Optionally

Mapped

into Program

Memory

0x0FFF 0x0FFE

0x10000x1001

0x0801 0x0800

0x0C01

0x0C00

Near

Data

0x1FFE 0x1F FF

2 Kbyte

SFR Space

2 Kbyt e

SRAM Space

8 Kbyte

Space

X Data

Unimplemented (X)

SFR Space

X Data RAM (X)

Y Data RAM (Y)

dsPIC30F3014/4013

FIGURE 3-8: DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS EXAMPLE

SFR SPACE

(Y SPACE)

X SPACE

SFR SPACE

UNUSED

X SPACE

Y SPACE

UNUSED

Non-MAC Class Ops (Read/Write) MAC Class Op s ( Re ad )

Indirect EA using any W Indirect EA using W8, W9 Indirect EA using W10, W11

MAC Class Ops (Write)

dsPIC30F3014/4013

3.2.2 DATA SPACES

The X data space is used by all instructions and sup-

ports all addressing modes. There are separate read

and write data buses. The X read data bus is the return

data path for all instructions that view data space as

combined X and Y address space. It is also the X

address space data path for the dual operand read

instructions (MAC class). The X write data bus is the

only write path to data space for all instructions.

The X dat a sp ace also su pports Modulo Addre ssing for

all instructions, subject to addressing mode restric-

tions. Bit-Reversed Addressing is only supported for

writes to X data space.

The Y data space is used in concert with the X data

space by the MAC class of instructions (CLR, ED,

EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to

provide two concurrent data read paths. No writes

occur ac ros s th e Y bu s. T his cl as s of ins truc tions dedi-

cates two W regi ster pointers, W10 and W11, to alway s

address Y data space, independent of X data space,

whereas W8 and W9 always address X data space.

Note that during accumulator write-back, the data

address space is consi dere d a c om bin ati on of X and Y

data spaces, so the write occurs across the X bus.

Consequently, the write can be to any address in the

entire data space.

The Y data space can only be used for the data

prefetch operation associated with the MAC class of

instructions. It also supports Modulo Addressing for

automat ed c irc ul ar bu f fe r s. Of c ours e, all othe r ins tru c-

tions can access the Y dat a address sp ace through the

X data path as part of the composite linear space.

The boundary between the X and Y data spaces is

defined as shown in Figure 3-7 and is not user pro-

gramma ble. Shoul d an EA poin t to d ata out side it s own

assigned address space, or to a location outside phys-

ical memory, an all zero word/byte is returned. For

example, although Y address space is visible by all

non-MAC instructions using any addressing mode, an

attempt by a MAC instruction to fetch data from that

space using W8 or W9 (X space pointers) returns

0x0000.

TABLE 3-2: EFFECT OF INVALID

MEMORY ACCESSES

All Effective Addresses are 16 bits wide and point to

bytes within the data space. Therefore, the data space

address range is 64 Kbytes or 32K words.

3.2.3 DATA SPACE WIDTH

The core data width is 16 bits. All internal registers are

organ ized as 16-bit wide words. Data space memory is

organized in byte addressable, 16-bit wide blocks.

3.2.4 DATA ALI GNMENT

To help maintain backward compatibility with PIC®

MCU devices and improve data space memory usage

efficiency, the dsPIC30F instruction set supports both

word and byte operation s. Data is al igned in dat a mem-

ory and registers as words, but all data space EAs

resolve to bytes. Data byte reads read the complete

word whic h co nt ains the byt e, us ing the L Sb of an y EA

to determine which byte to select. The selected byte is

placed onto the LSB of the X data path (no byte

acces ses are possible fro m the Y data pa th as the MAC

class of instruction can only fetch words). That is, data

memory and registers are organized as two parallel

byte-wide entities with shared (word) address decode

but separate write lines. Data byte writes only write to

the corresponding side of the array or register which

matches the byte address.

As a consequence of this byte accessibility , all Ef fective

Address calc ulations (includin g those generate d by the

DSP operations which are restricted to word-sized

data) a re inter nally scale d to step thro ugh word ali gned

memory. For example, the core would recognize that

Post-Modified Register Indirect Addressing mode

[Ws++] will result in a value of Ws + 1 for byte

operations and Ws + 2 for word operations.

All word accesses must be al igned to an even a ddress.

Misaligned word data fetches are not supported so

care must be taken when mixing byte and word opera-

tions, or translating from 8-bit MCU code. Shoul d a mis-

aligned read or write be attempted, an address error

trap is generated. If the error occurred on a read, the

instruction underway is completed, whereas if it

occurred on a write, the instruction is executed but the

write does not occur. In either case, a trap is then exe-

cuted, allowing the system and/or user to examine the

machine state prior to execution of the address Fault.

FIGURE 3-9: DATA ALIGNMENT

Attempted Operation Data Returned

EA = an unimplemented address 0x0000

W8 or W9 used to access Y data

spa ce in a MAC instru ction 0x0000

W10 or W11 used to access X

data space in a MAC instruction 0x0000

15 8 7 0

0001

0003

0005

0000

0002

0004

Byte 1 Byte 0

Byte 3 Byte 2

Byte 5 Byte 4

LSBMSB

dsPIC30F3014/4013

All byte loads into any W register are loaded into the

LSB. The MSB is not modified.

A Sign-Extend (SE) instruction is provided to allow

users to translate 8-bit signed data to 16-bit signed

values. Alternatively, for 16-bit unsigned data, users

can clear the MSB of any W register by executing a

Zero-Extend (ZE) instruction on the appropriate

address.

Although m os t i ns truc tions are capable of operating o n

word or byte data sizes, it should be noted that some

instructions, including the DSP instructions, operate

only on words .

3.2.5 NEAR DATA SPACE

An 8-Kbyte ‘near’ data space is reserved in X address

memory space between 0x0000 and 0x1FFF, which is

directly add res sab le via a 13 -bit ab so lute address field

within all memory direct instructions. The remaining X

address space and all of the Y address space is

address able indirec tly. Additional ly, the whole of X da ta

space is addressable using MOV instructions, which

support memory direct addressing with a 16-bit

address field.

3.2.6 SOFTWARE STACK

The dsPI C DSC de vices cont ain a s oftware st ack. W1 5

is used as the Stack Pointer.

The Stack Pointer always points to the first available

free word and grows from lower addresses towards

higher addresses. It pre-decrements for stack pops

and post-increments for stack pushes as shown in

Figure 3-10. Note that for a PC push during any CALL

instruc tio n, the M SB o f t he PC i s ze ro-ex te nde d b efo re

the push, ensuring that the MSB is always clear.

There is a Stack Pointer Limit register (SPLIM) associ-

ated with the Stack Pointer. SPLIM is uninitialized at

Reset. As is t he case f or t h e Stack Point er, SPL IM < 0>

is forced to ‘0’ because all stack operations must be

word aligned. Whenever an Effective Address (EA) is

generated, using W15 as a source or destination

pointer, the address thus generated is compared with

the valu e i n SPL IM. If the cont ents of the Stack Po int er

(W15) and the SPLIM register are equal and a push

operation is performed, a stack error trap does not

occur. The stack error trap occurs on a subsequent

push operation. Thus, for example, if it is desirable to

cause a stack error trap when the stack grows beyond

address 0x2000 in RAM, initialize the SPLIM with the

value, 0x1FFE.

Similarl y, a S tack Po inter un derflow ( sta ck erro r) trap i s

generated when the Stack Pointer address is found to

be less than 0x0800, thus preventing the stack from

interfering with the Special Function Register (SFR)

space.

A write to the SPLIM register should no t be immediately

follow ed by an indirect read ope rati on usi ng W15.

FIGURE 3-10: CALL STACK FRAME

Note: A PC push during exception processing

concat enates the SRL regis ter to the M SB

of the PC prior to the push.

PC<15:0>

000000000

015

W15 (before CALL)

W15 (after CALL)

Stack Grows Towards

Higher Address

0x0000

PC<22:16>

POP : [--W15]

PUSH : [W15++]

dsPIC30F3014/4013

TABLE 3-3: CORE REGISTER MAP

SFR Name Address

(Home) Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

W0 0000 W0/WREG 0000 0000 0000 0000

W1 0002 W1 0000 0000 0000 0000

W2 0004 W2 0000 0000 0000 0000

W3 0006 W3 0000 0000 0000 0000

W4 0008 W4 0000 0000 0000 0000

W5 000A W5 0000 0000 0000 0000

W6 000C W6 0000 0000 0000 0000

W7 000E W7 0000 0000 0000 0000

W8 0010 W8 0000 0000 0000 0000

W9 0012 W9 0000 0000 0000 0000

W10 0014 W10 0000 0000 0000 0000

W11 0016 W11 0000 0000 0000 0000

W12 0018 W12 0000 0000 0000 0000

W13 001A W13 0000 0000 0000 0000

W14 001C W14 0000 0000 0000 0000

W15 001E W15 0000 1000 0000 0000

SPLIM 0020 SPLIM 0000 0000 0000 0000

ACCAL 0022 ACCAL 0000 0000 0000 0000

ACCAH 0024 ACCAH 0000 0000 0000 0000

ACCAU 0026 Sign Extension (ACCA<39>) ACCAU 0000 0000 0000 0000

ACCBL 0028 ACCBL 0000 0000 0000 0000

ACCBH 002A ACCBH 0000 0000 0000 0000

ACCBU 002C Sign Extension (ACCB<39>) ACCBU 0000 0000 0000 0000

PCL 002E PCL 0000 0000 0000 0000

PCH 0030 — — — — — — — — —PCH0000 0000 0000 0000

TBLPAG 0032 — — — — — — — —TBLPAG0000 0000 0000 0000

PSVPAG 0034 — — — — — — — — PSVPAG 0000 0000 0000 0000

RCOUNT 0036 RCOUNT uuuu uuuu uuuu uuuu

DCOUNT 0038 DCOUNT uuuu uuuu uuuu uuuu

DOSTARTL 003A DOSTARTL 0uuuu uuuu uuuu uuu0

DOSTARTH 003C — — — — — — — — —DOSTARTH0000 0000 0uuu uuuu

DOENDL 003E DOENDL 0uuuu uuuu uuuu uuu0

DOENDH 0040 — — — — — — — — — DOENDH 0000 0000 0uuu uuuu

SR 0042 OA OB SA SB OAB SAB DA DC IPL2 IPL1 IPL0 RA N OV Z C 0000 0000 0000 0000

Legend: u = uninitialized bit

1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of regi ster bi t fields.

dsPIC30F3014/4013

CORCON 0044 — — — US EDT DL2 DL1 DL0 SATA SATB SATDW ACCSAT IPL3 PSV RND IF 0000 0000 0010 0000

MODCON 0046 XMODEN YMODEN —— BWM<3:0> YWM<3:0> XWM<3:0> 0000 0000 0000 0000

XMODSRT 0048 XS<15:1> 0 uuuu uuuu uuuu uuu0

XMODEND 004A XE<15:1> 1 uuuu uuuu uuuu uuu1

YMODSRT 004C YS<15:1> 0 uuuu uuuu uuuu uuu0

YMODEND 004E YE<15:1> 1 uuuu uuuu uuuu uuu1

XBREV 0050 BREN XB<14:0> uuuu uuuu uuuu uuuu

DISICNT 0052 —— DISICNT<13:0> 0000 0000 0000 0000

TABLE 3-3: CORE REGISTER MAP (CONTINUED)

SFR Name Address

(Home) Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

Legend: u = uninitialized bit

1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of regi ster bi t fields.

dsPIC30F3014/4013

4.0 ADDRESS GENERATOR UNITS

The dsPIC DSC core contains two independent

address generator un its: the X AGU and Y AGU. The Y

AGU supports word-sized data reads for the DSP MAC

class of instructions only. The dsPIC DSC AGUs sup-

port three types of data addressing:

• Linear Addressing

• Modulo (Circular) Addressing

• Bit-Revers ed Addre ss in g

Linear and Modulo Data Addressing modes can be

applied to data space or program space. Bit-Reversed

Addressi ng is on ly appli cable to data s pace a ddresses .

4.1 I nstruction Addressing Modes

The addressing modes in Table 4-1 form the basis of

the address ing modes o ptimized to support the sp ecific

features of individual instructions. The addressing

modes provided in the MAC class of instructions are

somewhat different from those in the other instruction

types.

4.1.1 FILE REGISTER INSTRUCTIONS

Most fil e re gis ter i ns truc tio ns use a 13-bit ad dres s f iel d

(f) to directly address data present in the first 8192

bytes of data memory (near data space). Most file

whic h is den oted as WREG in these i nstruc tions. The

destination is typically either the same file register or

WREG (with the exception of the MUL instruction),

which w rites the re sult t o a re gister or regi ster p air. The

MOV instruction allows additional flexibility and can

access the entire data space during file register

operation.

4.1.2 MCU INSTRUCTIONS

The three-operand MCU instructions are of the form:

Operand 3 = Operand 1 <function> Operand 2

where O pe rand 1 is alw a ys a work in g reg ister (i.e., the

addressing mode can only be register direct), which is

referred to as Wb. Operand 2 can be a W register,

fetched from data memory or a 5-bit literal. The result

location can be either a W register or an address

location. The following addressing modes are

supported by MCU instructions:

• Register Direct

• Register Indirect

• Register Indirect Post-modified

• Register Indirect Pre-modified

• 5-bit or 10-bit Literal

TABLE 4-1: FUNDAMENTAL ADDRESSING MODES SUPPORTED

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046). For more information on the device

instruction set and programming, refer to the “dsPIC30F/

33F Programmer’s Reference Manual” (DS70157).

Note: Not all instructions sup port all the address-

ing modes given above. Individual

instructions may support different subsets

of these addressing modes.

Addressing Mode Description

File Register Direct The address of the File register is specified explicitly.

decremented) by a constant value.

Registe r Indire ct Pr e- m odi fie d Wn is pre-m odi fied (increment ed or de cre me nted ) by a si gne d con stant valu e

to form the EA.

dsPIC30F3014/4013

4.1.3 MOVE AND ACCUMULATOR

INSTRUCTIONS

Move instructions and the DSP accumulator class of

instructions provide a greater degree of addressing

flexibility than other instructions. In addition to the

addressing modes supported by most MCU instruc-

tions, move and accumulator instructions also support

mode, also referred to as Register Indexed mode.

In summary, the following addressing modes are

supported by move and accumulator instructions:

• Register Direc t

• Register Indi rec t

• Register Indi rec t Post-mod ifi ed

• Register Indi rec t Pre- mo dif ied

• Register Indirect with Register Offset (Indexed)

• Register Indirect with Literal Offset

• 8-bit Literal

• 16-bit Literal

4.1.4 MAC INSTRUCTIONS

The dual s ource op erand DSP ins tructio ns (CLR, ED,

EDAC, MAC, MPY, MPY.N, MOVSAC and MSC), als o

referred to a s MAC instruction s, utilize a si mplified se t of

addressing modes to allow the user to effectively

manipulate the data pointers through register indirect

tables.

The two source operand prefetch registers must be a

member of the set {W8, W9, W10, W11}. For data

reads, W8 and W9 is always directed to the X RAGU,

and W10 and W11 are always directed to the Y AGU.

The Effective Addresses generated (before and after

modification) must, therefore, be valid addresses within

X dat a sp ace f or W8 and W9 and Y data space for W10

and W11.

In summary, the following addressing modes are

supported by the MAC class of instructions:

• Register Indirect

• Register Indirect Post-modified by 2

• Register Indirect Post-modified by 4

• Register Indirect Post-modified by 6

• Register Indirect with Register Offset (Indexed)

4.1.5 OTHER INSTRUCTIONS

Besides the various addressing modes outlined ab ove,

some i nstructio ns use li teral con sta nts of various sizes.

For example, BRA (branch) instructions use 16-bit

signed l iterals to spe cify the branch de stination dire ctly ,

whereas the DISI instruction uses a 14-bit unsigned

literal field. In some instructions, such as ADD Acc, the

source of an operand or result is implied by the opc ode

it self. Cert ain opera tions, such as NOP, do not have any

operands.

4.2 Modulo Addressing

Modulo Addressing is a method of providing an

automat ed means to support ci rcular dat a buf fers using

hardware. The objective is to remove the need for

software to perform data address boundary checks

when executing tightly looped code, as is typical in

many DSP algorithms.

Modulo Addressing can operate in either data or

program space (since the data pointer mechanism is

essentially the same for both). One circular buffer can

be support ed in e ach o f the X ( which also provide s th e

pointers into program space) and Y data spaces.

Modulo Addressing can operate on any W register

pointer . However , it is not advisable to use W14 or W15

for Modulo Addressing since these two registers are

used as the Stack Frame Pointer and Stack Pointer,

respectively.

In general, any particular circular buffer can only be

configured to operate in one direction, as there are

certain restrictio ns on the buffer start address (for incre-

menting buffers), or end address (for decrementing

buffers) based upon the direction of the buffer.

The only exception to the usage restrictions is for

buffers that have a power-of-2 length. As these buffers

satisfy the start and end address criteria, they may

operate in a Bidirecti onal mode (i.e., addres s boundar y

checks are performed on both the lower and upper

address boundaries).

Note: For the MOV instructions, the addressing

mode specified in the instruction can differ

for the source and destination EA.

However, the 4-bit Wb (register offset)

field is shared between both source and

destination (but typically only used by

one).

Note: Not all instructions su pport all the address-

ing modes given above. Individual

instructions may support different subsets

of these addressing modes.

Note: Register Indirect with Register Offset

addressing is only available for W9 (in X

spa ce) and W11 (in Y space).

dsPIC30F3014/4013

4.2.1 START AND END ADDRESS

The Modulo Addressing s cheme requires that a start-

ing and an ending address be specified and loaded

into the 16-bit Modulo Buffer Address registers:

XMODSRT, XMODEND, YMODSRT and YMODEND

(see Table 3-3).

The leng th of a ci rcular buffer is not di rectly s pecified. It

is determined by the difference between the

corresp onding st art and end ad dress es. Th e ma ximu m

possible length of the circular buffer is 32K words

(64 Kbytes).

4.2.2 W ADDRESS REGISTER

SELECTION

The Mod ulo an d Bi t-Rev ers ed Add ress in g Co ntro l re g-

ister M O DCON <1 5:0 > c on t ai ns enable fla gs as w ell a s

a W register field to specify the W address registers.

The XWM and YWM fields se lect whic h registe rs oper-

ate with Modulo Addressing. If XWM = 15, X RAGU

and X WAGU Modulo Ad dressing is disab led. Simi larly,

if YWM = 15, Y AGU Modulo Addressing is disabled.

The X Address Space Pointer W register (XWM), to

which Modulo Addressing is to be applied, is stored in

MODCON <3:0> (see Tab le 3-3). Modul o Addre ssing is

enabled for X data sp ace when XWM is set to any v alue

other than ‘15’ and the XMODEN bit is set at

MODCON<15>.

The Y Address Space Pointer W register (YWM), to

which Modulo Addressing is to be applied, is stored in

MODCON<7:4>. Modulo Addressing is enabled for Y

data space when YWM is set to any value other than

‘15’ and the YMODEN bit is set at MODCON<14>.

FIGURE 4-1: MODULO ADDRESSING OPERAT ION EXAMPLE

Note: Y space Modulo Addressing EA calcula-

tions assume word-sized data (LSb of

ever y EA is always clear ).

0x0800

0x0863

Start Addr = 0x0800

End Addr = 0x0863

Length = 0x00 32 w ords

Byte

Address MOV #0x800,W0

MOV W0,XMODSRT ;set modulo start address

MOV #0x863,W0

MOV W0,MODEND ;set modulo end address

MOV #0x8001,W0

MOV W0,MODCON ;enable W1, X AGU for modulo

MOV #0x0000,W0 ;W0 holds buffer fill value

MOV #0x800,W1 ;point W1 to buffer

DO AGAIN,#0x31 ;fill the 50 buffer locations

MOV W0,[W1++] ;fill the next location

AGAIN: INC W0,W0 ;increment the fill value

dsPIC30F3014/4013

4.2.3 MODULO ADDRESSING

APPLICABILITY

Modulo Addressing can be applied to the Effective

Address (EA) calculation associated with any W regis-

ter. It is important to realize that the address bound-

aries c he ck fo r ad dre sses le ss th an or greater tha n th e

upper (for incrementing buffers) and lower (for decre-

menting buffers) boundary addresses (not just equal

to). Address changes may, therefore, jump beyond

boundaries and still be adjusted correctly.

4.3 Bi t-Reversed Addressing

Bit-Reversed Addressing is intended to simplify data

re-ordering for radix-2 FFT algorithms. It is supported

by t he X AGU for data writes only.

The m odifier, which ma y be a c onstant value or reg ister

contents, is regarded as having its bit order reve rsed. The

address source and destination are kept in normal order .

Thus, the only operand requiring reversal is the modifier .

4.3. 1 BIT-REVERSED ADDRESSING

IMPLEMENTATION

Bit-Reversed Addressing is enabled when:

1. BWM (W register selection) in the MODCON

cannot be accessed using Bit-Reversed

Addressing) and

2. the BREN bit is set in the XBREV register and

3. the addressing mode used is Register Indirect

with Pre-Increment or Post-Increment.

If the length of a bit-reversed buffer is M = 2N bytes,

then the last ‘N’ bits of the data buffer start address

must be zero s.

XB<14:0> is th e b it-re versed addres s mo difi er o r ‘p iv ot

point’ which is typically a constant. In the case of an

FFT computation, its value is equal to half of the FFT

dat a buffer size.

When enabled, Bit-Reversed Addressing is only exe-

cuted for Register Indirect with Pre-Increment or Post-

Increment addressing and word-sized data writes. It

does not functi on for an y othe r a ddre ss in g mode or for

byte sized data. Normal addresses are generated

instead. When Bit-Reversed Addressing is active, the

W Address Pointer is always added to the address

modifie r (XB) and the o ffset assoc iat ed w it h the Regis -

ter Indi rect Addressi ng m ode i s ign ore d. In add ition, as

wor d-s iz ed da ta is a r e qu ire m en t , th e L S b of the E A is

ignored (and always clear).

If Bit-Reversed Addressing has already been enabled

by setting the BREN (XBREV<15>) bit, then a write to

the XBREV register should not be immediately followed

by an indirect read operation using the W register that

has been designated as the Bit-Reversed Pointer.

FIGURE 4-2: BIT-REVERSED ADDRESS EXAMPLE

Note: The m odulo correcte d Effective Address is

written back to the re giste r only when Pre-

Modify or Post-Modify Addressing mode is

used to compute the Effective Address.

When an address offset (e.g., [W7+W2] ) is

used, modulo address correction is per-

formed but the contents of the register

remain unc han ged.

Note: All bit-reversed EA calculations assume

word-sized data (LSb of every EA is

always clear). The XB value is scaled

accordingly to generate compatible (byte)

addresses.

Note: Modulo Addressing and Bit-Reversed

Addressing should not be enabled

together . In the event that the user attempts

to do this, Bit-Reversed Addressing

assumes priority when active for the X

WAGU, and X WAGU Modulo Addressing

is disabled. However, Modulo Addressing

continues to function in the X RAGU.

b3 b2 b1 0

b2 b3 b4 0

Bit Locations Swapped Left-to-Right

Around Center of Binary Value

Bit-Reversed Address

XB = 0x0008 for a 16-word Bit-Reversed Buffer

b7 b6 b5 b1

b7 b6 b5 b4b11 b10 b9 b8

b11 b10 b9 b8

b15 b14 b13 b12

Sequential Address

Pivot Point

dsPIC30F3014/4013

TABLE 4-2: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY)

TABLE 4-3: BIT-REVERSED ADDRESS MODIFIER VALUES FOR XBREV REGISTER

Normal Address Bit-Reversed Address

A3 A2 A1 A0 Decimal A3 A2 A1 A0 Decimal

0000 00000 0

0001 11000 8

0010 20100 4

0011 31100 12

0100 40010 2

0101 51010 10

0110 60110 6

0111 71110 14

1000 80001 1

1001 91001 9

1010 10 0101 5

1011 11 1101 13

1100 12 0011 3

1101 13 1011 11

1110 14 0111 7

1111 15 1111 15

Buffer Size (Words) XB<14:0> Bit-Reversed Address Modifier Value

1024 0x0200

512 0x0100

256 0x0080

128 0x0040

64 0x0020

32 0x0010

16 0x0008

8 0x0004

4 0x0002

2 0x0001

dsPIC30F3014/4013

NOTES:

dsPIC30F3014/4013

5.0 FLASH PROGRAM MEMORY

The dsPIC30F family of devices contains internal

program Flash memory for executing user code. There

are two methods by which the user can program this

memory:

1. Run-Time Self-Programming (RTSP)

2. In-Circuit Serial Programming™ (ICSP™)

5.1 I n-Circuit Serial Programming

(ICSP)

dsPIC30F devices can be serially programmed while i n

the end ap plica tion ci rcuit. Th is is s imply do ne wit h two

lines for Programming Clock and Programming Data

(which are named PGC and PGD, respectively), and

three other lines for Power (VDD), Ground (VSS) and

Master Cl ear (MCLR ). This allows customers to manu-

facture boards with unprogrammed devices and then

program the microcontroller just before shipping the

product. This also allows the most recent firmware or a

custom firmware to be programmed.

5.2 Run-Time Self-Programming

(RTSP)

RTSP is accomplished using TBLRD (table read) and

TBLWT (table wr ite) ins tru cti ons .

With RTSP, the user may erase program memory, 32

instruc tions (96 bytes) at a tim e an d c an wr it e pro gram

memory data, 32 instructions (96 bytes) at a time.

5.3 Table Instruction Operation

Summary

The TBLRDL and the TBLWTL instructions are used to

read or write to bits<15:0> of program memory.

TBLRDL and TBLWTL can access program memory in

Word or Byte mode.

The TBLRDH and TBLWTH i nstructio ns are used to read

or write to bits<23:16> of program memory. TBLRDH

and TBLWTH can access program memory in Word or

Byte mode.

A 24-bit program memory address is formed using

bits<7:0> of the TBLPAG register and the Effective

Address (EA) from a W register specified in the table

instruction, as shown in Figure 5-1.

FIGURE 5-1: ADDRESSING FOR TABLE AND NVM REGISTERS

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046). For more information on the device

instruction set and programming, refer to the “dsPIC30F/

33F Programmer’s Reference Manual” (DS70157).

Program Counter

24 bits

NVMADRU Reg

8 bits 16 bits

Program

Using

TBLPAG Reg

8 bits

Working Reg EA

16 bits

Using

Byte

24-bit EA

1/0

Select

Table

Instruction

NVMADR

Addressing

Counter

Using

NVMADR Reg EA

User/Configuration

Space Select

dsPIC30F3014/4013

5.4 RTSP Operati on

The dsPIC30F Flash program memory is organized

into rows and panels. Each row consists of 32 instruc-

tions or 96 bytes. Each panel consists of 128 rows or

4K x 24 instructions. RTSP allows the user to erase one

row (32 instructions) at a time and to program four

instructions at one time. RTSP may be used to program

multipl e program me mory p anels, but th e Table Pointer

must be changed at each panel boundary.

Each panel of program memory contains write latches

that hold 32 instructions of programming data. Prior to

the actual programming operation, the write data must

be loaded into the panel write latches. The data to be

programmed into the panel is loaded in sequential

order into the write latches; instruction 0, in str uct i on 1,

etc. T he i ns truc tio n words loaded m us t a lway s b e fro m

a 32 address boundary.

The basi c sequence for R TSP programming is to set up

a Table Pointer, then do a series of TBLWT instructions

to load th e wri te latc hes. Program ming is perfo rmed by

setting the special bits in the NVMCON register. 32

TBLWTL and four TBLWTH instructions are required to

load the 32 instructions. If multiple panel programming

is requ ired, th e Table Pointer needs to be chan ged an d

the next set of multiple write latches written.

All of the table write operations are single-word writes

(2 instruction cycles), because only the table latches

are written. A programming cycle is required for

programming each row.

The Flash Program Memory is readable, writable and

erasable during normal operation over the entire VDD

range.

5.5 Control Registers

The four SFRs used to read and write the program

Flash memory are:

•NVMCON

• NVMADR

• NVMADRU

• NVMKEY

5.5.1 NVMCON REGISTER

The NVMCON register controls which blocks are to be

erased, which memory type is to be programmed, and

start of the programming cycle.

5.5.2 NVMADR REGISTER

The NVMADR register is used to hold the lower two

bytes of the Effective Address. The NVMADR register

captures the EA<15 :0> of the last table instru ct ion that

has been executed and selects the row to write.

5.5.3 NVMADRU REGISTER

The NVMADRU register is used to hold the upper byte

of the Effective Address. The NVMADRU register cap-

tures the EA<23:16> of the last table instruction that

has been exec uted.

5.5. 4 NVMKEY REGISTER

NVMKEY is a write-only register that is used for write

protection. To start a programming or an erase

sequence, the user must consecutively write 0x55 and

0xAA to the NVMKEY register. Refer to Section 5.6

“Programming Operations” for further details.

Note: The user can also directly write to the

NVMADR and NVMADRU registers to

specify a program memory address for

erasing or programming.

dsPIC30F3014/4013

5.6 Pr ogramming Operations

A complete programming sequence is necessary for

programming or erasing the internal Flash in RTSP

mode. A progra mming operati on is nominally 2 ms ec in

duration and the processor stalls (waits) until the oper-

ation is finished. Setting the WR bit (NVMCON<15>)

starts the operation and the WR bit is automatically

cleared when the operation is finished.

5.6.1 PROGRAMMING ALGORITHM FOR

PROGRAM FLASH

The user can erase or program one row of program

Flash memory at a time. The general process is:

1. Read one row of program Flash (32 instruction

words) and store into data RAM as a data

“image”.

2. Update the data image with the desired new

data.

3. Eras e program Flash row.

a) Setup NVMCON register for multi-word,

program Flash, erase, and set WREN bit.

b) Write address of row to be erased into

NVMADRU/NVMDR.

c) Write ‘55’ to NVMKEY.

d) Write ‘AA’ to NVMKEY.

e) Set the WR bit. This begins erase cycle.

f) CPU stalls for the duration of the erase cycle.

g) The WR bit is cleared when erase cycle

ends.

4. Write 32 instruction words of data from data

RAM “image” into the program Flash write

latches.

5. Program 32 instruction words into program

Flash.

a) Setup NVMCON register for multi-word,

program Flash, program, and set WREN

bit.

b) Write ‘55’ to NVMKEY.

c) Write ‘AA’ to NVMKEY.

d) Set the WR bit. This begins program cycle.

e) CPU stalls for duration of the program cycle.

f) The WR bit is cleared by the hardware

when program cycle ends.

6. Repeat step s 1 through 5 as needed to program

desired amount of program Flash memory.

5.6.2 ERASING A ROW OF PROGRAM

MEMORY

Example 5-1 shows a co de seque nce that can be used

to erase a row (32 instructions) of program memory.

EXAMPLE 5-1: ERASING A ROW OF PROGRAM MEMORY

; Setup NVMCON for erase operation, multi word write

; program memory selected, and writes enabled

MOV #0x4041,W0 ;

MOV W0,NVMCON ; Init NVMCON SFR

; Init pointer to row to be ERASED

MOV #tblpage(PROG_ADDR),W0 ;

MOV W0,NVMADRU ; Initialize PM Page Boundary SFR

MOV #tbloffset(PROG_ADDR),W0 ; Intialize in-page EA[15:0] pointer

MOV W0, NVMADR ; Initialize NVMADR SFR

DISI #5 ; Block all interrupts with priority <7 for

; next 5 instructions

MOV #0x55,W0

MOV W0,NVMKEY ; Write the 0x55 key

MOV #0xAA,W1 ;

MOV W1,NVMKEY ; Write the 0xAA key

BSET NVMCON,#WR ; Start the erase sequence

NOP ; Insert two NOPs after the erase

NOP ; command is asserted

dsPIC30F3014/4013

5.6.3 LOADING WRITE LATCHES

Example 5-2 shows a sequence of instructions that

can be used to load the 96 bytes of write latches. 32

TBLWTL and 32 TBLWTH instructions are needed to

load the w rite lat ches selected by the Tabl e Pointer.

5.6.4 INITI ATING THE PROGRAMMING

SEQUENCE

For pr otection, the w rite in itiate sequ ence f or NVMKEY

must be used to allow any erase or program operation

to procee d. After the prog ramming com mand has bee n

executed, the user must wait for the programming time

until programming is complete. The two instructions

following the start of the programming sequence

should be NOPs as shown in Example 5-3.

EXAMP L E 5-2: L OA DIN G WRIT E LA TCHES

EXAMPLE 5-3: INITIATING A PROGRAMMING SEQUENCE

; Set up a pointer to the first program memory location to be written

; program memory selected, and writes enabled

MOV #0x0000,W0 ;

MOV W0,TBLPAG ; Initialize PM Page Boundary SFR

MOV #0x6000,W0 ; An example program memory address

; Perform the TBLWT instructions to write the latches

; 0th_program_word

MOV #LOW_WORD_0,W2 ;

MOV #HIGH_BYTE_0,W3 ;

TBLWTL W2,[W0] ; Write PM low word into program latch

TBLWTH W3,[W0++] ; Write PM high byte into program latch

; 1st_program_word

MOV #LOW_WORD_1,W2 ;

MOV #HIGH_BYTE_1,W3 ;

TBLWTL W2,[W0] ; Write PM low word into program latch

TBLWTH W3,[W0++] ; Write PM high byte into program latch

; 2nd_program_word

MOV #LOW_WORD_2,W2 ;

MOV #HIGH_BYTE_2,W3 ;

TBLWTL W2, [W0] ; Write PM low word into program latch

TBLWTH W3, [W0++] ; Write PM high byte into program latch

•

; 31st_program_word

MOV #LOW_WORD_31,W2 ;

MOV #HIGH_BYTE_31,W3 ;

TBLWTL W2, [W0] ; Write PM low word into program latch

TBLWTH W3, [W0++] ; Write PM high byte into program latch

Note: In Example 5-2, the contents of the upper byte of W3 has no effect.

DISI #5 ; Block all interrupts with priority <7 for

; next 5 instructions

MOV #0x55,W0 ;

MOV W0,NVMKEY ; Write the 0x55 key

MOV #0xAA,W1 ;

MOV W1,NVMKEY ; Write the 0xAA key

BSET NVMCON,#WR ; Start the erase sequence

NOP ; Insert two NOPs after the erase

NOP ; command is asserted

dsPIC30F3014/4013

TABLE 5-1: NVM REGISTER MAP

File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All RESETS

NVMCON 0760 WR WREN WRERR — — — —TWRI — PROGOP<6:0> 0000 0000 0000 0000

NVMADR 0762 NVMADR<15:0> uuuu uuuu uuuu uuuu

NVMADRU 0764 — — — — — — — — NVMADR<23:16> 0000 0000 uuuu uuuu

NVMKEY 0766 — — — — — — — — KEY<7:0> 0000 0000 0000 0000

Legend: u = uninitialized bit

2: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

dsPIC30F3014/4013

NOTES:

dsPIC30F3014/4013

6.0 DATA EEPROM MEMORY

The data EEPROM memory is readable and writable

during no rmal operatio n over the enti re VDD range. The

data EEPROM memory is directly mapped in the

program memory address space.

The four SFRs used to read and write the program

Flash memory are used to access data EEPROM

memory, as well. As described in Section 5.5 “Control

Registers”, these registers are:

•NVMCON

• NVMADR

• NVMADRU

• NVMKEY

The EEPR OM data memory allows read and writ e of

single words and 16-word blocks. When interfacing to

data memory, NVMADR, in conjunction with the

NVMADRU register, are used to address the

EEPROM location being accessed. TBLRDL and

TBLWTL instructions are used to read and write data

EEPROM. The dsPIC30F devices have up to 8 Kbytes

(4K words) of data EEPROM with an address range

from 0x7FF000 to 0x7FFFFE.

A word wri te operatio n should be prec eded by an e rase

of the corresponding memory location(s). The write

typically requires 2 ms to complete, but the write time

varies with voltage and tempe r atur e.

A program or erase operation on the data EEPROM

does n ot sto p the ins truc tion fl ow. The us er is r espon -

sible for waiting for the appropriate duration of time

before initiating another data EEPROM write/erase

operation. Attempting to read the data EEPROM while

a programming or erase operation is in progress results

in unspecified data.

Control bit WR initiates write operations similar to

prog ram Fl ash wri tes. This bi t canno t be clea red, only

set, in software. They are cleared in hardware at the

completion of the write operation. The inability to clear

the WR bit in software prevents the accidental or

premature termination of a write operation.

The WREN bit, when set, allows a write operation. On

power-u p, the WREN bi t is cle ar . The WRERR bit is set

when a writ e opera tion i s inte rrupted by a MC LR Reset

or a WDT Time-out Reset during normal operation. In

these situations, following Reset, the user can check

the WRERR bit and rewrite the location. The address

6.1 Reading the Data EEPROM

A TBLRD instruction reads a word at the current

program word address. This example uses W0 as a

pointer to data EEPROM. The result is placed in

EXAMPLE 6-1: DATA EEPROM READ

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046). For more information on the device

instruction set and programming, refer to the “dsPIC30F/

33F Programmer’s Reference Manual” (DS70157).

Note: Interrupt flag bit NVMIF in the IFS0 regis-

ter is set when write is complete. It must be

cleared in software.

MOV #LOW_ADDR_WORD,W0 ; Init Pointer

MOV #HIGH_ADDR_WORD,W1

MOV W1,TBLPAG

TBLRDL [ W0 ], W4 ; read data EEPROM

dsPIC30F3014/4013

6.2 Er asing Data EEPROM

6.2.1 ERASI NG A BLOCK OF DATA

EEPROM

In order to erase a block of data EEPROM, the

NVMADRU and NVMAD R registers must initially point

to the block of memory to be erased. Configure

NVMCON for erasing a block of data EEPROM and

set the WR and WR EN bits in the NVMCON re gister.

Setting the WR bit initiates the erase, as shown in

Example 6-2.

6.2.2 ERASING A WORD OF DATA

EEPROM

The NVMADRU and NVMADR registers must point to

the block. Select a block of data Flash and set the WR

and WREN bits in the NVMCON register. Setting the

WR bit initiates the er ase, as shown in Example 6-3.

EXAMPLE 6-2: DATA EEPROM BLOCK ERASE

EXAMPLE 6-3: DATA EEPROM WORD ERASE

; Select data EEPROM block, WR, WREN bits

MOV #4045,W0

MOV W0,NVMCON ; Initialize NVMCON SFR

; Start erase cycle by setting WR after writing key sequence

DISI #5 ; Block all interrupts with priority <7 for

; next 5 instructions

MOV #0x55,W0 ;

MOV W0,NVMKEY ; Write the 0x55 key

MOV #0xAA,W1 ;

MOV W1,NVMKEY ; Write the 0xAA key

BSET NVMCON,#WR ; Initiate erase sequence

NOP

; Erase cycle will complete in 2mS. CPU is not stalled for the Data Erase Cycle

; User can poll WR bit, use NVMIF or Timer IRQ to determine erasure complete

; Select data EEPROM word, WR, WREN bits

MOV #4044,W0

MOV W0,NVMCON

; Start erase cycle by setting WR after writing key sequence

DISI #5 ; Block all interrupts with priority <7 for

; next 5 instructions

MOV #0x55,W0 ;

MOV W0,NVMKEY ; Write the 0x55 key

MOV #0xAA,W1 ;

MOV W1,NVMKEY ; Write the 0xAA key

BSET NVMCON,#WR ; Initiate erase sequence

NOP

; Erase cycle will complete in 2mS. CPU is not stalled for the Data Erase Cycle

; User can poll WR bit, use NVMIF or Timer IRQ to determine erasure complete

dsPIC30F3014/4013

6.3 Writing to the Data EEPROM

To write an EEPROM data location, the following

sequen ce must be followed :

1. Erase data EEPROM word.

a) Select word, data EEPROM erase, and set

WREN bit in NVMCO N regis ter.

b) Write address of word to be erased into

NVMADR.

c) Enable NVM interrupt (optional).

d) Write ‘55’ to NVMK EY.

e) Write ‘AA’ to NVMKEY.

f) Set the WR bit. This begins erase cycle.

g) Either poll NVMIF bit or wait for NVMIF

interrupt.

h) The W R bit is cleare d whe n the era se cy cle

ends.

2. Write data word into data EEPROM write

latches.

3. Program 1 data word into data EEPROM.

a) Select word, data EEPROM program, and

set WREN bit in NVMCON register.

b) Enable NVM write done i nterrup t (o ptiona l).

c) Write ‘55’ to NVMKEY.

d) Write ‘AA’ to NVMKEY.

e) Set the WR bit. This begins program cycle.

f) Either poll NVMIF bit or wait for NVM

interrupt.

g) The WR bit is cleared when the write cycle

ends.

The write doe s not initiate if the above sequen ce is n ot

exactly followed (write 0x55 to NVMKEY, write 0xAA to

NVMCON, then set WR bit) for each word. It is strongly

recommended that interrupts be disabled during this

code segment.

Additionally, the WREN bit in NVMCON must be set to

enable writes. This mechanism prevents accidental

writes to data EEPROM due to unexpected code exe-

cution. The WREN bit should be kept clear at all times

except when updating the EEPROM. The WREN bit is

not cleared by hardware.

After a write sequence has been initiated, clearing the

WREN bit does not affect the current write cycle. The

WR bit is inhibited from bei ng s et un le ss the WREN b it

is set. The WREN bit must be set o n a previous instruc -

tion. Both WR a nd WREN c an not be se t with th e s am e

instruction.

At the completion of the write cycle, the WR bit is

cleared in ha rdware and the No nv ola til e M emory Write

Complete Interrupt Flag bit (NVMIF) is set. The user

may either enable this interrupt or poll this bit. NVMIF

must be cleared by software.

6.3.1 WRITING A WORD OF DATA

EEPROM

Once the user has erased the word to be programme d,

then a table write instruction is used to write one write

latch, as shown in Example 6-4.

6.3. 2 WRITING A BLOCK OF DATA

EEPROM

To write a block of data EEPROM, write to all sixteen

latches first, then set the NVMCON register and

program the block, as shown in Example 6-5.

EXAMPLE 6-4: DATA EEPROM WORD WRITE

; Point to data memory

MOV #LOW_ADDR_WORD,W0 ; Init pointer

MOV #HIGH_ADDR_WORD,W1

MOV W1,TBLPAG

MOV #LOW(WORD),W2 ; Get data

TBLWTL W2,[ W0] ; Write data

; The NVMADR captures last table access address

; Select data EEPROM for 1 word op

MOV #0x4004,W0

MOV W0,NVMCON

; Operate key to allow write operation

DISI #5 ; Block all interrupts with priority <7 for

; next 5 instructions

MOV #0x55,W0

MOV W0,NVMKEY ; Write the 0x55 key

MOV #0xAA,W1

MOV W1,NVMKEY ; Write the 0xAA key

BSET NVMCON,#WR ; Initiate program sequence

NOP

; Write cycle will complete in 2mS. CPU is not stalled for the Data Write Cycle

; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete

dsPIC30F3014/4013

EXAMPLE 6-5: DATA EEPROM BLOCK WRITE

6.4 Write Verify

Depending on the application, good programming

practice may dictate that the value written to the mem-

ory should be verified against the original value. This

should be used in applications where excessive writes

can stress bits near the specification limit.

6.5 Protection Against Spurious Write

There are conditions when the device may not want to

write to the data EEPROM memory. To protect against

spurious EEPROM writes, various mechanisms have

been built-in. On power-up, the WREN bit is cleared;

also, the Power-up Ti mer prevents EEPROM write.

The writ e in iti ate sequence an d the WR EN bi t tog eth er

help prevent an accidental write during brown-out,

power glitch or software malfunction.

MOV #LOW_ADDR_WORD,W0 ; Init pointer

MOV #HIGH_ADDR_WORD,W1

MOV W1,TBLPAG

MOV #data1,W2 ; Get 1st data

TBLWTL W2,[ W0]++ ; write data

MOV #data2,W2 ; Get 2nd data

TBLWTL W2,[ W0]++ ; write data

MOV #data3,W2 ; Get 3rd data

TBLWTL W2,[ W0]++ ; write data

MOV #data4,W2 ; Get 4th data

TBLWTL W2,[ W0]++ ; write data

MOV #data5,W2 ; Get 5th data

TBLWTL W2,[ W0]++ ; write data

MOV #data6,W2 ; Get 6th data

TBLWTL W2,[ W0]++ ; write data

MOV #data7,W2 ; Get 7th data

TBLWTL W2,[ W0]++ ; write data

MOV #data8,W2 ; Get 8th data

TBLWTL W2,[ W0]++ ; write data

MOV #data9,W2 ; Get 9th data

TBLWTL W2,[ W0]++ ; write data

MOV #data10,W2 ; Get 10th data

TBLWTL W2,[ W0]++ ; write data

MOV #data11,W2 ; Get 11th data

TBLWTL W2,[ W0]++ ; write data

MOV #data12,W2 ; Get 12th data

TBLWTL W2,[ W0]++ ; write data

MOV #data13,W2 ; Get 13th data

TBLWTL W2,[ W0]++ ; write data

MOV #data14,W2 ; Get 14th data

TBLWTL W2,[ W0]++ ; write data

MOV #data15,W2 ; Get 15th data

TBLWTL W2,[ W0]++ ; write data

MOV #data16,W2 ; Get 16th data

TBLWTL W2,[ W0]++ ; write data. The NVMADR captures last table access address.

MOV #0x400A,W0 ; Select data EEPROM for multi word op

MOV W0,NVMCON ; Operate Key to allow program operation

DISI #5 ; Block all interrupts with priority <7 for

; next 5 instructions

MOV #0x55,W0

MOV W0,NVMKEY ; Write the 0x55 key

MOV #0xAA,W1

MOV W1,NVMKEY ; Write the 0xAA key

BSET NVMCON,#WR ; Start write cycle

NOP

dsPIC30F3014/4013

7.0 I/O PORTS

All of the device pins (except VDD, VSS, MCLR and

OSC1/CLKI) are shared between the peripherals and

the parallel I/O ports.

All I/O input ports feature Schmitt Trigger inputs for

improved noise immunity.

7.1 Pa rallel I/O (P I O ) P o rts

When a peripheral is enabled and the peripheral is

actively driving an associated pin, the use of the pin as

a general purpose output pin is disabled. The I/O pin

can be read, but the output driver for the parallel port bit

is dis abled . If a p eriphe ral is enabl ed but the p eriphera l

is not actively driving a pin, that pin can be driven by a

port.

All port pins have three registers directly associated

with the operation of the port pin. The Data Direction

or an output. If the data direction bit is a ‘1’, t hen the pin

is an input. All port pins are defined as inputs after a

Reset.

Reads from the latch (LATx), read the latch. Writes to

the latch, write the latch (LATx). Reads from the port

(PORTx ), read th e port pi ns and writes to the port p ins,

write the latch (LATx).

Any bit and its associated data and control registers

that are not valid for a particular device are disabled,

which means the corresponding LATx and TRISx

registers and the port pin read as zeros.

When a pin is shared with another peripheral or func-

tion that is defined as an input only, it is nevertheless

regarded as a dedicated port because there is no

other competing source of outputs. An example is the

INT4 pin.

A parallel I/O (PIO) port that shares a pin with a periph-

eral is, in general, subservient to the peripheral. The

peripheral’s output buffer data and control signals are

provided to a pair of multiplexers. The multiplexers

select whether the peripheral or the associated port

has own ership of the outp ut dat a and co ntrol si gnals of

the I/O pad cell. Figure 7-2 shows how ports are shared

with oth er perip herals and the a ssociat ed I/O c ell (p ad)

to which they are connected. Table 7-1 shows the

formats of the registers for the shared ports, PORTB

through PORTF.

FIGURE 7-1: BLOCK DIAGRAM OF A DEDICATED PORT STRUCTURE

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046).

Note: The actual bits in use vary between

devices.

WR LAT +

TRIS Latch

I/O Pad

WR Port

Data Bus

Data Latch

Read LAT

Read Port

Read TRIS

WR TRIS

I/O Cell

Dedicated Port Module

dsPIC30F3014/4013

FIGURE 7-2: BLOCK DIAGRAM OF A SHARED PORT STRUCTURE

7.2 Conf iguring Analog Port Pins

The use of the ADPC FG and TRIS registers control the

operation of the A/D port pins. The port pins that are

desired as analog inputs must have their correspond-

ing TRIS bit set (input). If the TRIS bit is cleared

(output), the digital output level (VOH or VOL) is

converted.

When the PORT re gi ste r is rea d, all pi ns co nfi gure d a s

analog input channels are read as cleared (a low level).

Pins configured as digital inputs will not convert an

analog i nput. Analog leve ls on any pin that is defined as

a dig ital inp ut (inc luding t he ANx p ins) ma y cause the

input buffer to consume current that exceeds the

device specifications.

7.2.1 I/O PORT WRITE/READ TIMING

One instruction cycle is required between a port

direction change or port write operation and a read

operation of the same port. Typically, this instruction

would be a NOP.

EXAMP LE 7- 1: PORT WRITE/R EAD

EXAMPLE

WR LAT +

TRIS Latch

I/O Pad

WR Port

Data Bus

Data Latch

Read LAT

Read Port

Read TRIS

WR TRIS

Peripheral Output Data Output Enable

Peripheral Input Data

I/O Cell

Peripheral Module

Peripheral Output Enable

PIO Module

Output Multiplexers

Output Data

Input Data

Peripheral Module Enable

MOV 0xFF00, W0 ; Configure PORTB<15:8>

; as inputs

MOV W0, TRISB ; and PORTB<7:0> as outputs

NOP ; additional instruction

cylcle

btss PORTB, #11 ; bit test RB11 and skip if

set

dsPIC30F3014/4013

TABLE 7-1: dsPIC30F3014/4013 PORT REGISTER MAP

SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

TRISA 02C0 ————TRISA11 — ——————————0000 1000 0000 0000

PORTA 02C2 ————RA11 — ——————————0000 0000 0000 0000

LATA 02C4 ————LATA11 — ——————————0000 0000 0000 0000

TRISB 02C6 ———TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 0001 1111 1111 1111

PORTB 02C8 ———RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 0000 0000 0000 0000

LATB 02CB ———LATB12 LATB11 LATB10 LATB9 LATB8 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 0000 0000 0000 0000

TRISC 02CC TRISC15 TRISC14 TRISC13 — — — ——————————1110 0000 0000 0000

PORTC 02CE RC15 RC14 RC13 — — — ——————————0000 0000 0000 0000

LATC 02D0 LATC15 LATC14 LATC13 — — — ——————————0000 0000 0000 0000

TRISD 02D2 —————— TRISD9 TRISD8 ———— TRISD3 TRISD2 TRISD1 TRISD0 0000 0011 0000 1111

PORTD 02D4 —————— RD9 RD8 ———— RD3 RD2 RD1 RD0 0000 0000 0000 0000

LATD 02D6 ——————LATD9LATD8————LATD3LATD2LATD1LATD00000 0000 0000 0000

TRISF 02DE — — — — — — — — — TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 0000 0000 0111 1111

PORTF 02E0 — — — — — — — — — RF6RF5RF4RF3RF2RF1RF00000 0000 0000 0000

LATF 02E2 — — — — — — — — — LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 LATF0 0000 0000 0000 0000

Legend: u = uninitialized bit

3: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

dsPIC30F3014/4013

7.3 I nput Change Notification Module

The input change notification module provides the

dsPIC30F devices the ability to generate interrupt

requests to the processor, in response to a change of

state on selected input pins. This module is capable of

detecting input change of states even in Sleep mode,

when the cl ocks are disabled. The re are up to 24 exter-

nal signals (CN0 through CN23) that may be selected

(enabled) for generating an interrupt request on a

change of state.

TABLE 7-2: INPUT CHANGE NOTIFICATION REGISTER MAP FOR dsPIC30F3014 (BITS 15-8)

TABLE 7-3: INPUT CHANGE NOTIFICATION REGISTER MAP FOR dsPIC30F3014 (BITS 7-0)

TABLE 7-4: INPUT CHANGE NOTIFICATION REGISTER MAP FOR dsPIC30F4013 (BITS 15-8)

TABLE 7-5: INPUT CHANGE NOTIFICATION REGISTER MAP FOR dsPIC30F4013 (BITS 7-0)

SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Reset State

CNEN1 00C0 CN15IE CN14IE CN13IE CN12IE CN11IE CN10IE CN9IE CN8IE 0000 0000 0000 0000

CNEN2 00C2 — — — — — — — — 0000 0000 0000 0000

CNPU1 00C4 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CN8PUE 0000 0000 0000 0000

CNPU2 00C6 — — — — — — — — 0000 0000 0000 0000

Legend: u = uninitialized bit

1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

SFR

Name Addr. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

CNEN1 00C0 CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000 0000 0000 0000

CNEN2 00C2 ————— CN18IE CN17IE CN16IE 0000 0000 0000 0000

CNPU1 00C4 CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000 0000 0000 0000

CNPU2 00C6 ————— CN18PUE CN17PUE CN16PUE 0000 0000 0000 0000

Legend: u = uninitialized bit

1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

SFR

Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Reset St ate

CNEN1 00C0 CN15IE CN14IE CN13IE CN12IE CN11IE CN10IE CN9IE CN8IE 0000 0000 0000 0000

CNEN2 00C2 — — — — — — — — 0000 0000 0000 0000

CNPU1 00C4 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CN8PUE 0000 0000 0000 0000

CNPU2 00C6 — — — — — — — — 0000 0000 0000 0000

Legend: u = uninitialized bit

1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

SFR

Name Addr. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

CNEN1 00C0 CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000 0000 0000 0000

CNEN2 00C2 CN23IE CN22IE CN21IE CN20IE CN19IE CN18IE CN17IE CN16IE 0000 0000 0000 0000

CNPU1 00C4 CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000 0000 0000 0000

CNPU2 00C6 CN23PUE CN22PUE CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE CN16PUE 0000 0000 0000 0000

Legend: u = uninitialized bit

1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

dsPIC30F3014/4013

8.0 INTERRUPTS

The dsPIC30F sensor and general purpose families

have up to 41 interrup t sources an d 4 processo r excep-

tions (traps) which must be arbitrated based on a

priority scheme.

The CPU i s respons ible for rea ding the I nterrupt Vector

Table (IVT) and transferring the address contained in

the interrupt vector to the program counter. The inter-

rupt vector is transferred from the program data bus

into the program counter via a 24-bit wide multiplexer

on the input of the program counter.

The Inte rrupt Vector Table (IVT ) and A lternate Interru pt

Vector Table (AIVT) are placed near the beginning of

program memory (0x000004). The IVT and AIVT are

shown in Figure 8-1.

The interrupt controller is responsible for pre-

processing the interrupts and processor exceptions

prior to them being presented to the processor core.

The peripheral interrupts and traps are enabled,

prioritized and controlled using centralized Special

Function Registers:

• IFS0<15:0>, IFS1<15:0>, IFS2<15:0>

All interrupt request flags are maintained in these

three registers. The flags are set by their respec-

tive peripherals or external signals and they are

cleared via software.

• IEC0<15:0>, IEC1<15:0>, IEC2<15:0>

All interrupt enable control bits are maintained in

these three registers. These control bits are used

to individually enable interrupts from the

peripherals or external signals.

• IPC0<15:0>... IPC10<7:0>

The user assignable priority level associated with

each of these 41 interrupts is held centrally in

these eleven registers.

• IPL<3:0>

The current CPU priority level is explicitly stored

in the IPL bi ts. IPL<3> i s p res en t in the C ORCO N

STATUS register (SR) in the processor core.

• INTCON1< 15:0>, INTCON2<15 :0>

Global interrupt control functions are deriv ed from

these two registers. INTCON1 contains the con-

trol and status flags for the processor exceptions.

The INTCON2 register controls the external

interrupt request signal behavior and the use of

the alternate vector table.

All interrupt sources can be user assigned to one of 7

priori ty levels, 1 thro ugh 7, via the IPCx registers . Each

interrupt source is associated with an interrupt vector,

as shown in Table 8-1. Levels 7 and 1 represent the

highest and lowest maskable priorities, respectively.

If the NSTDIS bit (INTCON1<15>) is set, nesting of

interrupts is prev en ted . Th us, i f an interrupt is c urrentl y

being serviced, processing of a new interrupt is pre-

vented even if the new interrupt is of higher priorit y than

the one currently being serviced.

Certain interrupts have specialized control bits for

features like edge or level triggered interrupts, inter-

rupt-on-change, etc. Control of these features remains

within the peripheral module which generates the

interrupt.

The DISI instruction can be used to disable the

processing of interrupts of priorities 6 and lower for a

certain number of instructions, during which the DISI bit

(INTCON2<14>) remains set.

When an interrupt is serviced, the PC is loaded with the

address stor ed in the vector locati on in program mem-

ory that cor res ponds to the interru pt. There are 63 dif-

ferent vectors within the IVT (refer to Table 8-1) These

vectors are contained in locations 0x000004 through

0x0000FE of program memory (refer to Table 8-1).

These locations contain 24-bit addresses. In order to

prese rve robustn ess, an add ress error trap take s plac e

should the PC a ttem pt to f etc h a ny of the se words dur-

ing normal execution. This prevents execution of ran-

dom dat a as a result of accident ally decremen ting a PC

into vector space, accidentally mapping a data space

address into vector space, or the PC rolling over to

0x000000 after reaching the end of implemented pro-

gram memory space. Execution of a GOTO instruction

to this vector space also generates an address error

trap.

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046). For more information on the device

instruction set and programming, refer to the “dsPIC30F/

33F Programmer’s Reference Manual” (DS70157). Note: Interrupt flag bit s get set when an in terrupt

conditi on occ urs, regar dless o f the s tate of

its corresponding enable bit. User soft-

ware should ensure the appropriate inter-

rupt flag bits are clear prior to enabling an

interrupt.

Note: Assigning a priority level of ‘0’ to an inter-

rupt source is equivalent to disabling that

interrupt.

Note: The IPL bits become read-only whenever

the NSTDIS bit has been set to ‘1’.

dsPIC30F3014/4013

8.1 Interrupt Priority

The user assignable interrupt priority (IP<2:0>) bits for

each individual interrupt source are located in the LS

3 bits of eac h nibble withi n the IPCx registe r(s) . Bit 3 of

each nibble is not used and is read as a ‘0’. These bits

define the priority level assigned to a particular interrupt

by the user.

Natural Order Priority is determined by the position of

an interrupt in the vector table, and only affects

interrupt operation when multiple interrupts with the

same user-assigned priority become pending at the

same time.

Table 8-1 and Table 8-2 list the interrupt numbers,

corresponding interrupt sources and associated vector

numbers for the dsPIC30F3014 and dsPIC30F4013

devices, respectively.

The ability for the user to assign every interrupt to one

of seven pri ority levels means that the user can as sig n

a very high overall priority level to an interrupt with a

low natural order priority. For example, the PLVD (Low-

Voltage Detect) can be given a priority of 7. The INT0

(External Interrupt 0) may be assigned to priority level

1, thus giving it a very low effective priority.

TABLE 8-1: dsPIC30F3014 INTERRUPT

VECTOR TABLE

Note: The user selectable priority levels start at

0 as the lo west pri ority an d level 7 as the

highest priority.

Note 1: The natural order priority scheme has 0

as the highest priority and 53 as the

lowest priority.

2: The natural order priority number is the

same as the INT number.

INT

Number Vector

Number Interrupt Source

Highest Natural Order Priority

0 8 INT0 – External Interrupt 0

1 9 IC1 – I nput Capture 1

2 10 OC1 – Output C om par e 1

3 11 T1 – Timer 1

4 12 IC2 – Inp ut Ca pt ur e 2

5 13 OC2 – Output C om par e 2

6 14 T2 – Timer 2

7 15 T3 – Timer 3

816SPI1

9 17 U1RX – UART1 Receiver

10 18 U1T X – U ART1 Transmitter

11 19 ADC – ADC Convert Done

12 20 NVM – NVM Write Complete

13 21 SI2C – I2C™ Sla ve Interrupt

14 22 MI2C – I2C Mas t er Inter r upt

15 23 Input Change Interrupt

16 24 INT1 – External Interrupt 1

17-22 25-30 Reserved

23 31 INT2 – External Interrupt 2

24 32 U2RX – UART2 Receiver

25 33 U2TX – UART2 Transmitter

26 34 Reserved

27 35 C1 – Combined IRQ for CAN1

28-41 36-49 Reserved

42 50 LVD – Low-Voltage Detec t

43-53 51-61 Reserved

Lowest Natural Order Priority

dsPIC30F3014/4013

TABLE 8-2: dsPIC30F4013 INTERRUPT

VECTOR TABLE 8.2 Reset Sequence

A Reset is not a true exception because the interrupt

controll er is not involv ed in the Reset proce ss. The pro-

cessor initializes its registers in response to a Reset

which forces the PC to zero. The processor then begins

program execution at location 0x000000. A GOTO

instruction is stored in the first program memory loca-

tion immediately followed by the address target for the

GOTO instruction. The processor executes the GOTO to

the speci fie d address and then be gin s op erat ion at the

specified target (start) address.

8.2.1 RESET SOURCES

In addition to external Reset and Power-on Reset

(POR), these sources of error conditions ‘trap’ to the

Reset vector:

• Watchdog Time-out:

The watchdog has timed out, indicating that the

proce ssor is no lon ger exe cu ting the correct flow

of code.

• Uninitialized W Register Trap:

An attempt to use an uninitialized W register as

an Address Pointer causes a Reset.

• Illegal Ins truc t io n Trap:

Attempted execution of any unused opcodes

results in an illegal instruction trap. Note that a

fetch of an illegal instruction does not result in an

illegal instruction trap if that instruction is flushed

prior to execution due to a flow change.

• Brown-out Reset (BOR):

A momentary dip in the power supply to the

device has been detected which may result in

malfunction.

• Trap Lockout:

Occurrence of multiple trap conditions

simultaneously causes a Reset.

INT

Number Vector

Number Interrupt Source

Highest Natural Order Priority

0 8 INT0 – External Interrupt 0

1 9 IC1 – Input Capt ur e 1

2 10 OC1 – Out put C om par e 1

3 11 T1 – Timer 1

4 12 IC2 – Input Ca pt ur e 2

5 13 OC2 – Out put C om par e 2

6 14 T2 V Timer 2

7 15 T3 – Timer 3

816SPI1

9 17 U1RX – UART1 Receiver

10 18 U1TX – UART1 Transmitter

11 19 ADC – ADC Convert Done

12 20 NVM – NVM Write Complete

13 21 SI2C – I2C™ Slave Interrupt

14 22 MI2C – I2C Master Interrupt

15 23 Input Change Interr upt

16 24 INT1 – External Interrupt 1

17 25 IC7 – Input Capt ur e 7

18 26 IC8 – Input Capt ur e 8

19 27 OC3 – Output Compare 3

20 28 OC4 – Output Compare 4

21 29 T4 – Timer 4

22 30 T5 – Timer 5

23 31 INT2 – External Interrupt 2

24 32 U2RX – UART2 Receiver

25 33 U2TX – UART2 Transmitter

26 34 Reserved

27 35 C1 – Combined IRQ for CAN1

28-40 36-48 Reserved

41 49 DCI – CODEC Transfer Done

42 50 LVD – Low-Voltage Dete ct

43-53 51-61 Reserved

Lowest Natural Order Priority

dsPIC30F3014/4013

8.3 Traps

Traps can be considered as non-maskable interrupts

indicating a software or hardware error, which adhere

to a predefined priority as shown in Figure 8-1. They

are intended to provide the user a means to correct

erroneous o pera t io n d uri ng deb ug and when operating

within the application.

Note that many of these trap conditions can only be

detecte d when th ey occur. Conseque ntly, the questio n-

able instruction is allowed to complete prior to trap

exception processing. If the user chooses to recover

from the error, the result of the erroneous action that

caused the trap may have to be corrected.

There are 8 fixed priority levels for traps: Level 8

through L evel 15, whi ch mea ns that the IPL3 i s alw ay s

set during processing of a trap.

If the us er is not cu rrently exec uting a trap, a nd he s et s

the I PL<3:0> bit s t o a va lue o f ‘0111’ (Lev el 7), then all

inter rupts ar e disabled , but trap s can stil l be proces sed.

8.3.1 TRAP SOURCES

The following traps are provided with increasing prior-

ity. However, since all traps can be nested, priority has

little effect.

Math Error Trap:

The math error trap executes under these circum-

stances:

1. Should an attempt be made to divide by zero,

the divide operation aborts on a cycle boundary

and the trap is taken.

2. If enabled, a math error trap is taken when an

arithmetic operation on either accumulator A or

B causes an overflow from bit 31 and the accu-

mulator guard bits are not utilized.

3. If enabled, a math error trap is taken when an

arithmetic operation on either accumulator A or

B causes a catastrophic overflow from bit 39 and

all saturation is disabled.

4. If the shift amount specified in a shift instruction

is greater than the maximum allowed shift

amount, a trap occurs.

Addres s Er r or Trap:

This trap is initiated when any of the following

circumstances occurs:

1. A misaligned data word access is attempted.

2. A data fetch from our unimplemented data

memory location is attempted.

3. A data access of an unimplemented program

memory location is attempted.

4. An instruction fetch from vector space is

attempted.

5. Execution of a “BRA #literal” instruction or a

“GOTO #literal” instruc ti on, w he re literal

is an un implem ented progra m memo ry address .

6. Executing instructions after modifying the PC to

point to unimplemented program memory

addresses. The PC may be modified by loading

a value into the stack and executing a RETURN

instruction.

Stack Error Trap:

This trap is initiated under the following conditions:

1. The Stack Pointer is loaded with a value which

is greater than the (user programmable) limit

value written into the SPLIM register (stack

overflow).

2. The Stack Pointer is loaded with a value which

is less than 0x0800 (simple stack underflow).

Oscillator Fail Trap:

This trap is initiated if the external oscillator fails and

operation becomes reliant on an internal RC backup.

8.3.2 HARD AND SOFT TRAPS

It is possible that multiple traps can become active

within the same cycle (e.g., a misaligned word stack

write to an overflowed address). In such a case, the

fixed priority shown in Figure 8-2 is implemented,

whic h may requir e the user t o check if oth er traps are

pending, in order to completely correct the Fault.

‘Soft’ traps incl ude exceptions of priority lev el 8 through

level 11, inclusive. The arithmetic error trap (level 11)

falls into this category of traps.

‘Hard’ traps include exceptions of priority level 12

through level 15, inclusive. The address error (level

12), stack error (level 13) and oscillator error (level 14)

traps fall into this category.

Note: If the user does not intend to take correc-

tive action in the event of a trap error

condition, these vectors must be loaded

with the address of a default handler that

simply contains the RESET instruction. If,

on the other hand, one of the vectors

containing an invalid address is called, an

address error trap is generated.

Note: In the MAC class of instructions, wherein

the data space is split into X and Y data

space, unimplemented X space includes

all of Y space, and unimplemented Y

space includes all of X space.

dsPIC30F3014/4013

Each hard trap that occurs must be acknowledged

before code execution of any type may continue. If a

lower priority hard trap occurs while a higher priority

trap is pending, acknowledged, or is being processed,

a hard trap conflict occurs.

The devic e is automatic ally Reset in a ha rd trap conflict

condition. The TRAPR Status bit (RCON<15>) is set

when the Reset occurs so that the condition may be

detected in software.

FIGURE 8-1: TRAP VECTORS

8.4 Interrupt Sequence

All inte rrupt event flags are sampled in the be ginning of

each instruction cycle by the IFSx registers. A pending

Interrupt Request (IRQ) is indicated by the flag bit

being equ al to a ‘1’ in an IFSx reg ister . The IRQ cau ses

an interrupt to occur if the corresponding bit in the Inter-

rupt Enable (IEC x) register is set. For the rema ind er of

the i nstruc tion cy cle, the priori ties of a ll pend ing in ter-

rupt requests are evaluated.

If there is a pending IRQ with a priority level greater

than the current processor priority level in the IPL bits,

the processor is interrupted.

The pr ocessor then st acks the curren t program counter

and the low byte of the processor STATUS register

(SRL), as shown in Figure 8-2. The low byte of the

ST ATUS register cont ains the processor pri ority level at

the time prior to the beginning of the interrupt cycle.

The pr ocessor the n loads t he priority level fo r this int er-

rupt into the STATUS register. This action disables all

lower priority interrupts until the completion of the

Interrupt Service Routine.

FIGURE 8-2: INTERRUPT STACK FRAME

The RETFIE (return from interrupt) instruction unstacks

the program counter and STATUS registers to return

the processor to its state prior to the interrupt

sequence.

8.5 Al ternate Vect or Table

In program memory, the Interrupt Vector Table (IVT) is

follow ed by the Altern ate Interr upt Vector Table (AIVT),

as shown in Figure 8-1. Access to the alternate vector

table is provided by the ALTIVT bit in the INTCON2 reg-

ister. If the ALTIVT bit is set, all interru pt a nd ex cep tio n

processes use the alternate vectors instead of the

defa ul t vec to r s. T h e alt er na t e v e ctor s a re or g ani ze d in

the same manner as the de fault vectors. The AIVT sup-

ports emulation and debugging efforts by providing a

means to sw i tch betw e en an ap pli ca t io n and a su ppo rt

environment without requiring the interrupt vectors to

be reprogram m ed. Th is featu re als o ena bl es s w itchin g

between applications for evaluation of different

software algorithms at run time.

If the AIVT is not required, the program memory

allocated to the AIVT may be used for other purposes.

AIVT is not a protected section and may be freely

programmed by the user.

Address Error Trap Vector

Oscillator Fail Trap Vector

Stack Error Trap Vector

Reserved Vector

Math Error Trap Vector

Reserved

Oscillator Fail Trap Vector

Address Error Trap Vector

Reserved Vector

Reserv ed Vector

Interrupt 0 Vector

Interrupt 1 Vector

—

Interrupt 52 Vector

Interrupt 53 Vector

Math Error Trap Vector

Decreasing

Priority

0x000000

0x000014

Reserved

Stack Error Trap Vector

Reserved Vector

Interrupt 1 Vector

—

Interrupt 52 Vector

Interrupt 53 Vector

IVT

AIVT

0x000080

0x00007E

0x0000FE

Reserved

0x000094

Reset - GOTO Instruction

Reset - GOTO Address 0x000002

Reserved 0x000082

0x000084

0x000004

Reserved Vector

Interru pt 0 Vector

—

Note 1: The user can always lower the priority

level by writing a new value into SR. The

Interrupt Service Routine must clear the

interrupt flag bits in the IFSx register

before lowering the processor interrupt

priority, in order to avoid recursive

interrupts.

2: The IPL3 bit (CORCON<3>) is always

clear when interrupts are being pro-

cessed. It is set only during execution of

traps.

015

W15 (before CALL)

W15 (after CALL)

Stack Grows Towards

Higher Address

0x0000

PC<15:0>

SRL IPL3 PC<22:16>

POP : [--W15]

PUSH: [W15++]

dsPIC30F3014/4013

8.6 Fast Context Saving

A context saving option is available using shadow reg-

isters. Shadow registers are provided for the DC, N,

OV, Z and C bits in SR, and the registers W0 through

W3. The s hadows are only o ne level deep. Th e shadow

registers are accessible using the PUSH.S and POP.S

instruc tions only.

When the processor vectors to an interrupt, the

PUSH.S instruction can be used to store the current

value of the aforementioned registers into their

respective shadow registers.

If an ISR of a certain priority uses the PUSH.S and

POP.S instructions for fast context saving, then a

higher priority IS R shou ld no t inc lude the s ame instru c-

tions. Users must save the key registers in software

during a lo wer priori ty interru pt if the h igher priorit y ISR

uses fast context saving.

8.7 External Interrupt Requests

The interrupt controller supports up to five external

interrupt request signals, INT0-INT4. These inputs are

edge sensitive; they require a low-to-high or a high-to-

low transition to generate an interrupt request. The

INTCON2 re gister has thre e bits , INT0EP-INT2EP, that

select the polarity of the edge detection circuitry.

8.8 Wake-up from Sleep and Idle

The interrupt controller may be used to wake-up the

processor from either Sleep or Idle modes, if Sleep or

Idle mode is active when the interrupt is generated.

If an enabled interrupt request of sufficient priority is

received by the interrupt controller, then the standard

interrupt request is presented to the processor. At the

same time, the processor wakes up from Sleep or Idle

and begins execution of the Interrupt Service Routine

(ISR) needed to process the int errup t reque st.

dsPIC30F3014/4013

TABLE 8-3: dsPIC30F3014 INTERRUPT CONTROLLER REGISTER MAP

SFR

Name ADR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

INTCON1 0080 NSTDIS ———— OVATE OVBTE COVTE — — — MATHERR ADDRERR STKERR OSCFAIL —0000 0000 0000 0000

INTCON2 0082 ALTIVT DISI — — — — — — — — — — — INT2EP INT1EP INT0EP 0000 0000 0000 0000

IFS0 0084 CNIF MI2CIF SI2CIF NVMIF ADIF U1TXIF U1RXIF SPI1IF T3IF T2IF OC2IF IC2IF T1IF OC1IF IC1IF INT0IF 0000 0000 0000 0000

IFS1 0086 ————C1IF— U2TXIF U2RXIF INT2IF — — — — — —INT1IF

0000 0000 0000 0000

IFS2 0088 — — — — —LVDIF— — — — — — — — — — 0000 0000 0000 0000

IEC0 008C CNIE MI2CIE SI2CIE NVMIE ADIE U1TXIE U1RXIE SPI1IE T3IE T2IE OC2IE IC2IE T1IE OC1IE IC1IE INT0IE 0000 0000 0000 0000

IEC1 008E ————C1IE— U2TXIE U2RXIE INT2IE — — — — — —INT1IE

0000 0000 0000 0000

IEC2 0090 — — — — —LVDIE— — — — — — — — — — 0000 0000 0000 0000

IPC0 0094 — T1IP<2:0> —OC1IP<2:0>— IC1IP<2:0> — INT0IP<2:0> 0100 0100 0100 0100

IPC1 0096 — T31P<2:0> — T2IP<2:0> — OC2IP<2:0> — IC2IP<2:0> 0100 0100 0100 0100

IPC2 0098 —ADIP<2:0>— U1TXIP<2:0> — U1RXIP<2:0> — SPI1IP<2:0> 0100 0100 0100 0100

IPC3 009A — CNIP<2:0> —MI2CIP<2:0>— SI2CIP<2:0> — NVMIP<2:0> 0100 0100 0100 0100

IPC4 009C — — — — — — — — — — — — — INT1IP<2:0> 0100 0100 0100 0100

IPC5 009E — INT2IP<2:0> — — — — — — — — — — — — 0100 0100 0100 0100

IPC6 00A0 — C1IP<2:0> — — — — — U2TXIP<2:0> — U2RXIP<2:0> 0100 0100 0100 0100

IPC7 00A2 — — — — — — — — — — — — — — — — 0100 0100 0100 0100

IPC8 00A4 — — — — — — — — — — — — — — — — 0100 0100 0100 0100

IPC9 00A6 — — — — — — — — — — — — — — — — 0000 0100 0100 0100

IPC10 00A8 — — — — — LVDIP<2:0> — DCIIP<2:0> — — — — 0000 0100 0100 0000

Legend: u = uninitialized bit

2: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

dsPIC30F3014/4013

TABLE 8-4: dsPIC30F4013 INTERRUPT CONTROLLER REGISTER MAP

SFR

Name ADR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

INTCON1 0080 NSTDIS ———— OVATE OVBTE COVTE — — — MATHERR ADDRERR STKERR OSCFAIL —0000 0000 0000 0000

INTCON2 0082 ALTIVT DISI — — — — — — — — — — — INT2EP INT1EP INT0EP 0000 0000 0000 0000

IFS0 0084 CNIF MI2CIF SI2CIF NVMIF ADIF U1TXIF U1RXIF SPI1IF T3IF T2IF OC2IF IC2IF T1IF OC1IF IC1IF INT0IF 0000 0000 0000 0000

IFS1 0086 ————C1IF— U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF IC8IF IC7IF INT1IF 0000 0000 0000 0000

IFS2 0088 — — — — — LVDIF DCIIF — — — — — — — — — 0000 0000 0000 0000

IEC0 008C CNIE MI2CIE SI2CIE NVMIE ADIE U1TXIE U1RXIE SPI1IE T3IE T2IE OC2IE IC2IE T1IE OC1IE IC1IE INT0IE 0000 0000 0000 0000

IEC1 008E ————C1IE— U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE IC8IE IC7IE INT1IE 0000 0000 0000 0000

IEC2 0090 — — — — — LVDIE DCIIE — — — — — — — — — 0000 0000 0000 0000

IPC0 0094 — T1IP<2:0> —OC1IP<2:0>— IC1IP<2:0> — INT0IP<2:0> 0100 0100 0100 0100

IPC1 0096 — T31P<2:0> — T2IP<2:0> — OC2IP<2:0> — IC2IP<2:0> 0100 0100 0100 0100

IPC2 0098 —ADIP<2:0>— U1TXIP<2:0> — U1RXIP<2:0> — SPI1IP<2:0> 0100 0100 0100 0100

IPC3 009A — CNIP<2:0> —MI2CIP<2:0>— SI2CIP<2:0> — NVMIP<2:0> 0100 0100 0100 0100

IPC4 009C —OC3IP<2:0>—IC8IP<2:0>— IC7IP<2:0> — INT1IP<2:0> 0100 0100 0100 0100

IPC5 009E — INT2IP<2:0> — T5IP<2:0> — T4IP<2:0> — OC4IP<2:0> 0100 0100 0100 0100

IPC6 00A0 — C1IP<2:0> — SPI2IP<2:0> — U2TXIP<2:0> — U2RXIP<2:0> 0100 0100 0100 0100

IPC7 00A2 — — — — — — — — — — — — — — — — 0100 0100 0100 0100

IPC8 00A4 — — — — — — — — — — — — — — — — 0100 0100 0100 0100

IPC9 00A6 — — — — — — — — — — — — — — — — 0000 0100 0100 0100

IPC10 00A8 — — — — — LVDIP<2:0> — DCIIP<2:0> — — — — 0000 0100 0100 0000

Legend: u = uninitialized bit

1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

dsPIC30F3014/4013

9.0 TIMER1 MODULE

This section describes the 16-bit general purpose

Timer1 module and associated operational modes.

Figure 9-1 depicts the simplified block diagram of the

16-bit Ti mer1 module.

The following sections provide a detailed description

including setup and control registers, along with

associated block diagrams for the operatio nal modes of

the timers.

The T imer1 mo dule is a 16-bit timer which can serv e as

the time count er for the rea l-time clo ck, o r operate as a

free-running interval timer/counter. The 16-bit timer

has the followi ng mo des :

• 16-bit Timer

• 16-bit Synchronous Counter

• 16-bit Asynchronous Counter

Further, the following operational characteristics are

supported:

• Timer gate operation

• Selectable prescaler set tings

• Timer operation during CPU Idle and Sleep

modes

• Interrupt on 16-bit Period register match or falling

edge of external gate signal

These operating modes are determined by setting the

appropriate bit(s) in the 16-bit SFR, T1CON. Figure 9-1

present s a block diagram o f the 16-bit timer modul e.

16-bit T imer Mode: In t he 16-bi t T imer m ode, the timer

increments on every instruction cycle up to a match

value preloaded into the Period register PR1, then

resets to ‘0’ and continues to count.

When the CPU go es into t he Idle m ode, the ti mer stop s

incrementing unless the TSIDL (T1CON<13>) bit = 0.

If TSIDL = 1, the timer m odule logic resu mes th e inc re-

menting sequence upon termination of the CPU Idle

mode.

16-bit Synchronous Counter Mode: In the 16-bit

Synchronous Counter mode, the timer increments on

the rising edge of the applied external clock signal

which is synchronized with the internal phase clocks.

The timer counts up to a match value preloaded in

PR1, then resets to ‘0’ and continues.

When the CPU go es into t he Idle m ode, the ti mer stop s

incrementing unless the respective TSIDL bit = 0. If

TSIDL = 1, the timer module logic resumes the incre-

menting sequence upon termination of the CPU Idle

mode.

16-bit Asynchronous Counter Mode: In the 16-bit

Asynchronous Counter mode, the timer increments on

every rising edge of the applied external clock signal.

The timer counts up to a match value preloaded in

PR1, then resets to ‘0’ and continues.

When the timer is configured for the Asynchronous

mode of operation and the CPU goes into the Idle

mode, the timer stops incrementing if TSIDL = 1.

FIGURE 9-1: 16-BIT TIMER1 MODULE BLOCK DIAGRAM

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046).

TON

Sync

SOSCI

SOSCO/

PR1

T1IF

Equal Comparator x 16

TMR1

Reset

LPOSCEN

Event Flag

TSYNC

TGATE

TCKPS<1:0>

Prescaler

1, 8, 64, 256

TGATE

TCY

T1CK

TCS

1 x

0 1

TGATE

0 0

Gate

Sync

dsPIC30F3014/4013

9.1 Timer Gate Operation

The 16-bi t timer can be pl aced in the Ga ted Ti me Accu-

mulation mode. This mode allows the internal TCY to

increm ent the respec tive timer when the gate input si g-

nal (T1CK pin) is asserted high. Control bit, TGATE

(T1CON<6>), must be set to enable this mode. The

timer must be enabled (TON = 1) and the timer clock

source se t to interna l (TCS = 0).

When the CPU go es into t he Idle m ode, the ti mer stop s

increm enti ng unless TSID L = 0. If TSIDL = 1, the timer

resumes the incrementing sequence upon termination

of the CPU Idle mode.

9.2 Timer Prescaler

The input clock (FOSC/4 or external clock) to the 16-bit

T imer has a pre scale optio n of 1:1, 1:8, 1:64 a nd 1:256,

selected by control bits, TCKPS<1:0> (T1CON<5:4>).

The prescaler counter is cleared when any of the

following occurs:

• a write to the TMR1 register

• a write to the T1CON register

• device Reset, su ch as POR and BOR

However, if the timer is disabled (TON = 0), then the

timer prescaler cannot be reset since the prescaler

clock is halted.

TMR1 is not cleared when T1CON is written. It is

cleared by writin g to the TMR1 register.

9.3 Timer Operation During Sleep

Mode

During CPU Sleep mode, the timer operates if:

• The timer module is enabled (TON = 1) and

• The timer clock source is selected as external

(TCS = 1) and

• The TSYNC bit (T1CO N<2>) is asserted to a log ic

‘0’ which defines the exter nal clock source as

asynchronous.

When all three conditions are true, the timer continues

to count up to the Period register and is reset to

0x0000.

When a match between the timer and the Period

respective timer interrupt enable bit is asserted.

9.4 Timer Interrupt

The 16-bit timer has the ability to generate an interrupt-

on-period match. When the timer count matches the

Peri od regis ter, the T1I F bit is asse rted an d an inte rrupt

is gene rat ed , if enabled. The T1IF bit must be cleared in

software. The timer interrupt flag, T1IF, is located in the

IFS0 Control register in the interrupt controller.

When the Gated Time Accumulation mode is enabled,

an interrupt is al so ge nerated on the falling edg e o f the

gate signal (at the end of the accumulation cycle).

Enabling an interrupt is accomplished via the respec-

tive timer interrupt enable bit, T1IE. The timer interrupt

enable bit is located in the IEC0 Control register in the

interrupt controller.

9.5 Real-Time Clock

Timer1, when operating in Real-Time Clock (RTC)

mode, provides time of day and event time-stamping

capabilities. Key operation al features of the RTC are:

• Operation from 32 kHz LP oscillator

• 8-bit presc ale r

•Low power

• Real-Time Clock interrupts

These operating modes are determined by setting the

appropriate bit(s) in the T1CON Control register.

FIGURE 9-2: RECOMMENDED

COMPONENTS FOR

TI MER1 LP OSCILLATOR

RTC

SOSCI

SOSCO

dsPIC30FXXXX

32.768 kHz

XTAL

C1 = C2 = 18 pF; R = 100K

dsPIC30F3014/4013

9.5.1 RTC OSCILLATOR OPERATION

When the T ON = 1, T CS = 1 and TGATE = 0, the timer

increm ents on th e ris in g e dge of the 32 kHz LP oscill a-

tor output si gnal, up to the val ue specified in the Period

The TSYNC bit must be asserted to a logic ‘0’

(Asynchronous mode) for correct operation.

Enabling LPOSCEN (OSCCON<1>) disables the nor-

mal Timer and Counter modes and enable a timer

carry-out wake-up event.

When the CPU ente rs Sleep mod e, the RTC co nti nues

to opera te, provid ed the 32 kHz e xternal c rystal oscill a-

tor is active and the control bits have not been

changed. The TSIDL bit should be cleared to ‘0’ in

order for RTC to continue operation in Idle mode.

9.5.2 RTC INTERRUPTS

When an interrupt event oc curs, the respectiv e interrupt

flag, T1IF, is asserted and an interrupt is generated, if

enabled. The T1IF bit must be cleared in software. The

respective Timer interrupt flag, T1IF, is located in the

IFS0 STATUS register in the interrupt controller.

Enabling an interrupt is accomplished via the respec-

tive timer interrupt enable bit, T1IE. The timer interrupt

enable bit is located in the IEC0 Control register in the

interrupt con trol le r.

dsPIC30F3014/4013

TABLE 9-1: dsPIC30F3014/4013 TIMER1 REGISTER MAP

SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

TMR1 0100 Timer1 Register uuuu uuuu uuuu uuuu

PR1 0102 Period Regis ter 1 1111 1111 1111 1111

T1CON 0104 TON —TSIDL— — — — — — TGATE TCKPS1 TCKPS0 —TSYNCTCS —0000 0000 0000 0000

Legend: u = uninitialized bit

2: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

dsPIC30F3014/4013

10.0 TIMER2/3 MODULE

This section describes the 32-bit general purpose

Timer module (Timer2/3) and associated operational

modes. Figure 10-1 depicts the simplified block dia-

gram of the 32-bit Timer2/3 module. Figure 10-2 and

Figure 10-3 show Timer2/3 configured as two

independent 16-bit timers, Timer2 and Timer3,

respectively.

The Timer2/3 module is a 32-bit timer (which can be

configured as two 16-bit timers) with selectable

operating modes. These timers are utilized by other

periphe ral modul es, such as:

• Input Capture

• Output Compare/Simpl e PWM

The following sections provide a detailed description,

including setup and control registers, along with

associated block diagrams for the operatio nal modes of

the timers.

The 32-bit timer has the following modes:

• Two independent 16-bit timers (Timer2 and

Tim er3) with all 16 -bit operating mode s (except

Asynchronous Counter mode)

• Single 32-bit timer operation

• Single 32-bit synchronous counter

Further, the following operational characteristics are

supported:

• AD C event trigger

• Timer gate operation

• Selectable prescaler set tings

• Timer operation during Idle and Sleep modes

• Interrupt on a 32-bit peri od register match

These operating modes are determined by setting the

appropriate bit(s) in the 16-bit T2CON and T3CON

SFRs.

For 32-bit timer/counter operation, Timer2 is the lsw

and T i me r3 is the msw of the 32-b it tim er.

16-bit Timer Mode: In the 16-bit mode, Timer2 and

Timer3 can be configured as two independent 16-bit

timers. Each timer can be set up in either 16-bit Timer

mode or 16-bit Synchronous Counter mode. See

Section 9.0 “Timer1 Module” for details on these two

operating modes.

The only functional difference between Timer2 and

Timer3 is that Timer2 provides synchronization of the

clock prescal er output. This is useful for high-frequency

external clock inputs.

32-bit T imer Mode: In t he 32-bi t T imer m ode, the timer

increments on every instruction cycle, up to a match

value preloaded into the combined 32-bit Period

count.

For synchronous 32-bit reads of the Timer2/Timer3

pair, reading the lsw (TMR2 register) causes the msw

to be read and latched into a 16-bit holding register,

termed TMR3HLD.

For synchronous 32-bit writes, the holding register

(TMR3HLD) must first be written to. When followed by

a write to the TMR2 re gister, the content s of TM R3HLD

is transferred and latched into the MSB of the 32-bit

timer (TMR3).

32-bit Synchronous Counter Mode: In the 32-bit

Synchronous Counter mode, the timer increments on

the rising edge of the applied external clock signal

which is synchronized with the internal phase clocks.

The timer counts up to a match value preloaded in the

combi ne d 32 -bi t per i od re gi st er, PR3/PR 2 , th en re se ts

to ‘0’ and continues.

When the timer is configured for the Synchronous

Counter mode of operation and the CPU goes into the

Idle mode, the timer stops incrementing unless the

TSIDL (T2CON<13>) bit = 0. If TSIDL = 1, the timer

module logic resumes the incrementing sequence

upon termination of the CPU Idle mode.

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046).

Note: For 32-bit timer operation, T3CON control

bits are ignored. Only T2CON control bits

are used for setup and control. Timer2

clock and gate inputs are utilized for the

32-bit timer module, but an interrupt is

generated with the Timer3 interrupt flag

(T3IF) and th e interrupt is en abled with the

Timer3 interrupt enable bit (T3IE).

dsPIC30F3014/4013

FIGURE 10-1: 32-BIT TIMER 2/3 BLOCK DIAGRAM

TMR3 TMR2

T3IF

Equal Comparator x 32

PR3 PR2

Reset

LSB MSB

Event Flag

Note: Timer Configuration bit T32 (T2CON<3>) must be set to ‘1’ for a 32-bit timer/counter operation. All control

bits are respective to the T2CON register.

Data Bus<15:0>

Read TMR2

Write TMR2 16

TGATE ( T2 CON<6>)

(T2CON<6>)

TGATE

TON TCKPS<1:0>

TCY

TCS

1 x

0 1

TGATE

0 0

Gate

T2CK

Sync

ADC Event Trigger

Sync

TMR3HLD

Prescaler

1, 8, 64, 256

dsPIC30F3014/4013

FIGURE 10-2: 16-BIT TIMER2 BLOCK DIAGRAM

FIGURE 10-3: 16-BIT TIMER3 BLOCK DIAGRAM

TON

Sync

PR2

T2IF

Equal Comparator x 16

TMR2

Reset

Event Flag TGATE

TCKPS<1:0>

TGATE

TCY

TCS

1 x

0 1

TGATE

0 0

Gate

T2CK

Sync Prescaler

1, 8, 64, 256

TON

PR3

T3IF

Equal Comparator x 16

TMR3

Reset

Event Flag TGATE

TCKPS<1:0>

TGATE

TCY

TCS

1 x

0 1

TGATE

0 0

T3CK

ADC Event Trigger

Sync

Prescaler

1, 8, 64, 256

Note: T3CK pin does not exist on dsPIC30F3014/4013 devices. The block diagram shown here illustrates the

schematic of Timer3 as implemented on the dsPIC30F6014 device.

dsPIC30F3014/4013

10.1 Timer Gate Operation

The 32-bi t timer can be pl aced in the Ga ted Ti me Accu-

mulation mode. This mode allows the internal TCY to

increment the respective timer when the gate input

signa l ( T 2C K pi n) i s as se rt ed hi g h. C o ntr o l b it, TG ATE

(T2CON<6>), must be set to enable this mode. When

in this mode, Timer2 is the originating clock source.

The TGATE setting is ignored for Timer3. The timer

must be e nab led (T O N = 1) and the time r cl oc k so urc e

set to internal (TCS = 0).

The falling edge of the external signal terminates the

count operation but does not reset the timer. The user

must reset the timer in order to start counting from zero.

10.2 ADC Event Trigger

When a matc h occurs betwe en the 32-bit timer (TM R3/

TMR2) and the 32-bit combined period register (PR3/

PR2), a special ADC trigger event signal is generated

by Timer3.

10.3 Timer Prescaler

The in put cloc k (FOSC/4 or external clock) to the timer

has a prescale option of 1:1, 1:8, 1:64, and 1:256,

selected by control bits, TCKPS<1:0> (T2CON<5:4>

and T3CON<5:4>). For the 32-bit timer operation, the

origina ting clock so urce is Timer2. Th e prescale r oper-

ation for Timer3 is not applicable in this mode. The

prescaler counter is cleared when any of the following

occurs:

• a write to the TMR2/TMR3 register

• a write to the T2CON/T3CON register

• device Reset, su ch as POR and BOR

However, if the timer is disabled (TON = 0), then the

Timer 2 prescaler cannot be reset since the prescaler

clock is halted.

TMR2/TMR3 is not cleared when T2CON/T3CON is

written.

10.4 Timer Operation During Sleep

Mode

During CPU Sleep mode, the timer does not operate

because the internal clocks are disabled.

10.5 Timer Interrupt

The 32-bit timer module can generate an interrupt-on-

period ma tch or on the fall ing edg e of the ext ernal ga te

signal. When the 32-bit timer count matches the

respective 32-bit period register, or the falling edge of

the external “gate” signal is detected, the T3IF bit

(IFS0<7>) is asserted and an interrupt is generated, if

enabled . In this mode, th e T3IF int errupt fl ag is used as

the source of the interrupt. The T3IF bit must be

cleared in software.

Enabling an interrupt is accomplished via the

respective timer interrupt enable bit, T3IE (IEC0<7>).

dsPIC30F3014/4013

TABLE 10-1: dsPIC30F3014/4013 TIMER2/3 REGISTER MAP

SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

TMR2 0106 Timer2 Register uuuu uuuu uuuu uuuu

TMR3HLD 0108 Timer3 Holding Register (for 32-bit timer operations only) uuuu uuuu uuuu uuuu

TMR3 010A Time r3 Register uuuu uuuu uuuu uuuu

PR2 010C Period Register 2 1111 1111 1111 1111

PR3 010E Period Register 3 1111 1111 1111 1111

T2CON 0110 TON —TSIDL— — — — — — TGATE TCKPS1 TCKPS0 T32 —TCS —0000 0000 0000 0000

T3CON 0112 TON —TSIDL— — — — — — TGATE TCKPS1 TCKPS0 ——TCS —0000 0000 0000 0000

Legend: u = uninitialized bit

3: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

dsPIC30F3014/4013

NOTES:

dsPIC30F3014/4013

11.0 TIMER4/5 MODULE

This section describes the second 32-bit general

purpose Timer module (Timer4/5) and associated

operational modes. Figure 11-1 depicts the simplified

block diagram of the 32-bit Timer4/5 module.

Figure 11-2 and Figure 11-3 show Time r4/5 co nfi gured

as two independent 16-bit timers, Timer4 and Timer5,

respectively.

The Timer4/5 module is similar in operation to the

Timer2/3 module. However, there are some

diffe rences which are listed:

• The T imer4/5 module does not support the ADC

event trigger feature

• Timer4/5 can not be utilized by other peripheral

modules, such as input capture and output compare

The oper ating modes of the T imer4/5 module are deter-

mined by setting the appropriate bit(s) in the 16-bit

T4CON and T5CON SFRs.

For 32-bit timer/counter operation, Timer4 is the lsw

and Timer5 is the msw of the 32-bit timer.

FIGURE 11-1: 32-BIT TIMER4/5 BLOCK DIAGRAM

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the dsPIC30F Family Reference

Manual (DS70046). Note: For 32-bit timer operation, T5CON control

bits are ignored. Only T4CON control bits

are used for setup and control. Timer4

clock and gate inputs are utilized for the

32-bit timer module but an interrupt is

generated with the Timer5 interrupt flag

(T5IF) and th e interrupt is en abled with the

Timer5 interrupt enable bit (T5IE).

TMR5 TMR4

T5IF

Equal Comparator x 32

PR5 PR4

Reset

LSB

MSB

Event Flag

Note: T imer Configuration bit T32 (T4CON<3>) must be set to ‘1’ for a 32-bit timer/counter operation. All control

bits are respective to the T4CON register.

Data Bu s< 15 :0 >

TMR5HLD

Read TMR4

Write TMR4 16

TGATE (T4CON<6>)

(T4CON<6>)

TGATE

TON TCKPS<1:0>

Prescaler

1, 8, 64 , 25 6

TCY

TCS

1 x

0 1

TGATE

0 0

Gate

T4CK

Sync

dsPIC30F3014/4013

FIGURE 11-2: 16-BIT TIMER4 BLOCK DIAGRAM

FIGURE 11-3: 16-BIT TIMER5 BLOCK DIAGRAM

TON

Sync

PR4

T4IF

Equal Comparator x 16

TMR4

Reset

Event Flag TGATE

TCKPS<1:0>

Prescaler

1, 8, 64, 256

TGATE

TCY

TCS

1 x

0 1

TGATE

0 0

Gate

T4CK

Sync

TON

PR5

T5IF

Equal Comparator x 16

TMR5

Reset

Event Flag TGATE

TCKPS<1:0>

Prescaler

1, 8, 64, 256

TGATE

TCY

TCS

1 x

0 1

TGATE

0 0

T5CK

ADC Event Trigger

Sync

Note: In the dsPIC30F3014 device, there is no T5CK pin. Therefore, in this device the following modes should

not be used for Timer5:

4: TCS = 1 (16-bit counter)

5: TCS = 0, TGATE = 1 (gated time accumulation)

dsPIC30F3014/4013

TABLE 11-1: dsPIC30F4013 TIMER4/5 REGISTER MAP

SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 1 1 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

TMR4 0114 T imer 4 Register uuuu uuuu uuuu uuuu

TMR5HLD 0116 Timer 5 Holding Register (for 32-bit operations only) uuuu uuuu uuuu uuuu

TMR5 0118 T imer 5 Register uuuu uuuu uuuu uuuu

PR4 011A Period Register 4 1111 1111 1111 1111

PR5 011C Period Register 5 1111 1111 1111 1111

T4CON 011E TON —TSIDL— — — — — — TGATE TCKPS1 TCKPS0 T32 —TCS—0000 0000 0000 0000

T5CON 0120 TON —TSIDL— — — — — — TGATE TCKPS1 TCKPS0 ——TCS—0000 0000 0000 0000

Legend: u = uninitialized

1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

dsPIC30F3014/4013

NOTES:

dsPIC30F3014/4013

12.0 INPUT CAPTURE MODULE

This section describes the input capture module and

associated operational modes. The features provided

by this module are useful in applications requiring fre-

quency (period) and pulse measurement. Figure 12-1

depicts a block diagram of the input capture module.

Input capture is useful for such modes as:

• Frequency/Period/Pulse Measurements

• Additional Sources of External Interrupts

The key operational features of the input capture

module are:

• Simple Capture Event mode

• Timer2 and Timer3 mode selection

• Interrupt on input capture event

These operating modes are determined by setting the

appropriate bits in the ICxCON register (where

x = 1,2,...,N). The dsPIC DSC devices contain up to 8

capture channels (i.e., the maximum value of N is 8).

The dsPIC30F3014 device contains 2 capture

channels while the dsPIC30F4013 device contains 4

capture channels.

12.1 Simple Capture Event Mode

The simple capture events in the dsPIC30F product

family are:

• Capture every falling edge

• Capture every rising edge

• Capture every 4th rising edge

• Capture every 16th rising edge

• Capture every rising and falling edge

These simple Input Capture modes are configured by

setting t he appropri ate bits, IC M<2:0> (ICxC ON<2:0>).

12.1.1 CAPTURE PRESCALER

There are four input capture prescaler settings speci-

fied by bits ICM<2:0> (ICxCON<2:0>). Whenever the

capture channel is turned off, the prescaler counter is

cleared. In addition, any Reset clears the prescaler

counter.

FIGURE 12-1: INPUT CAPTURE MODE BLOCK DIAGRAM

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046).

ICxBUF

Prescaler

ICx pin

ICM<2:0>

Mode Select

Note: Where ‘x’ is shown, reference is made to the registers or bits associated to the respective input capture

channels 1 through N.

Set Flag

ICxIF

ICTMR

T2_CNT T3_CNT

Edge

Detection

Logic

Clock

Synchronizer

1, 4, 16

From GP Timer Module

16 16

FIFO

R/W

Logic

ICI<1:0>

ICBN E, IC OV

ICxCON Interrupt

Logic

Set Flag

ICxIF

Data Bus

dsPIC30F3014/4013

12.1.2 CAPTURE BUFFER OPERATION

Each capture channel has an associated FIFO buffer

which is four 16-bit words deep. There are two status

flags which provide status on the FIFO buffer:

• ICBNE – Input Capture Buffer Not Empty

• IC OV – Input Capture Ov erfl ow

The ICBFNE is set on the first input capture event and

remain s et unt il all ca pture even ts have b een read fro m

the FIFO. As each word is read from the FIFO, the

remaining words are advanced by one position within

the buffer.

In the event that the FIFO is full with four capture

events and a fifth capture event occurs prior to a read

of the FIFO, an overflow condition occurs and the ICOV

bit is s et to a lo gic ‘1’. T he fifth ca pture eve nt is lost and

is not stored in the FIFO. No additional events are

captured until all four events have been read from the

buffer.

If a FIFO read is performed after the last read and no

new capture event has been received, the read will

yield indeterminate results.

12.1.3 TIMER2 AND TIMER3 SELECTION

MODE

The inp ut capture mod ule cons ist s of up to 8 input cap-

ture chann els. Each channel can select between one of

two timers for the time base, Timer2 or Timer3.

Selection of the timer resource is accomplished

through SFR bit, ICTMR (ICxCON<7>). Timer3 is the

default timer resource available for the input capture

module.

12.1.4 HALL SENSOR MODE

When the input capture module is set for capture on

every edge, rising and falling, ICM<2:0> = 001, the

following operations are performed by the input capture

logic:

• The input capture interrupt flag is set on every

edge, rising and falling.

• The interrupt on Capture mode setting bits,

ICI<1:0>, is ignored since every capture

generates an interrupt.

• A capture overflow condition is not generated in

this mode.

12.2 Input Capture Operation During

Sleep and Idle Modes

An input capture event generates a device wake-up or

interrupt, if enabl ed, if the devi ce is in CPU Id le or Sleep

mode.

Independent of the timer being enabled, the input cap-

ture module wakes up from the CPU Sleep or Idle mode

when a c apture event occurs if ICM<2:0> = 111 and the

interrupt enable bit is asserted. The same wake-up can

generate an interrupt if the conditions for processing the

interrupt have been satisfied. The wake-up feature is

useful as a method of adding extra external pin

interrupts.

12.2.1 INPUT CAPTURE IN CPU SLEEP

MODE

CPU Sleep mode allows input capture module opera-

tion w ith reduced function ality. In the CPU Sleep mode,

the ICI<1:0> bits are not applicable and the input cap-

ture module can only function as an external interrupt

source.

The capture module must be configured for interrupt

only on rising edge (ICM<2:0> = 111) in order for the

input capture module to be used while the device is in

Sleep mode. The prescale settings of 4:1 or 16:1 are

not applicable in this mode.

12.2.2 INPUT CAPTURE IN CPU IDLE

MODE

CPU Idle mode allows input capture module operation

with full functionality. In the CPU Idle mode, the Inter-

rupt mode selected by the ICI<1:0> bits is applicable,

as well as the 4:1 and 16:1 capture prescale settings

which are defined by c on trol bi ts ICM<2:0 >. This mod e

requires the selected timer to be enabled. Moreover,

the ICSIDL bit must be asserted to a logic ‘0’.

If the input capture module is defined as

ICM<2:0> = 111 in CPU Idle mode, the input capture

pin serves only as an external interrupt pin.

12.3 Input Capture Interrupts

The inpu t captur e channe ls have the a bility to generate

an interrupt based upon the selected number of

capture events. The selection number is set by control

bits, ICI<1:0> (ICxCON<6:5>).

Each chan nel provide s an interrupt flag (ICxI F) bit. The

respective capture channel interrupt flag is located in

the corresponding IFSx STATUS register.

Enabling an interrupt is accomplished via the respec-

tive capture channel interrupt enable (ICxIE) bit. The

capture interrupt enable bit is located in the

corresponding IEC Control register.

dsPIC30F3014/4013

TABLE 12-1: dsPIC30F3014 INPUT CAPTURE REGISTER MAP

TABLE 12-2: dsPIC30F4013 INPUT CAPTURE REGISTER MAP

SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

IC1BUF 0140 Input 1 Capture Register uuuu uuuu uuuu uuuu

IC1CON 0142 ——ICSIDL— — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000

IC2BUF 0144 Input 2 Capture Register uuuu uuuu uuuu uuuu

IC2CON 0146 ——ICSIDL— — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000

Legend: u = uninitialized bit

1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

IC1BUF 0140 Input 1 Capture Register uuuu uuuu uuuu uuuu

IC1CON 0142 ——ICSIDL— — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000

IC2BUF 0144 Input 2 Capture Register uuuu uuuu uuuu uuuu

IC2CON 0146 ——ICSIDL— — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000

IC7BUF 0158 Input 7 Capture Register uuuu uuuu uuuu uuuu

IC7CON 015A ——ICSIDL— — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000

IC8BUF 015C Input 8 Capture Register uuuu uuuu uuuu uuuu

IC8CON 015E ——ICSIDL— — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000

Legend: u = uninitialized bit

1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

dsPIC30F3014/4013

NOTES:

dsPIC30F3014/4013

13.0 OUTPUT COMPARE MODULE

This sec tion desc ribes the ou tput comp are modu le and

associated operational modes. The features provided

by this module are useful in applications requiring

operational modes, such as:

• Generation of Variable Width Output Pulses

• Pow er Fact or Correction

Figure 13-1 depicts a block diagram of the output

compare module.

The key operational features of the output compare

module include:

• Timer2 and Timer3 Selection mode

• Simple Output Compare Match mode

• Dual Output Compare Match mode

• Simple PWM mode

• Output Compare During Sleep and Idle modes

• Interrupt on Output Compare/PWM Event

These operating modes are determined by setting the

appropriate bits in the 16-bit OCxCON SFR (where

x = 1,2,3,...,N). The dsPIC DSC devices contain up to

8 comp are channels (i.e., the maximum value of N is 8).

The dsPIC30F3014 device contains 2 compare

channels while the dsPIC30F4013 device contains 4

compare channels.

OCxRS and OCxR in Figure 13-1 represent the Dual

Compare registers. In the Dual Compare mode, the

OCxR register is used for the f irst comp are and O CxRS

is used for the second compare.

13.1 T imer2 and Ti mer3 Selection Mode

Each output compare channel can select between one

of two 16-bit timers, Timer2 or Timer3.

The selection of the timers is controlled by the OCTSEL

bit (OCxCON<3> ). Timer2 is th e defau lt timer resource

for the output compare module.

FIGURE 13-1: OUTPUT COMPARE MODE BLOCK DIAGRAM

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046).

OCxR

Comparator

Output

Logic QS

OCM<2:0>

Output OCx

Set Flag bit

OCxIF

OCxRS

Mode Select

Note: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare

channels 1 through N.

OCFA

OCTSEL 01

T2P2_MATCHTMR2<15:0 TMR3<15:0> T3P3_MATCH

From GP

(for x = 1, 2, 3 or 4)

or OCFB

(for x = 5, 6, 7 or 8)

Timer Module

Enable

dsPIC30F3014/4013

13.2 Simple Output Compare Match

Mode

When control bits OCM<2:0> (OCxCON<2:0>) = 001,

010 or 011, the selected output compare channel is

configured for one of three simple Output Compare

Match modes:

• Compare forces I/O pin low

• Compare forces I/O pin high

• Compare toggles I/O pin

The OCxR reg is ter i s us ed in th es e m ode s. Th e O C xR

selected incrementing timer count. When a compare

occurs, o ne of these C ompare Match modes oc curs. If

the counter resets to zero before reaching the value in

OCxR, the state of the OCx pin remains unchanged.

13.3 Dual Output Compare Match Mode

When control bits OCM<2:0> (OCxCON<2:0>) = 100

or 101, the selec ted outp ut compare chan nel is co nfig-

ured for one of two Dual Output Compare modes,

which are:

• Single Output Pulse mode

• Conti nuous Output Pulse mode

13.3.1 SINGLE PULSE MODE

For the use r to confi gure the modul e for the ge ner ation

of a single output pulse, the following steps are

required (assuming timer is off):

• Determine instruction cycle time TCY.

• Calcu la te d es ired pulse w id t h v al ue bas ed on TCY.

• Calcu late time to S t art pulse from time r start v alue

of 0x0000.

• Write pulse width start and stop times into OCxR

and OCxRS Compare registers (x denotes

channel 1, 2, ...,N).

• Set Timer Period register to value equal to or

greater than value in OCxRS Compare register.

• Set OCM<2:0> = 100.

• Enable timer, TON (TxCON<15>) = 1.

To initiate another single pulse, issue another write to

set OCM<2:0> = 100.

13.3.2 CONTINUOUS PULSE MODE

For the use r to confi gure the modul e for the ge neratio n

of a continuous stream of output pulses, the following

steps are required:

• Determine instruction cycle time TCY.

• Calculate desired pulse value based on TCY.

• Calculate timer to Start pulse width from timer

start value of 0x0000.

• Write pulse width Start and Stop times into OCxR

and OCxRS (x denotes channel 1, 2, ...,N)

Compare registers, respectively.

• Set Timer Period register to value equal to or

greater than value in OCxRS Compare register.

• Set OCM<2:0> = 101.

• Enable timer, TON (TxCON<15>) = 1.

13.4 Simple PWM Mode

When control bits OCM<2:0> (OCxCON<2:0>) = 110

or 111, the selec ted outp ut comp are c hannel is confi g-

ured for th e PWM mode of opera tion. When co nfigured

for the PWM mode of operation, OCxR is the main l atch

(read-only) and OCxRS is the secondary latch. This

enables glitchless PWM transitions.

The user must perform the following steps in order to

configure the output compare module for PWM

operation:

1. Set the PWM pe riod by writing to the appropriate

period register.

2. Set the PWM duty cy cle by writ ing to the OCxRS

3. Configure the output compare module for PWM

operation.

4. Set the TMRx prescale value and enable the

Timer, TON (TxCON<15>) = 1.

13.4.1 INPUT PIN FAULT PROTECTION

FOR PWM

When control bits OCM<2:0> (OCxCON<2:0>) = 111,

the selected output compare channel is again config-

ured fo r the PWM mode of op eration with the add itional

feature of input Fault protection. While in this mode, if

a logic ‘0’ is detected on the OCF A/B pin, the respective

PWM output pin is placed in the high-impedance input

state . The O CFLT bit (OCxCON <4>) in dicate s wheth er

a Faul t condition ha s occurred. Thi s state is mai ntaine d

until both of the following events have occurred:

• The external Fault condition has been removed.

• The PWM mode has been re-enabled by writing

to the appropriate control bits.

dsPIC30F3014/4013

13.4.2 PWM PERIOD

The PWM period is specified by writing to the PRx

Equation 13-1.

EQUATION 13-1:

PWM frequency is defined as 1/[PWM period].

When the selected TMRx is equal to its respective

period reg ister, PRx, the followi ng f our event s occ ur on

the next i ncrement cycle:

• TMRx is clear e d.

• The OCx pin is set.

- Exception 1: If PWM duty cycle is 0x0000,

the OCx pin remains low.

- Exception 2: If d uty cycl e is gr eater tha n PRx,

the pin remains high.

• The PWM duty cycle is latched from OCxRS into

OCxR.

• The corresponding timer interrupt flag is set.

See Figure 13-2 for key PWM period comparisons.

Timer3 is referred to in Figure 13-2 for clarity.

FIGURE 13-2: PWM OUTPUT TIMING

13.5 Output Comp are Operation During

CPU Sleep Mode

When the CPU enters Sleep mode, all internal clocks

are stopped. Therefore, when the CPU enters the

Sleep s t ate, the outp ut c om p a re c ha nnel drives the pi n

to the active state that was observed prior to entering

the CPU Sleep state.

For exam ple, if the pin was hi gh when the CPU entere d

the Sleep state, the pin remains high. Likewise, if the

pin wa s low when the CPU entered th e Sleep st ate, th e

pin remains low. In either case, the output compare

module res um es operation w hen the dev ic e w a ke s u p.

13.6 Output Comp are Operation During

CPU Idle Mode

When the CPU enters the Idle mode, the output

compare module can operate with full functionality.

The output compare channel operates during the CPU

Idle mode if the OCSIDL bit (OCxCON<13>) is at logic

‘0’ and the selected time base (Timer2 or Timer3) is

enabled and the TSIDL bit of the selected timer is set

to logic ‘0’.

13.7 Outp u t Compare In terrupt s

The outpu t comp are channels have the abil ity to gener-

ate an interrupt on a compare match, for whichever

Match mode has been selected.

For all modes, except the PWM mode, when a com-

pare e vent occurs, the resp ective interrupt fl ag (OCxIF)

is asserted and an interrupt is generated, if enabled.

The OCxIF bit is located in the corresponding IFS

STATUS register and must be cleared in software. The

interrupt is enabled via the respective compare inter-

rupt enable (OCxIE) bit located in the corresponding

IEC Control register.

For the PWM mode, when a n event occurs, the respec-

tive timer interrupt flag (T2IF or T3IF) is asserted and

an interrupt is generated, if enabled. The IF bit is

located in the IFS0 STATUS register and must be

cleared in software. The interrupt is enabled via the

respective timer interrupt enable bit (T2IE or T3IE)

located in the IEC0 Control register. The output

compare interrupt flag is never set during the PWM

mode of operation.

PWM period = [(PRx) + 1] • 4 • TOSC •

(TMRx prescale value)

Period

Duty Cycle

TMR3 = Duty Cycle TMR3 = Duty Cycle

TMR3 = PR3

T3IF = 1

(Interrupt Flag)

OCxR = OCxRS

TMR3 = PR3

(Interrupt Flag)

OCxR = OCxRS

T3IF = 1

(OCxR) (OCxR)

dsPIC30F3014/4013

TABLE 13-1: dsPIC30F3014 OUTPUT COMPARE REGISTER MAP

TABLE 13-2: dsPIC30F4013 OUTPUT COMPARE REGISTER MAP

SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

OC1RS 0180 Output Compare 1 Secondary Register 0000 0000 0000 0000

OC1R 0182 Output Compare 1 Main Register 0000 0000 0000 0000

OC1CON 0184 ——OCSIDL— — — — — — — — OCFLT OCTSEL OCM<2:0> 0000 0000 0000 0000

OC2RS 0186 Output Compare 2 Secondary Register 0000 0000 0000 0000

OC2R 0188 Output Compare 2 Main Register 0000 0000 0000 0000

OC2CON 018A ——OCSIDL— — — — — — — — OCFLT OCTSE OCM<2:0> 0000 0000 0000 0000