© Semiconductor Components Industries, LLC, 2010
July, 2010 Rev. 18
1Publication Order Number:
MC100EPT23/D
MC100EPT23
3.3V Dual Differential
LVPECL/LVDS/CML to
LVTTL/LVCMOS Translator
The MC100EPT23 is a dual differential LVPECL/LVDS/CML to
LVTTL/LVCMOS translator. Because LVPECL (Positive ECL),
LVDS, and positive CML input levels and LVTTL/LVCMOS output
levels are used, only +3.3 V and ground are required. The small
outline 8-lead SOIC package and the dual gate design of the EPT23
makes it ideal for applications which require the translation of a clock
or data signal.
The EPT23 is available in only the ECL 100K standard. Since there
are no LVPECL outputs or an external VBB reference, the EPT23 does
not require both ECL standard versions. The LVPECL/LVDS inputs
are differential. Therefore, the MC100EPT23 can accept any standard
differential LVPECL/LVDS input referenced from a VCC of +3.3 V.
Features
1.5 ns Typical Propagation Delay
Maximum Operating Frequency > 275 MHz
LVPECL/LVDS/CML Inputs, LVTTL/LVCMOS Outputs
24 mA LVTTL Outputs
Operating Range: VCC = 3.0 V to 3.6 V with GND = 0 V
PbFree Packages are Available
*For additional marking information, refer to
Application Note AND8002/D.
MARKING
DIAGRAMS*
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
M= Date Code
G= PbFree Package
KA23
ALYWG
G
SOIC8
D SUFFIX
CASE 751
1
8
TSSOP8
DT SUFFIX
CASE 948R
1
8
1
8
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
ORDERING INFORMATION
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KPT23
ALYW
G
1
8
DFN8
MN SUFFIX
CASE 506AA
3T M G
G
14
(Note: Microdot may be in either location)
1
MC100EPT23
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2
1
2
3
45
6
7
8
Q0
GND
VCC
Figure 1. Logic Diagram and 8Lead Pinout
D0
Q1D1
D1
D0
LVPECL LVTTL
(Top View)
Table 1. PIN DESCRIPTION
Pin Function
Q0, Q1 LVTTL/LVCMOS Outputs
D0**, D1**
D0**, D1**
Differential LVPECL/LVDS/CML Inputs
VCC Positive Supply
GND Ground
EP (DFN8 only) Thermal exposed pad must be
connected to a sufficient thermal conduit.
Electrically connect to the most negative
supply (GND) or leave unconnected, floating
open.
** Pins will default to VCC/2 when left open.
Table 2. ATTRIBUTES
Characteristics Value
Internal Input Pulldown Resistor 50 kW
Internal Input Pullup Resistor 50 kW
ESD Protection Human Body Model
Machine Model
Charged Device Model
> 1500 V
> 100 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Level 1
Flammability Rating Oxygen Index: 28 to 34 UL 94 V0 @ 0.125 in
Transistor Count 91 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 3. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Unit
VCC Power Supply GND = 0 V 3.8 V
VIInput Voltage GND = 0 V VI VCC 3.8 V
Iout Output Current Continuous
Surge
50
100
mA
mA
TAOperating Temperature Range 40 to +85 °C
Tstg Storage Temperature Range 65 to +150 °C
qJA Thermal Resistance (JunctiontoAmbient) 0 lfpm
500 lfpm
SOIC8
SOIC8
190
130
°C/W
°C/W
qJC Thermal Resistance (JunctiontoCase) Standard Board SOIC841 to 44 °C/W
qJA Thermal Resistance (JunctiontoAmbient) 0 lfpm
500 lfpm
TSSOP8
TSSOP8
185
140
°C/W
°C/W
qJC Thermal Resistance (JunctiontoCase) Standard Board TSSOP841 to 44 °C/W
qJA Thermal Resistance (JunctiontoAmbient) 0 lfpm
500 lfpm
DFN8
DFN8
129
84
°C/W
°C/W
Tsol Wave Solder Pb
PbFree
<2 to 3 sec @ 248°C
<2 to 3 sec @ 260°C
265
265
°C
qJC Thermal Resistance (JunctiontoCase) (Note 2) DFN8 35 to 40 °C/W
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. JEDEC standard multilayer board 2S2P (2 signal, 2 power)
MC100EPT23
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3
Table 4. PECL DC CHARACTERISTICS VCC = 3.3 V, GND = 0 V (Note 3)
Symbol Characteristic
40°C 25°C 85°C
Unit
Min Typ Max Min Typ Max Min Typ Max
ICCH Power Supply Current (Outputs set to HIGH) 10 20 35 10 20 35 10 20 35 mA
ICCL Power Supply Current (Outputs set to LOW) 15 27 40 15 27 40 15 27 40 mA
VIH Input HIGH Voltage 2075 2420 2075 2420 2075 2420 mV
VIL Input LOW Voltage 1355 1675 1355 1675 1355 1675 mV
VIHCMR Input HIGH Voltage Common Mode Range
(Note 4)
1.2 3.3 1.2 3.3 1.2 3.3 V
IIH Input HIGH Current 150 150 150 mA
IIL Input LOW Current D
D
150
150
150
150
150
150
0.5 mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. All values vary 1:1 with VCC.
4. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
Table 5. LVTTL/LVCMOS OUTPUT DC CHARACTERISTICS VCC = 3.3 V, GND = 0.0 V, TA = 40°C to 85°C
Symbol Characteristic Condition Min Typ Max Unit
VOH Output HIGH Voltage IOH = 3.0 mA 2.4 V
VOL Output LOW Voltage IOL = 24 mA 0.5 V
IOS Output Short Circuit Current 180 50 mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
Table 6. AC CHARACTERISTICS VCC = 3.0 V to 3.6 V, GND = 0.0 V (Note 5)
Symbol Characteristic
40°C 25°C 85°C
Unit
Min Typ Max Min Typ Max Min Typ Max
fmax Maximum Frequency (Figure 2) 275 350 275 350 275 350 MHz
tPLH,
tPHL
Propagation Delay to
Output Differential (Note 6)
1.1 1.5 1.8 1.1 1.5 1.8 1.1 1.5 1.8 ns
tSK+ +
tSK
tSKPP
OutputtoOutput Skew++
OutputtoOutput Skew−−
ParttoPart Skew (Note 7)
15
35
70
60
80
500
15
40
70
70
80
500
30
40
140
125
80
500
ps
tJITTER Random Clock Jitter (RMS) (Figure 2) 5 10 5 10 5 10 ps
VPP Input Voltage Swing (Differential Configuration) 150 800 1200 150 800 1200 150 800 1200 mV
tr tfOutput Rise/Fall Times (0.8 V 2.0 V) Q, Q 330 600 900 330 600 900 330 650 900 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Measured with a 750 mV 50% dutycycle clock source. RL = 500 W to GND and CL = 20 pF to GND. Refer to Figure 3.
6. Reference (VCC = 3.3V ± 5%; GND = 0 V)
7. Skews are measured between outputs under identical conditions.
MC100EPT23
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4
Figure 2. Typical VOH / Jitter versus Frequency (255C)
FREQUENCY (MHz)
VOH (V)
0.0
1.0
2.0
3.0
VOH
VOL 0.5 V
JITTER
RANDOM CLOCK JITTER (ps RMS)
0 100 200 300 400
12
8
4
0
Figure 3. TTL Output Loading Used for Device Evaluation
CHARACTERISTIC TEST
CL*R
L
AC TEST LOAD
GND
*CL includes
fixture
capacitance
APPLICATION
TTL RECEIVER
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5
ORDERING INFORMATION
Device Package Shipping
MC100EPT23D SOIC898 Units / Rail
MC100EPT23DG SOIC8
(PbFree)
98 Units / Rail
MC100EPT23DR2 SOIC82500 / Tape & Reel
MC100EPT23DR2G SOIC8
(PbFree)
2500 / Tape & Reel
MC100EPT23DT TSSOP8100 Units / Rail
MC100EPT23DTG TSSOP8
(PbFree)
100 Units / Rail
MC100EPT23DTR2 TSSOP82500 / Tape & Reel
MC100EPT23DTR2G TSSOP8
(PbFree)
2500 / Tape & Reel
MC100EPT23MNR4 DFN8 1000 / Tape & Reel
MC100EPT23MNR4G DFN8
(PbFree)
1000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D ECL Clock Distribution Techniques
AN1406/D Designing with PECL (ECL at +5.0 V)
AN1503/D ECLinPSt I/O SPiCE Modeling Kit
AN1504/D Metastability and the ECLinPS Family
AN1568/D Interfacing Between LVDS and ECL
AN1672/D The ECL Translator Guide
AND8001/D Odd Number Counters Design
AND8002/D Marking and Date Codes
AND8020/D Termination of ECL Logic Devices
AND8066/D Interfacing with ECLinPS
AND8090/D AC Characteristics of ECL Devices
MC100EPT23
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6
PACKAGE DIMENSIONS
SOIC8 NB
CASE 75107
ISSUE AJ
SEATING
PLANE
1
4
58
N
J
X 45 _
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 75101 THRU 75106 ARE OBSOLETE. NEW
STANDARD IS 75107.
A
BS
D
H
C
0.10 (0.004)
DIM
A
MIN MAX MIN MAX
INCHES
4.80 5.00 0.189 0.197
MILLIMETERS
B3.80 4.00 0.150 0.157
C1.35 1.75 0.053 0.069
D0.33 0.51 0.013 0.020
G1.27 BSC 0.050 BSC
H0.10 0.25 0.004 0.010
J0.19 0.25 0.007 0.010
K0.40 1.27 0.016 0.050
M0 8 0 8
N0.25 0.50 0.010 0.020
S5.80 6.20 0.228 0.244
X
Y
G
M
Y
M
0.25 (0.010)
Z
Y
M
0.25 (0.010) ZSXS
M
____
1.52
0.060
7.0
0.275
0.6
0.024
1.270
0.050
4.0
0.155
ǒmm
inchesǓ
SCALE 6:1
*For additional information on our PbFree strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
MC100EPT23
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7
PACKAGE DIMENSIONS
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A2.90 3.10 0.114 0.122
B2.90 3.10 0.114 0.122
C0.80 1.10 0.031 0.043
D0.05 0.15 0.002 0.006
F0.40 0.70 0.016 0.028
G0.65 BSC 0.026 BSC
L4.90 BSC 0.193 BSC
M0 6 0 6
____
SEATING
PLANE
PIN 1
14
85
DETAIL E
B
C
D
A
G
DETAIL E
F
M
L
2X L/2
U
S
U0.15 (0.006) T
S
U0.15 (0.006) T
S
U
M
0.10 (0.004) V S
T
0.10 (0.004)
T
V
W
0.25 (0.010)
8x REFK
IDENT
K0.25 0.40 0.010 0.016
TSSOP8
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948R02
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
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8
PACKAGE DIMENSIONS
ÇÇ
ÇÇ
DFN8 2x2, 0.5P
CASE 506AA01
ISSUE E
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994 .
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.20 MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
A
D
E
B
C0.10
PIN ONE
2X
REFERENCE
2X
TOP VIEW
SIDE VIEW
BOTTOM VIEW
A
L
(A3)
D2
E2
C
C0.10
C0.10
C0.08
NOTE 4 A1 SEATING
PLANE
e/2
e
8X
K
NOTE 3
b
8X
0.10 C
0.05 C
ABB
DIM MIN MAX
MILLIMETERS
A0.80 1.00
A1 0.00 0.05
A3 0.20 REF
b0.20 0.30
D2.00 BSC
D2 1.10 1.30
E2.00 BSC
E2 0.70 0.90
e0.50 BSC
K
L0.25 0.35
14
85
*For additional information on our PbFree strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
2.30
0.50
0.50
8X
DIMENSIONS: MILLIMETERS
0.30 PITCH
8X
1
PACKAGE
OUTLINE
RECOMMENDED
L1
DETAIL A
L
OPTIONAL
CONSTRUCTIONS
L
ÉÉ
ÉÉ
DETAIL B
MOLD CMPDEXPOSED Cu
OPTIONAL
CONSTRUCTION
DETAIL B
DETAIL A
L1 −−− 0.10
0.30 REF
0.90
1.30
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USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
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Phone: 81357733850
MC100EPT23/D
ECLinPS is a trademark of Semiconductor Components INdustries, LLC (SCILLC).
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