MC74VHCT541ADTR2 - ON Semiconductor

June, 2011 − Rev. 5

1Publication Order Number:

MC74VHCT541A/D

MC74VHCT541A

Octal Bus Buffer

The MC74VHCT541A is an advanced high speed CMOS octal bus

buffer fabricated with silicon gate CMOS technology. It achieves high

speed operation similar to equivalent Bipolar Schottky TTL while

maintaining CMOS low power dissipation.

The MC74VHCT541A is a noninverting, 3−state, buffer/line

driver/line receiver. When either OE1 or OE2 is high, the terminal

outputs are in the high impedance state.

The VHCT inputs are compatible with TTL levels. This device can

be used as a level converter for interfacing 3.3 V to 5.0 V, because it

has full 5.0 V CMOS level output swings.

The VHCT541A input and output (when disabled) structures

provide protection when voltages between 0 V and 5.5 V are applied,

regardless of the supply voltage. These input and output structures

help prevent device destruction caused by supply

voltage−input/output voltage mismatch, battery backup, hot insertion,

etc.

Features

•High Speed: tPD = 5.4 ns (Typ) at VCC = 5.0 V

•Low Power Dissipation: ICC = 4 mA (Max) at TA = 25°C

•TTL−Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V

•Power Down Protection Provided on Inputs and Outputs

•Balanced Propagation Delays

•Designed for 4.5 V to 5.5 V Operating Range

•Low Noise: VOLP = 1.6 V (Max)

•Pin and Function Compatible with Other Standard Logic Families

•Latchup Performance Exceeds 300 mA

•ESD Performance:

Human Body Model > 2000 V;

Machine Model > 200 V

•Chip Complexity: 134 FETs or 33.5 Equivalent Gates

•These Devices are Pb−Free and are RoHS Compliant

SOEIAJ−20

SUFFIX M

CASE 967

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See detailed ordering and shipping information in the package

dimensions section on page 4 of this data sheet.

ORDERING INFORMATION

MARKING

DIAGRAMS

74VHCT541

AWLYWWG

TSSOP−20

SUFFIX DT

CASE 948E

SOIC−20WB

SUFFIX DW

CASE 751D

VHCT

541A

ALYWG

VHCT541A

AWLYYWWG

A = Assembly Location

WL, L = Wafer Lot

YY, Y = Year

WW, W = Work Week

G or G= Pb−Free Package

(Note: Microdot may be in either location)

FUNCTION TABLE

Inputs

Output Y

OE1 OE2 A

MC74VHCT541A

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18 Y1

17 Y2

16 Y3

15 Y4

14 Y5

13 Y6

12 Y7

11 Y8

OE1

OE2

OUTPUT

ENABLES

DATA

INPUTS

NONINVERTING

OUTPUTS

Figure 1. Logic Diagram

Figure 2. Pin Assignment

OE1

GND

A4 5

OE2

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MAXIMUM RATINGS

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎ

Value

ÎÎÎ

Unit

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage

ÎÎÎÎÎ

– 0.5 to + 7.0

ÎÎÎ

ÎÎÎÎ

Vin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage

ÎÎÎÎÎ

– 0.5 to + 7.0

ÎÎÎ

ÎÎÎÎ

Vout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Voltage Outputs in 3−State

High or Low State

ÎÎÎÎÎ

– 0.5 to + 7.0

– 0.5 to VCC + 0.5

ÎÎÎ

ÎÎÎÎ

IIK

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Input Diode Current

ÎÎÎÎÎ

− 20

ÎÎÎ

ÎÎÎÎ

IOK

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Output Diode Current (VOUT < GND; VOUT > VCC)

ÎÎÎÎÎ

±20

ÎÎÎ

ÎÎÎÎ

Iout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Current, per Pin

ÎÎÎÎÎ

±25

ÎÎÎ

ÎÎÎÎ

ICC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Current, VCC and GND Pins

ÎÎÎÎÎ

±75

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Power Dissipation in Still Air, SOIC Package†

TSSOP Package†

ÎÎÎÎÎ

500

450

ÎÎÎ

ÎÎÎÎ

Tstg

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Storage Temperature

ÎÎÎÎÎ

– 65 to + 150

ÎÎÎ

Maximum ratings are those values beyond which device damage can occur. Maximum ratings

applied to the device are individual stress limit values (not normal operating conditions) and are

not valid simultaneously. If these limits are exceeded, device functional operation is not implied,

damage may occur and reliability may be affected.

†Derating −SOIC Packages: – 7 mW/_C from 65_ to 125_C

TSSOP Package: − 6.1 mW/_C from 65_ to 125_C

RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎ

Min

ÎÎÎÎ

Max

ÎÎ

Unit

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage

ÎÎÎ

4.5

ÎÎÎÎ

5.5

ÎÎ

ÎÎÎÎ

Vin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage

ÎÎÎ

ÎÎÎÎ

5.5

ÎÎ

ÎÎÎÎ

Vout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Voltage Outputs in 3−State

High or Low State

ÎÎÎ

ÎÎÎÎ

5.5

VCC

ÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Operating Temperature

ÎÎÎ

− 40

ÎÎÎÎ

+ 85

ÎÎ

ÎÎÎÎ

tr, tf

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Input Rise and Fall Time VCC =5.0V ±0.5V

ÎÎÎ

ÎÎÎÎ

ÎÎ

ns/V

This device contains protection

circuitry to guard against damage

due to high static voltages or electric

fields. However, precautions must

be taken to avoid applications of any

voltage higher than maximum rated

voltages to this high−impedance cir-

cuit. For proper operation, Vin and

Vout should be constrained to the

range GND v (Vin or Vout) v VCC.

Unused inputs must always be

tied to an appropriate logic voltage

level (e.g., either GND or VCC).

Unused outputs must be left open.

MC74VHCT541A

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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC ELECTRICAL CHARACTERISTICS

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎÎ

VCC

ÎÎÎÎÎÎ

TA = 25°C

ÎÎÎÎÎÎ

TA = − 40 to 85°C

ÎÎ

Unit

ÎÎ

Min

ÎÎÎ

Typ

ÎÎÎ

Max

ÎÎÎ

Min

ÎÎÎÎ

Max

ÎÎÎÎ

VIH

ÎÎÎÎÎÎÎÎÎÎ

Minimum High−Level Input Voltage

ÎÎÎÎÎÎÎ

ÎÎÎÎ

4.5 to 5.5

ÎÎ

2.0

ÎÎÎ

2.0

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

VIL

ÎÎÎÎÎÎÎÎÎÎ

Maximum Low−Level Input Voltage

ÎÎÎÎÎÎÎ

ÎÎÎÎ

4.5 to 5.5

ÎÎ

ÎÎÎ

0.8

ÎÎÎ

ÎÎÎÎ

0.8

ÎÎ

ÎÎÎÎ

VOH

ÎÎÎÎÎÎÎÎÎÎ

Minimum High−Level Output

Voltage Vin = VIH or VIL

ÎÎÎÎÎÎÎ

IOH = − 50mA

ÎÎÎÎ

4.5

ÎÎ

4.4

ÎÎÎ

4.5

ÎÎÎ

4.4

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎ

IOH = − 8mA

ÎÎÎÎ

4.5

ÎÎ

3.94

ÎÎÎ

3.80

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

VOL

ÎÎÎÎÎÎÎÎÎÎ

Maximum Low−Level Output

Voltage Vin = VIH or VIL

ÎÎÎÎÎÎÎ

IOL = 50mA

ÎÎÎÎ

4.5

ÎÎ

ÎÎÎ

0.0

ÎÎÎ

0.1

ÎÎÎ

ÎÎÎÎ

0.1

ÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎ

IOL = 8mA

ÎÎÎÎ

4.5

ÎÎ

ÎÎÎ

0.36

ÎÎÎ

ÎÎÎÎ

0.44

ÎÎ

ÎÎÎÎ

Iin

ÎÎÎÎÎÎÎÎÎÎ

Maximum Input Leakage Current

ÎÎÎÎÎÎÎ

Vin = 5.5 V or GND

ÎÎÎÎ

0 to 5.5

ÎÎ

ÎÎÎ

±0.1

ÎÎÎ

ÎÎÎÎ

±1.0

ÎÎ

ÎÎÎÎ

IOZ

ÎÎÎÎÎÎÎÎÎÎ

Maximum 3−State Leakage Current

ÎÎÎÎÎÎÎ

Vin = VIL or VIH

Vout = VCC or GND

ÎÎÎÎ

5.5

ÎÎ

ÎÎÎ

± 0.25

ÎÎÎ

ÎÎÎÎ

± 2.5

ÎÎ

ÎÎÎÎ

ICC

ÎÎÎÎÎÎÎÎÎÎ

Maximum Quiescent Supply Current

ÎÎÎÎÎÎÎ

Vin = VCC or GND

ÎÎÎÎ

5.5

ÎÎ

ÎÎÎ

4.0

ÎÎÎ

ÎÎÎÎ

40.0

ÎÎ

ÎÎÎÎ

ICCT

ÎÎÎÎÎÎÎÎÎÎ

Quiescent Supply Current

ÎÎÎÎÎÎÎ

Per Input: VIN = 3.4V

Other Input: VCC or GND

ÎÎÎÎ

5.5

ÎÎ

ÎÎÎ

1.35

ÎÎÎ

ÎÎÎÎ

1.50

ÎÎ

ÎÎÎÎ

IOPD

ÎÎÎÎÎÎÎÎÎÎ

Output Leakage Current

ÎÎÎÎÎÎÎ

VOUT = 5.5V

ÎÎÎÎ

ÎÎ

ÎÎÎ

0.5

ÎÎÎ

ÎÎÎÎ

5.0

ÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎÎÎÎ

TA = 25°C

ÎÎÎÎÎÎ

TA = − 40 to 85°C

ÎÎ

Unit

ÎÎ

Min

ÎÎÎ

Typ

ÎÎÎ

Max

ÎÎÎ

Min

ÎÎÎÎ

Max

ÎÎÎÎ

tPLH,

tPHL

ÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay,

A to Y

ÎÎÎÎÎÎÎÎÎ

VCC = 5.0 ± 0.5V CL = 15pF

CL = 50pF

ÎÎ

ÎÎÎ

5.0

5.5

ÎÎÎ

6.9

7.9

ÎÎÎ

1.0

ÎÎÎÎ

8.0

9.0

ÎÎ

ÎÎÎÎ

tPZL,

tPZH

ÎÎÎÎÎÎÎÎÎÎÎ

Output Enable TIme,

OE to Y

ÎÎÎÎÎÎÎÎÎ

VCC = 5.0 ± 0.5V CL = 15pF

RL = 1kWCL = 50pF

ÎÎ

ÎÎÎ

8.3

8.8

ÎÎÎ

11.3

12.3

ÎÎÎ

1.0

ÎÎÎÎ

13.0

14.0

ÎÎ

ÎÎÎÎ

tPLZ,

tPHZ

ÎÎÎÎÎÎÎÎÎÎÎ

Output Disable Time,

OE to Y

ÎÎÎÎÎÎÎÎÎ

VCC = 5.0 ± 0.5V CL = 50pF

RL = 1kW

ÎÎ

ÎÎÎ

9.4

ÎÎÎ

11.9

ÎÎÎ

1.0

ÎÎÎÎ

13.5

ÎÎ

ÎÎÎÎ

tOSLH,

tOSHL

ÎÎÎÎÎÎÎÎÎÎÎ

Output to Output Skew

ÎÎÎÎÎÎÎÎÎ

VCC = 5.0 ± 0.5V CL = 50pF

(Note 1)

ÎÎ

ÎÎÎ

1.0

ÎÎÎ

ÎÎÎÎ

1.0

ÎÎ

ÎÎÎÎ

Cin

ÎÎÎÎÎÎÎÎÎÎÎ

Maximum Input Capacitance

ÎÎÎÎÎÎÎÎÎ

ÎÎ

ÎÎÎ

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

Cout

ÎÎÎÎÎÎÎÎÎÎÎ

Maximum 3−State Output Capacitance

(Output in High Impedance State)

ÎÎÎÎÎÎÎÎÎ

ÎÎ

ÎÎÎ

ÎÎÎÎ

ÎÎ

CPD Power Dissipation Capacitance (Note 2)

Typical @ 25°C, VCC = 5.0V

1. Parameter guaranteed by design. tOSLH = |tPLHm − tPLHn|, tOSHL = |tPHLm − tPHLn|.

2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.

Average operating current can be obtained by the equation: ICC(OPR) = CPD  VCC  fin + ICC / 8 (per bit). CPD is used to determine the no−load

dynamic power consumption; PD = CPD  VCC2  fin + ICC  VCC.

NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 5.0V)

Symbol Parameter

TA = 25°C

Unit

Typ Max

VOLP Quiet Output Maximum Dynamic VOL 1.2 1.6 V

VOLV Quiet Output Minimum Dynamic VOL −1.2 −1.6 V

VIHD Minimum High Level Dynamic Input Voltage 2.0 V

VILD Maximum Low Level Dynamic Input Voltage 0.8 V

MC74VHCT541A

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ORDERING INFORMATION

Device Package Shipping†

MC74VHCT541ADWG SOIC−20WB

(Pb−Free)

38 Units / Rail

MC74VHCT541ADWRG SOIC−20WB

(Pb−Free)

1000 / Tape & Reel

MC74VHCT541ADTG TSSOP−20* 75 Units / Rail

MC74VHCT541ADTRG TSSOP−20* 2500 / Tape & Reel

MC74VHCT541AMELG SOEIAJ−20

(Pb−Free)

2000 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*This package is inherently Pb−Free.

Figure 3. Switching Waveform Figure 4. Switching Waveform

OE1 or OE2

Y 1.5V

tPZL tPLZ

tPZH tPHZ

HIGH

IMPEDANCE

VOL +0.3V

VOH -0.3V

HIGH

IMPEDANCE

*Includes all probe and jig capacitance

CL*

TEST POINT

DEVICE

UNDER

TEST

OUTPUT

Figure 5. Test Circuit

*Includes all probe and jig capacitance

CL*

TEST POINT

DEVICE

UNDER

TEST

OUTPUT

Figure 6. Test Circuit

CONNECT TO VCC WHEN

TESTING tPLZ AND tPZL.

CONNECT TO GND WHEN

TESTING tPHZ AND tPZH.

1 kW

GND

tPHL

tPLH

1.5V

VOL

VOH

1.5V

GND

MC74VHCT541A

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PACKAGE DIMENSIONS

B20X

H10X

18X A1

SEATING

PLANE

hX 45_

0.25 M

0.25 S

DIM MIN MAX

MILLIMETERS

A2.35 2.65

A1 0.10 0.25

B0.35 0.49

C0.23 0.32

D12.65 12.95

E7.40 7.60

e1.27 BSC

H10.05 10.55

h0.25 0.75

L0.50 0.90

q0 7

NOTES:

1. DIMENSIONS ARE IN MILLIMETERS.

2. INTERPRET DIMENSIONS AND TOLERANCES

PER ASME Y14.5M, 1994.

3. DIMENSIONS D AND E DO NOT INCLUDE MOLD

PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

5. DIMENSION B DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE PROTRUSION

SHALL BE 0.13 TOTAL IN EXCESS OF B

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

SOIC−20 WB

DW SUFFIX

CASE 751D−05

ISSUE G

MC74VHCT541A

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PACKAGE DIMENSIONS

TSSOP−20

CASE 948E−02

ISSUE C

DIM

MIN MAX MIN MAX

INCHES

6.60 0.260

MILLIMETERS

B4.30 4.50 0.169 0.177

C1.20 0.047

D0.05 0.15 0.002 0.006

F0.50 0.75 0.020 0.030

G0.65 BSC 0.026 BSC

H0.27 0.37 0.011 0.015

J0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L6.40 BSC 0.252 BSC

M0 8 0 8

____

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION:

MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE

MOLD FLASH, PROTRUSIONS OR GATE

BURRS. MOLD FLASH OR GATE BURRS

SHALL NOT EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE

INTERLEAD FLASH OR PROTRUSION.

INTERLEAD FLASH OR PROTRUSION

SHALL NOT EXCEED 0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE

DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08

(0.003) TOTAL IN EXCESS OF THE K

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE

DETERMINED AT DATUM PLANE −W−.

ÍÍÍÍ

110

1120

PIN 1

IDENT

−T−

0.100 (0.004)

DGH

SECTION N−N

JJ1

−W−

SEATING

PLANE

−V−

−U−

0.10 (0.004) V S

20X REFK

L/2

U0.15 (0.006) T

DETAIL E

0.25 (0.010)

DETAIL E

6.40 0.252

--- ---

U0.15 (0.006) T

7.06

16X

0.36 16X

1.26

0.65

DIMENSIONS: MILLIMETERS

PITCH

SOLDERING FOOTPRINT

MC74VHCT541A

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PACKAGE DIMENSIONS

SOEIAJ−20

M SUFFIX

CASE 967−01

ISSUE A

DIM MIN MAX MIN MAX

INCHES

--- 2.05 --- 0.081

MILLIMETERS

0.05 0.20 0.002 0.008

0.35 0.50 0.014 0.020

0.15 0.25 0.006 0.010

12.35 12.80 0.486 0.504

5.10 5.45 0.201 0.215

1.27 BSC 0.050 BSC

7.40 8.20 0.291 0.323

0.50 0.85 0.020 0.033

1.10 1.50 0.043 0.059

0.70 0.90 0.028 0.035

--- 0.81 --- 0.032

_10 _0

_10 _

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS D AND E DO NOT INCLUDE

MOLD FLASH OR PROTRUSIONS AND ARE

MEASURED AT THE PARTING LINE. MOLD FLASH

OR PROTRUSIONS SHALL NOT EXCEED 0.15

(0.006) PER SIDE.

4. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

5. THE LEAD WIDTH DIMENSION (b) DOES NOT

INCLUDE DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08 (0.003)

TOTAL IN EXCESS OF THE LEAD WIDTH

DIMENSION AT MAXIMUM MATERIAL CONDITION.

DAMBAR CANNOT BE LOCATED ON THE LOWER

RADIUS OR THE FOOT. MINIMUM SPACE

BETWEEN PROTRUSIONS AND ADJACENT LEAD

TO BE 0.46 ( 0.018).

110

0.13 (0.005)

0.10 (0.004)

VIEW P

DETAIL P

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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

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MC74VHCT541A/D

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