Features
Monolithic CMOS A/D Converters
Microprocessor Compatible
Parallel and Serial Output
Inherent Track/Hold Input
True 12, 14 and 16-Bit Precision
Conversion Times:
CS501616.25 µs
CS501414.25 µs
CS5012A 7.20 µs
Self Calibration Maintains Accuracy
Over Time and Temperature
Low Power Dissipation: 150 mW
Low Distortion
General Description
The CS5012A/14/16 are 12, 14 and 16-bit monolithic
analog to digital converters with conversion times of
7.2µs, 14.25µs and 16.25µs. Unique self-calibration cir-
cuitry insures excellent linearity and differential non-
linearity, with no missing codes. Offset and full scale
errors are kept within 1/2 LSB (CS5012A/14) and
1 LSB (CS5016), eliminating the need for calibration.
Unipolar and bipolar input ranges are digitally select-
able.
The pin compatible CS5012A/14/16 consist of a DAC,
conversion and calibration microcontroller, oscillator,
comparator, microprocessor compatible 3-state I/O,
and calibration circuitry. The input track-and-hold, in-
herent to the devices’ sampling architecture, acquires
the input signal after each conversion using a fast
slewing on-chip buffer amplifier. This allows throughput
rates up to 100 kHz (CS5012A), 56 kHz (CS5014) and
50 kHz (CS5016).
An evaluation board (CDB5012/14/16) is available
which allows fast ev aluation of ADC performance.
ORDERING INFORMATION: Pages 2-45, 2-46, & 2-47
JAN '01
DS14F7
2-7
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 FAX : (512) 445 7581
16, 14 & 12-Bit, Self-Calibrating A/D Converters
Semiconductor Corporation CS5016 CS5014 CS5012A
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15 (MSB)
D4 (LSB) CS5012A
6
7
8
9
12
13
14
15
16
17
18
19
D2 (LSB) CS5014
D0 (LSB) CS5016
D1
SCLKEOTEOCSDATA
2
3
4
5
37 38 39 40
D3
CLKIN
CLOCK
GENERATOR
20
INTRLV
34
RST
3221
A0
23
RD
22
HOLD
1
BW
3324
CAL
35
CS BP/UP
REFBUF
AGND
29
VREF
28
AIN26
27
CHARGE
REDISTRIBUTION
DAC
COMPARATOR
VA+ VA- VD+ VD- DGND TST
25 30 11 36 10 31
+
-
+
-
+
-
+
-
CONTROL
CALIBRATION
MEMORY
MICROCONTROLLER
STATUS REGISTER
Copyright
Crystal Semiconductor Corporation 1995
(All Rights Reserved)
CS5012A
CS5012A ANALOG CHARACTERISTICS (TA = TMIN to TMAX; VA+, VD+ = 5V;
VA-, VD- = -5V; VREF = 2.5V to 4.5V; fclk = 6.4 MHz for -7, 4 MHz for -12; Analog Source Impedance = 200)
CS5012A-B
Parameter* Min Typ Max Units
Specified Temperature Range -40 to +85 °C
Accuracy
Linearity Error (Note 1)
Drift (Note 2) ±1/4
±1/8 ±1/2 LSB12
LSB12
Differential Linearity (Note 1)
Drift (Note 2) ±1/4
±1/32 ±1/2 LSB12
LSB12
Full Scale Error (Note 1)
Drift (Note 2) ±1/4
±1/16 ±1/2 LSB12
LSB12
Unipolar Offset (Note 1)
Drift (Note 2) ±1/4
±1/16 ±1/2 LSB12
LSB12
Bipolar Offset (Note 1)
Drift (Note 2) ±1/4
±1/16 ±1/2 LSB12
LSB12
Bipolar Negative Full-Scale Error(Note 1)
Drift (Note 2) ±1/4
±1/16 ±1/2 LSB12
LSB12
Total Unadjusted Error (Note 1)
Drift (Note 2) ±1/4
±1/4 LSB12
LSB12
Dynamic Performance (Bipolar Mode)
Peak Harmonic or (Note 1)
Spurious Noise
Full Scale, 1 kHz Input
Full Scale, 12 kHz Input 84
84 92
88 dB
dB
Total Harmonic Distortion 0.008 %
Signal-to-Noise Ratio (Note 1)
1 kHz, 0 dB Input
1 kHz, -60 dB Input 72 73
13 dB
dB
Noise (Note 3)
Unipolar Mode
Bipolar Mode 45
90 µVrms
µVrms
Notes:1.Applies after c alibration at any temperature within the specified temperature range.
2.Total drift over specified temperature range since calibration at power-up at 25 °C
3.Wideband noise aliased into the baseband. Referred to the input.
* Refer to
Parameter Definitions
(immediately following the pin descriptions at the end of this data sheet).
Specifications are s ubject to change without notice.
2-8 DS14F7
CS5012A ANALOG CHARACTERISTICS (continued)
CS5012A-B
Parameter* Min Typ Max Units
Specified Temperature Range -40 to +85 °C
Analog Input
Aperture Time 25 ns
Aperture Jitter 100 ps
Input Capacitance (Note 4)
Unipolar ModeCS5012A
Bipolar Mode CS5012A
103
72
137
96
pF
pF
pF
pF
Conversion & Throughput
Conversion Time -7 (Notes 5 and 6) 7.2 µs
Acquisition Time -7 (Note 6) 2.5 2.8
µs
Throughput -7 (Note 6) 100
kHz
Power Supplies
DC Power Supply Currents (Note 7)
IA+
IA-
D+
(CS5012A) ID+
ID-
12
-12
3
6
-3
19
-19
6
7.5
-6
mA
mA
mA
mA
mA
Power Dissipation (Note 7) 150 250 mW
Power Supply Rejection (Note 8)
Positive Supplies
Negative Supplies 84
84 dB
dB
Notes:4.Applies only in track mode. When converting or c alibrating, input capacitance will not exceed 15 pF.
5.Measured from falling trans ition on HOLD to falling transition on EOC.
6.Conversion, acquisition, and throughput times depend on CLKIN, sampling, and calibration conditions.
The numbers shown assume sampling and conversion is synchronized with the CS5012A/14/16 ’s
conversion clock , interleave calibrate is disabled, and operation is from the full-rated, external c lock.
Refer to the section
Conversion Time/Throughput
for a detailed discussion of conversion timing.
7.All outputs unloaded. All inputs CMO S levels.
8.With 300 mV p-p, 1 kHz ripple applied to each analog supply separately in bipolar mode. Rejection
improves by 6 dB in the unipolar mode to 90 dB. Figure 13 shows a plot of typical power supply
rejection versus frequency.
CS5012A
DS14F7 2-9
CS5014 ANALOG CHARACTERISTICS (TA = TMIN to TMAX; VA+, VD+ = 5V;
VA-, VD - = -5V; VREF = 4.5V; CLK IN = 4 MHz for -14, 2 MHz for -28; Analog S ource Impedance = 200)
CS5014-B
Parameter* Min Typ Max Units
Specified Temperature Range -40 to +85 °C
Accuracy
Linearity Error (Note 1)
Drift (Note 2)
±1/4
±1/8
±1/2 LSB14
LSB14
LSB14
Differential Linearity (Note 1)
Drift (Note 2) ±1/4
±1/32 ±1/2 LSB14
LSB14
Full Scale Error (Note 1)
Drift (Note 2) ±1/2
±1/4 ±1 LSB14
LSB14
Unipolar Offset (Note 1)
Drift (Note 2)
±1/4
±1/4
±3/4 LSB14
LSB14
LSB14
Bipolar Offset (Note 1)
Drift (Note 2)
±1/4
±1/2
±3/4 LSB14
LSB14
LSB14
Bipolar Negative Full-Scale Error(Note 1)
Drift (Note 2)
±1/2
±1/4
±1 LSB14
LSB14
LSB14
Total Unadjusted Error (Note 1)
Drift (Note 2) ±1
±1LSB14
LSB14
Dynamic Performance (Bipolar Mode)
Peak Harmonic or (Note 1)
Spurious Noise
Full Scale, 1 kHz Input
Full Scale, 12 kHz Input
94
84
98
87
dB
dB
dB
dB
Total Harmonic Distortion 0.003 %
Signal-to-Noise Ratio (Notes 1 and 9)
1 kHz, 0 dB Input
1 kHz, -60 dB Input
82 84
23
dB
dB
dB
Noise (Note 3)
Unipolar Mode
Bipolar Mode 45
90 µVrms
µVrms
Notes:9.A detailed plot of S/(N+D) vs. input amplitude appears in Figure 26 for the CS5014 and Figure 28
for the CS5016.
* Refer to
Parameter Definitions
(immediately following the pin descriptions at the end of this data sheet).
Specifications are s ubject to change without notice.
CS5014
2-10 DS14F7
CS5014
CS5014 ANALOG CHARACTERISTICS (continued)
CS5014-B
Parameter* Min Typ Max Units
Specified Temperature Range -40 to +85 °C
Analog Input
Aperture Time 25 ns
Aperture Jitter 100 ps
Input Capacitance (Note 4)
Unipolar Mode
Bipolar Mode 275
165 375
220 pF
pF
Conversion & Throughput
Conversion Time -14(Notes 5 and 6) 14.25 µs
Acquisition Time -14 (Note 6) 3.0 3.75 µs
Throughput -14 (Note 6) 55.6 kHz
Power Supplies
DC Power Supply Currents (Note 7)
IA+
IA-
ID+
ID-
9
-9
3
-3
19
-19
6
-6
mA
mA
mA
mA
Power Dissipation (Note 7) 120 250 mW
Power Supply Rejection (Note 8)
Positive Supplies
Negative Supplies 84
84 dB
dB
DS14F7 2-11
CS5016
CS5016 ANALOG CHARACTERISTICS (TA = TMIN to TMAX; VA+, VD+ = 5V;
VA-, VD - = -5V; VREF = 4.5V; CLK IN = 4 MHz for -16, 2 MHz for -32; Analog S ource Impedance = 200;
Synchronous S ampling.)
CS5016-J, K CS5016-A, B CS5016-S, T
Parameter* Min Typ Max Min Typ Max Min Typ Max Units
Specified Temperature Range 0 to +70 -40 to + 85 -55 to +125 °C
Accuracy
Linearity Error J, A , S (Note 1)
K, B, T
Drift (Note 2)
0.002
0.001
±1/4
0.003
0.0015 0.002
0.001
±1/4
0.003
0.0015 0.002
0.001
±1/4
0.0076
0.0015 %FS
%FS
LSB16
Differential Linearity (Note 10) 16 16 16 Bits
Full Scale Error J, A, S (Note 1)
K, B, T
Drift (Note 2)
±2
±2
±1
±3
±3±2
±2
±1
±3
±3±2
±2
±2
±4
±3LSB16
LSB16
LSB16
Unipolar Offset J, A, S (Note 1)
K, B, T
Drift (Note 2)
±1
±1
±1
±2
±3/2 ±1
±1
±1
±3
±3±1
±1
±2
±4
±3LSB16
LSB16
LSB16
Bipolar Offset J, A , S (Note 1)
K, B, T
Drift (Note 2)
±1
±1
±1
±2
±3/2 ±1
±1
±2
±2
±2±1
±1
±2
±4
±2LSB16
LSB16
LSB16
Bipolar Negative Full-Scale Error(Note 1)
J, A, S
K, B, T
Drift (Note 2)
±2
±2
±1
±3
±3±2
±2
±2
±3
±3±2
±2
±2
±5
±3LSB16
LSB16
LSB16
Dynamic Performance (Bipolar Mode)
Peak Harmonic or (Note 1)
Spurious Noise
Full Scale, 1 kHz Input J, A, S
K, B, T
Full Scale, 12 kHz Input J, A, S
K, B, T
96
100
85
85
100
104
88
91
96
100
85
85
100
104
88
91
92
100
82
85
100
104
88
91
dB
dB
dB
dB
Total Harmonic Distortion J, A, S
Full Scale, 1 kHz Input K, B, T 0.002
0.001 0.002
0.001 0.002
0.001 %
%
Signal-to-Noise Ratio (Notes 1 and 9)
1 kHz, 0 dB Input J, A, S
K, B, T
1 kHz, -60 dB Input J, A, S
K, B, T
87
90 90
92
30
32
87
90 90
92
30
32
84
90 90
92
30
32
dB
dB
dB
dB
Noise (Note 3)
Unipolar Mode
Bipolar Mode 35
70 35
70 35
70 µVrms
µVrms
Notes:10.Minimum resolution for which no missing codes is guaranteed
* Refer to
Parameter Definitions
(immediately following the pin descriptions at the end of this data sheet).
Specifications are s ubject to change without notice.
2-12 DS14F7
CS5016
CS5016 ANALOG CHARACTERISTICS (continued)
CS5016-J, K CS5016-A, B CS5016-S, T
Parameter* Min Typ Max Min Typ Max Min Typ Max Units
Specified Temperature Range 0 to +70 -40 to + 85 -55 to +125 °C
Analog Input
Aperture Time 25 25 25 ns
Aperture Jitter 100 100 100 ps
Input Capacitance (Note 4)
Unipolar Mode
Bipolar Mode 275
165 375
220 275
165 375
220 275
165 375
220 pF
pF
Conversion & Throughput
Conversion Time -16(Notes 5 and 6)
-32 16.25
32.5 16.25
32.5 16.25
32.5 µs
µs
Acquisition Time -16 (Note 6)
-32 3.0
4.5 3.75
5.25 3.0
4.5 3.75
5.25 3.0
4.5 3.75
5.25 µs
µs
Throughput -16 (Note 6)
-32 50
26.5 50
26.5 50
26.5 kHz
kHz
Power Supplies
DC Power Supply Currents (Note 7)
IA+
IA-
ID+
ID-
9
-9
3
-3
19
-19
6
-6
9
-9
3
-3
19
-19
6
-6
9
-9
3
-3
19
-19
6
-6
mA
mA
mA
mA
Power Dissipation (Note 7) 120 250 120 250 120 250 mW
Power Supply Rejection (Note 8)
Positive Supplies
Negative Supplies 84
84 84
84 84
84 dB
dB
DS14F7 2-13
SWITCHING CHARACTERISTICS (TA = TMIN to TMAX; VA+, VD+ = 5V ±10%;
VA-, VD- = -5V ±10%; Inputs: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF, BW = VD+)
Parameter Symbol Min Typ Max Units
CS5012A CLKIN Frequency:
Internally Generated:
Externally Supplied: -7
fCLK 1.75
100 kHz -
--
6.4 MHz
MHz
CS5014/5016 CLKIN Frequency:
Internally Generated: -14, -16
-14, -32
Externally Supplied: -14, -16
-14, -32
fCLK 1.75
1
100 kHz
100 kHz
-
-
-
-
-
-
4
2
MHz
MHz
MHz
MHz
CLKIN Duty Cycle 40 - 60 %
Rise Times: Any Digital Input
Any Digital Output trise -
--
20 1.0
-µs
ns
Fall Times: Any Digital Input
Any Digital Output tfall -
--
20 1.0
-µs
ns
HOLD Pulse Width thpw 1/fCLK+50 - tc ns
Conversion Time: CS5012A
CS5014
CS5016
tc 49/fCLK+50
57/fCLK
65/fCLK
-
-
-
53/fCLK+235
61/fCLK+235
69/fCLK+235
ns
ns
ns
Data Delay Time tdd - 40 100 ns
EOC Pulse Width (Note 11) tepw 4/fCLK-20 - - ns
Set Up Times: CAL, INTRLV to CS Low
A0 to CS and RD Low tcs
tas 20
20 10
10 -
-ns
ns
Hold Times: CS or RD High to A0 Invalid
CS High to CAL, INTRLV Invalid tah
tch 50
50 30
30 -
-ns
ns
Access Times: CS Low to Data Valid A, B, J, K
S, T
RD Low to Data Valid A, B, J, K
S, T
tca
tra
-
-
-
-
90
115
90
90
120
150
120
150
ns
ns
ns
ns
Output Float Delay: K, B
CS or RD High to Output Hi-Z Ttfd -
-90
90 110
140 ns
ns
Serial Clock Pulse Width Low
Pulse Width High tpwl
tpwh -
-2/fCLK
2/fCLK -
-ns
ns
Set Up Times: SDATA to SCLK Rising tss 2/fCLK-50 2/fCLK -ns
Hold Times: SCLK Rising to SDATA tsh 2/fCLK-100 2/fCLK -ns
Notes:11. EOC remains low 4 CLKIN cycles if CS and RD are held low. Otherwise, it returns high
within 4 CLKIN cycles from the start of a data read operation or a conversion cycle.
CS5012A, CS5014, CS5016
2-14 DS14F7
90%
10%
t
fall
rise
t
90%
10%
Hi-Z Hi-Z
ch
t
t
cs
t
ah
t
fd
tas
tra
tca
HOLD
EOC
Output Data
thpw
t
c
LAST CONVERSION DATA VALID
t
dd NEW DATA VALID
tepw
D0-D15
A0
CS
RD
CAL, INTRLV
SDATA
t
ss tsh
SCLK
t
pwl
t
pwh
Rise and Fall Times
Conversion Timing
Serial Output Timing
Read and Calibration Control Timing
CS5012A, CS5014, CS5016
DS14F7 2-15
CS5012A, CS5014, CS5016
DIGITAL CHARACTERISTICS (TA = TMIN to TMAX; VA+, VD+ = 5V ±10%; VA-, VD- = -5V ±10%)
Parameter Symbol Min Typ Max Units
High-Level Input Voltage VIH 2.0 - - V
Low-Level Input Voltage VIL --0.8V
High-Level Output Voltage (Note 12) VOH (VD+) - 1.0V - - V
Low-Level Output Voltage Iout = 1.6mA VOL --0.4V
Input Leakage Current Iin --10µA
3-State Leakage Current IOZ --±10 µA
Digital Output Pin Capacitance Cout -9-pF
Notes:12.Iout = -100 µA. This specification guarantees TTL compatibility (VOH = 2.4V @ Iout = -40 µA).
RECOMMENDED OPERATING CONDITIONS (AGND, DGND = 0V, see Note 13)
Parameter Symbol Min Typ Max Units
DC Power Supplies: Positive Digital
Negative Digital
Positive Analog
Negative Analog
VD+
VD-
VA+
VA-
4.5
-4.5
4.5
-4.5
5.0
-5.0
5.0
-5.0
VA+
-5.5
5.5
-5.5
V
V
V
V
Analog Reference Voltage VREF 2.5 4.5 (VA+) - 0.5 V
Analog Input Voltage: (Note 14)
Unipolar
Bipolar VAIN
VAIN AGND
-VREF -
-VREF
VREF V
V
Notes:13.All voltages with respect to ground.
14.The CS5012A/14/16 can accept input voltages up to the analog supplies (VA + and VA-).
It will output all 1’s for inputs above VREF and all 0’s for inputs below AGND in unipolar mode
and -VREF in bipolar mode.
ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0V, all voltages with repect to ground.)
WARNING:Operation at or beyond these limits may reult in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
Parameter Symbol Min Max Units
DC Power Supplies: Positive Digital (Note 15)
Negative Digital
Positive Analog
Negative Analog
VD+
VD-
VA+
VA-
-0.3
0.3
-0.3
0.3
6.0
-6.0
6.0
-6.0
V
V
V
V
Input Current, Any Pin E xcept Supplies (Note 16) Iin - ±10 mA
Analog Input Voltage (AIN and VREF pins) VINA (VA-) - 0.3 (VA+) + 0.3 V
Digital Input Voltage VIND -0.3 (VA+) + 0.3 V
Ambient Operating Temperature TA -55 125 °C
Storage Temperature Tstg -65 150 °C
Notes:15.In addition, VD+ s hould not be greater than (VA+) + 0.3V.
16.Transient currents of up to 100 mA will not cause SCR latch-up.
2-16 DS14F7
THEORY OF OPERATION
The CS5012A/14/16 family utilize a successive
approximation conversion technique. The analog
input is successively compared to the output of a
D/A converter controlled by the conversion algo-
rithm. Successive approximation begins by
comparing the analog input to the DAC output
which is set to half-scale (MSB on, all other bits
off). If the input is found to be below half-scale,
the MSB is reset to zero and the input is com-
pared to one-quarter scale (next MSB on, all
others off). If the input were above half-scale, the
MSB would remain high and the next compari-
son would be at three-quarters of full scale. This
procedure continues until all bits have been exer-
cised.
A unique charge redistribution architecture is
used to implement the successive approximation
algorithm. Instead of the traditional resistor net-
work, the DAC is an array of binary-weighted
capacitors. All capacitors in the array share a
common node at the comparators input. Their
other terminals are capable of being connected to
AIN, AGND, or VREF (Figure 1). When the de-
vice is not calibrating or converting, all capacitors
are tied to AIN forming Ctot. Switch S1 is closed
and the charge on the array, Qin, tracks the input
sign al V in (Figure 2a).
When the conversion command is issued, switch
S1 opens as shown in Figure 2b. This traps
charge Qin on the comparator side of the capaci-
tor array and creates a floating node at the
comparators input. The conversion algorithm op-
erates on this fixed charge, and the signal at the
analog input pin is ignored. In effect, the entire
DAC capacitor array serves as analog memory
AIN
VREF
AGND
CC/2
C/4 C/8
MSB
LSB
Bit 11 Bit 10
Bit 9
Bit 8
Bit 0
Dummy
C/X S1
Bit 13
Bit 15
Bit 12
Bit 14 Bit 11
Bit 13
Bit 10
Bit 12
CS5012A:
CS5014:
CS5016:
C/X
X = 2048
X = 8192
X = 32768
CS5012A
CS5014
CS5016
C = C + C/2 + C/4 + ... + C/X
tot
Figure 1. Charge Redistribution DAC
(1-D)Ctot
in
Q+
-
Vfn To MCU
S1
Ctot
D.
VREF
AGND
D for
VREF
Vin =0V
fn
V=
Figure 2b. Convert Mode
in
Q
Ctot
S1
V
in
AIN
+
-
To MCU
=V
in
C
tot
in
-Q
Figure 2a. Trac king Mode
CS5012A, CS5014, CS5016
DS14F7 2-17
during conversion much like a hold capacitor in a
sample/hold amplifier.
The conversion consists of manipulating the free
plates of the capacitor array to VREF and AGND
to form a capacitive divider. Since the charge at
the floating node remains fixed, the voltage at
that point depends on the proportion of capaci-
tance tied to VREF versus AGND. The
successive-approximation algorithm is used to
find the proportion of capacitance, termed D in
Figure 2b, which when connected to the refer-
ence will drive the voltage at the floating node
(Vfn) to zero. That binary fraction of capacitance
represents the converters digital output.
This charge redistribution architecture easily sup-
ports bipolar input ranges. If half the capacitor
array (the MSB capacitor) is tied to VREF rather
than AIN in the track mode, the input range is
doubled and is offset half-scale. The magnitude
of the reference voltage thus defines both positive
and negative full-scale (-VREF to +VREF), and
the digital code is an offset binary representation
of the input.
Calibration
The ability of the CS5012A/14/16 to convert ac-
curately clearly depends on the accuracy of their
comparator and DAC. The CS5012A/14/16 util-
ize an "auto-zeroing" scheme to null errors
introduced by the comparator. All offsets are
stored on the capacitor array while in the track
mode and are effectively subtracted from the in-
put signal when a conversion is initiated.
Auto-zeroing enhances power supply rejection at
frequencies well below the conversion rate.
To achieve complete accuracy from the DAC, the
CS5012A/14/16 use a novel self-calibration
scheme. Each bit capacitor, shown in Figure 1,
actually consists of several capacitors which can
be manipulated to adjust the overall bit weight.
An on-chip microcontroller adjusts the subarrays
to precisely ratio the bits. Each bit is adjusted to
just balance the sum of all less significant bits
plus one dummy LSB (for example, 16C = 8C +
4C + 2C + C + C). Calibration resolution for the
array is a small fraction of an LSB resulting in
nearly ideal differential and in tegral linearity.
DIGITAL CIRCUIT CONNECTIONS
The CS5012A/14/16 can be applied in a wide va-
riety of master clock, sampling, and calibration
conditions which directly affect the devices con-
version time and throughput. The devices also
feature on-chip 3-state output buffers and a com-
plete interface for connecting to 8-bit and 16-bit
digital systems. Output data is also available in
serial format.
Master Clock
The CS5012A/14/16 operate from a master clock
(CLKIN) which can be externally supplied or in-
ternally generated. The internal oscillator is
activated by externally tying the CLKIN input
low. Alternatively, the CS5012A/14/16 can be
synchronized to the external system by driving
the CLKIN pin with a TTL or CMOS clock sig-
nal.
CLKIN
Master Clock
(Optional)
HOLD
EOT
CS5012A/14/16
Figure 3b. Synchronous Sampling
CLKIN
Master Clock
(Optional)
HOLD
Sampling
Clock
CS5012A/14/16
Figure 3a. Asynchronous Sampling
CS5012A, CS5014, CS5016
2-18 DS14F7
All calibration, conversion, and throughput times
directly scale to CLKIN frequency. Thus,
throughput can be precisely controlled and/or
maximized using an external CLKIN signal. In
contrast, the CS5012A/14/16s internal oscillator
will vary from unit-to-unit and over temperature.
The CS5012A/14/16 can typically convert with
CLKIN as low as 10 kHz at room temperature.
Initiating Conversions
A falling transition on the HOLD pin places the
input in the hold mode and initiates a conversion
cycle. Upon completion of the conversion cycle,
the CS5012A/14/16 automatically return to the
track mode. In contrast to systems with separate
track-and-holds and A/D converters, a sampling
clock can simply be connected to the HOLD in-
put (Figure 3a). The duty cycle of this clock is
not critical. It need only remain low at least one
CLKIN cycle plus 50 ns, but no longer than the
minimum conversion time or an additional con-
version cycle will be initiated with inadequate
time for acquisition.
Microprocessor-Controlled Operation
Sampling and conversion can be placed under
microprocessor control (Figure 4) by simply gat-
ing the devices decoded address with the write
strobe for the HOLD input. Thus, a write cycle to
the CS5012A/14/16s base address will initiate a
conversion. However, the write cycle must be to
the odd address (A0 high) to avoid initiating a
software controlled reset (see Reset below).
The calibration control inputs, CAL, and
INTRLV are inputs to a set of transparent latches.
These signals are internally latched by CS return-
ing high. They must be in the appropriate state
whenever the chip is selected during a read or
write cycle. Address lines A1 and A2 are shown
connected to CAL and INTRLV in Figure 4 plac-
ing calibration under microprocessor control as
well. Thus, any read or write cycle to the
CS5012A/14/16s base address will initiate or ter-
minate calibration. Alternatively, A0, INTRLV,
and CAL may be connected to the microproces-
sor data bus.
Conversion Time/Throughput
Upon completing a conversion cycle and return-
ing to the track mode, the CS5012A/14/16
require time to acquire the analog input signal
before another conversion can be initiated. The
acquisition time is specified as six CLKIN cycles
plus 2.25 µs (1.32 µs for the CS5012A -7 version
only). This adds to the conversion time to define
the converters maximum throughput. The con-
version time of the CS5012A/14/16, in turn,
depends on the sampling, calibration, and CLKIN
conditions.
HOLD
CS5012A/14/16
Addr
Dec
A3
AN
Address
Bus
WR
RD
CS
RD
INTRLV
A2
A1
CAL
A0A0
ADDR VALID
Figure 4b. Conversions under Microprocessor Control
CS5012A/14/16
CS
Addr
Dec
A3
AN
Address
Bus
RDRD
CONCLK HOLD
INTRLV
CAL
A0
A2
A1
A0
ADDR VALID
Figure 4a. Conversions Asynchronous to CLKIN
CS5012A, CS5014, CS5016
DS14F7 2-19
Asynchronous Sampling
The CS5012A/14/16 internally operate from a
clock which is delayed and divided down from
CLKIN (fCLK/4). If sampling is not synchronized
to this internal clock, the conversion cycle may
not begin until up to four clock cycles after
HOLD goes low even though the charge is
trapped immediately. In this asynchronous mode
(Figure 3a), the four clock cycles add to th e mini-
mum 49, 57 and 65 clock cycles (for the
CS5012A/14/16 respectively) to define the maxi-
mum conversion time (see Figure 5a and
Table 1).
Synchronous Sampling
To achieve maximum throughput, sampling can
be synchronized with the internal conversion
clock by connecting the End-of-Track (EOT) out-
put to HOLD (Figure 3b). The EOT output falls
15 CLKIN cycles after EOC indicating the ana-
log input has been acquired to the
CS5012A/14/16s specified accuracy. The EOT
output is synchronized to the internal conversion
clock, so the four clock cycle synchronization un-
certainty is removed yielding throughput at
[1/64]fCLK for the CS5012A, [1/72]fCLK for
CS5014 and [1/80]fCLK for CS5016 where fCLK
is the CLKIN frequency (see Figure 5b and Ta-
ble 1).
*
Conversion
(49 + N cycles)
1 / Throughput
(64 + N cycles)
Output
EOT
Output
EOC
Input
HOLD
Acquisition
(15 cycles)
*Dashed line: CS & RD = 0 CS5012AN = 0
Solid line: See Figure 9 CS5014 N = 8
CS5016 N = 16
Figure 5b. Synchronous (Loopback Mode)
Conversion
Synchronization Uncertai nty (4 cycles)
Input
Output
Output
Acquisition
HOLD
EOC
EOT
1 / Throughput
Figure 5a. Asynchronous Sampling (External Clock)
Throughput TimeConversion Time
Sampling Mode
Synchronous (Loopback)
Asynchronous
Min
64tclk
N/A
N/A
Max
64tclk
59 1.32
µ
s
tclk+
59 2.25
µ
s
tclk+
Max
+ 235 ns53tclk
49tclk
+ 235 ns53tclk
Min
49tclk
49tclk
49tclk
-7
-12,-24
CS5012A
CS5014
57tclk
57tclk + 235 ns61tclk
57tclk 72tclk
N/A
72tclk
67 2.25
µ
s
tclk+
Synchronous (Loopback)
Asynchronous
65tclk
65tclk + 235 ns69tclk
65tclk 80tclk
N/A
80tclk
75 2.25
µ
stclk+
Synchronous (Loopback)
Asynchronous
CS5016
Table 1. Conversion and Throughput Times (tclk = Master Clock Period)
CS5012A, CS5014, CS5016
2-20 DS14F7