1MAY 2001
DSC-5993/-
2001 Integrated Device Technology, Inc.
2.5 VOLT HIGH-SPEED TeraSyncTM
FIFO 36-BIT CONFIGURATIONS
65,536 x 36, 131,072 x 36,
262,144 x 36
ADVANCE INFORMATION
IDT72T36105
IDT72T36115
IDT72T36125
The IDT logo is a registered trademark and the TeraSync FIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
FEATURES:
Choose among the following memory organizations:
IDT72T36105
65,536 x 36
IDT72T36115
131,072 x 36
IDT72T36125
262,144 x 36
Up to 200 MHz Operation of Clocks
Functionally compatible to the 32,768 x36 TeraSync devices
User selectable HSTL/LVTTL Input and/or Output
Read Enable & Read Clock Echo outputs aid high speed operation
User selectable Asynchronous read and/or write port timing
Mark & Retransmit, resets read pointer to user marked position
Write Chip Select (WCS) input disables Write Port HSTL inputs
Read Chip Select (RCS) synchronous to RCLK
Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of eight preselected offsets
Program programmable flags by either serial or parallel means
Selectable synchronous/asynchronous timing modes for Almost-
Empty and Almost-Full flags
Separate SCLK input for Serial programming of flag offsets
User selectable input and output port bus-sizing
- x36 in to x36 out
- x36 in to x18 out
- x36 in to x9 out
- x18 in to x36 out
- x9 in to x36 out
Big-Endian/Little-Endian user selectable byte representation
Auto power down minimizes standby power consumption
Master Reset clears entire FIFO
Partial Reset clears data, but retains programmable settings
Empty, Full and Half-Full flags signal FIFO status
Select IDT Standard timing (using EF and FF flags) or First Word
Fall Through timing (using OR and IR flags)
Output enable puts data outputs into high impedance state
JTAG port, provided for Boundary Scan function
Available in 240-pin (19mm x 19mm)Plastic Ball Grid Array (PBGA)
Easily expandable in depth and width
Independent Read and Write Clocks (permit reading and writing
simultaneously)
High-performance submicron CMOS technology
Industrial temperature range (–40°°
°°
°C to +85°°
°°
°C) is available
FUNCTIONAL BLOCK DIAGRAM
INPUT REGISTER
OUTPUT REGISTER
RAM ARRAY
65,536 x 36
131,072 x 36
262,144 x 36
FLAG
LOGIC
FF/IR
PAF
EF/OR
PAE
HF
READ POINTER
READ
CONTROL
LOGIC
WRITE CONTROL
LOGIC
WRITE POINTER
RESET
LOGIC
WEN WCLK/WR
D
0
-D
n
(x36, x18 or x9)
LD
MRS
REN
RCLK/RD
OE
Q
0
-Q
n
(x36, x18 or x9)
OFFSET REGISTER
PRS
FWFT/SI
SEN
RT
5993 drw01
BUS
CONFIGURATION
BM
CONTROL
LOGIC
BE
OW
IP
PFM
FSEL0
FSEL1
IW
MARK
SCLK
RCS
JTAG CONTROL
(BOUNDARY SCAN)
TCK
TMS
TDO
TDI
TRST
ASYR
WCS
ERCLK
EREN
HSTL I/0
CONTROL
Vref
WHSTL
RHSTL
ASYW
SHSTL
2
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T36105/72T36115/72T36125 2.5V TeraSync 36-BIT FIFO
65,536 x 36, 131,072 x 36, 262,144 x 36
PIN CONFIGURATION
PBGA: 1mm pitch, 19mm x 19mm (BB240-1, order code: BB)
TOP VIEW
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
D21
D19 D20 D13
GND
TDO
GND
D4 TMS
GND
D5D10
D23
D22
D1
Q24
Q14GND Q0 Q2 Q11Q8Q3
GND
GND GNDGND GND GND
GND GND GND
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
D24
V
CC
GND
GND
GND
GND
GND
GND
GND
GND GND
GND
GND
GND
GND
GND
GND
GND
V
CC
REN
GND
PAF
EREN V
DDQ
OE
RCLKV
CC
V
CC
V
CC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
12 345678910111213141516
A1 BALL PAD CORNER
MRS
V
CC
V
CC
D35
D32
D29
D26
FF
EF
V
CC
V
CC
V
CC
D33
D30
D27
V
CC
V
CC
V
CC
V
CC
SEN
V
CC
V
CC
V
CC
D34
D31
D28
D25 Q27
V
DDQ
V
DDQ
V
DDQ
V
DDQ
Q33
Q30
RCS V
DDQ
V
DDQ
V
CC
V
CC
V
CC
SCLK
V
CC
V
CC
V
CC
V
CC
WCS
V
CC
V
CC
V
CC
PAELD HF
GND V
DDQ
MARK V
DDQ
RT
SHSTLFWFT/SI FS0
OW IPFS1 BE
GND PFMBM ASYR
RHSTL
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
WHSTL
ASYW
VREF
IW
GND
GND
GND
GND
V
CC
V
DDQ
V
DDQ
V
CC
WEN GND
WCLK PRS
V
CC
5993 drw02
U
V
D18
V
CC
D16 D15
TDI
TCK
TRST
D6 D0
D2
D9D12
D14D17
D3
Q15
Q16GND ERCLK Q4 Q13Q10Q7
Q5D11 D8D7 GND Q6Q1 Q9 Q12
17 18
Q22
Q20
Q21
Q23
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
Q25
V
DDQ
V
DDQ
V
DDQ
Q34
Q31
Q28
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
Q35
Q32
Q29
Q26
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
Q19
V
DDQ
Q17
Q18
3
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T36105/72T36115/72T36125 2.5V TeraSync 36-BIT FIFO
65,536 x 36, 131,072 x 36, 262,144 x 36
DESCRIPTION:
The IDT72T36105/72T36115/72T36125 are exceptionally deep,
extrememly high speed, CMOS First-In-First-Out (FIFO) memories with
clocked read and write controls and a flexible Bus-Matching x36/x18/x9 data
flow. These FIFOs offer several key user benefits:
Flexible x36/x18/x9 Bus-Matching on both read and write ports
A user selectable MARK location for retransmit
User selectable I/O structure for HSTL or LVTTL
Asynchronous/Synchronous translation on the read or write ports
The first word data latency period, from the time the first word is written to an
empty FIFO to the time it can be read, is fixed and short.
High density offerings up to 9 Mbit
Bus-Matching TeraSync FIFOs are particularly appropriate for network,
video, telecommunications, data communications and other applications that
need to buffer large amounts of data and match busses of unequal sizes.
Each FIFO has a data input port (Dn) and a data output port (Qn), both of
which can assume either a 36-bit, 18-bit or a 9-bit width as determined by the
state of external control pins Input Width (IW), Output Width (OW), and Bus-
Matching (BM) pin during the Master Reset cycle.
The input port can be selected as either a Synchronous (clocked) interface,
or Asynchronous interface. During Synchronous operation the input port is
controlled by a Write Clock (WCLK) input and a Write Enable (WEN) input. Data
present on the Dn data inputs is written into the FIFO on every rising edge of
WCLK when WEN is asserted. During Asynchronous operation only the WR
input is used to write data into the FIFO. Data is written on a rising edge of WR,
the WEN input should be tied to its active state, (LOW).
The input port can be selected for either 2.5V LVTTL or HSTL operation,
this operation is selected by the state of the WHSTL input during a master reset.
A Write Chip Select input (WCS) is provided for use when the write port is in
HSTL mode. During HSTL operation the WCS input can be used to disable write
port inputs (data only).
The output port can be selected as either a Synchronous (clocked) interface,
or Asynchronous interface. During Synchronous operation the output port is
controlled by a Read Clock (RCLK) input and Read Enable (REN) input. Data
is read from the FIFO on every rising edge of RCLK when REN is asserted.
During Asynchronous operation only the RD input is used to read data from the
FIFO. Data is read on a rising edge of RD, the REN input should be tied to its
active state, LOW. When Asynchronous operation is selected on the output port
the FIFO must be configured for Standard IDT mode, also the RCS should be
tied LOW and the OE input used to provide three-state control of the outputs, Qn.
The output port can be selected for either 2.5V LVTTL or HSTL operation,
this operation is selected by the state of the RHSTL input during a master reset.
An Output Enable (OE) input is provided for three-state control of the outputs.
A Read Chip Select (RCS) input is also provided, the RCS input is synchronized
to the read clock, and also provides three-state control of the Qn data outputs.
When RCS is disabled, the data outputs will be high impedance. During
Asynchronous operation of the output port, RCS should be enabled, held LOW.
Echo Read Enable, EREN and Echo Read Clock, ERCLK outputs are
provided. These are outputs from the read port of the FIFO that are required
for high speed data communication, to provide tighter synchronization between
the data being transmitted from the Qn outputs and the data being received by
the input device. Data read from the read port is available on the output bus with
respect to EREN and ERCLK, this is very useful when data is being read at
high speed. The ERCLK and EREN outputs are non-functional when the Read
port is setup for Asynchronous mode.
The frequencies of both the RCLK and the WCLK signals may vary from 0
to fMAX with complete independence. There are no restrictions on the frequency
of the one clock input with respect to the other.
There are two possible timing modes of operation with these devices: IDT
Standard mode and First Word Fall Through (FWFT) mode.
In IDT Standard mode, the first word written to an empty FIFO will not appear
on the data output lines unless a specific read operation is performed. A read
operation, which consists of activating REN and enabling a rising RCLK edge,
will shift the word from internal memory to the data output lines.
In FWFT mode, the first word written to an empty FIFO is clocked directly
to the data output lines after three transitions of the RCLK signal. A REN does
not have to be asserted for accessing the first word. However, subsequent
words written to the FIFO do require a LOW on REN for access. The state of
the FWFT/SI input during Master Reset determines the timing mode in use.
For applications requiring more data storage capacity than a single FIFO
can provide, the FWFT timing mode permits depth expansion by chaining FIFOs
in series (i.e. the data outputs of one FIFO are connected to the corresponding
data inputs of the next). No external logic is required.
These FIFOs have five flag pins, EF/OR (Empty Flag or Output Ready),
FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable
Almost-Empty flag) and PAF (Programmable Almost-Full flag). The EF and FF
functions are selected in IDT Standard mode. The IR and OR functions are
selected in FWFT mode. HF, PAE and PAF are always available for use,
irrespective of timing mode.
PAE and PAF can be programmed independently to switch at any point in
memory. Programmable offsets determine the flag switching threshold and can
be loaded by two methods: parallel or serial. Eight default offset settings are also
provided, so that PAE can be set to switch at a predefined number of locations
from the empty boundary and the PAF threshold can also be set at similar
predefined values from the full boundary. The default offset values are set during
Master Reset by the state of the FSEL0, FSEL1, and LD pins.
For serial programming, SEN together with LD on each rising edge of
SCLK, are used to load the offset registers via the Serial Input (SI). For parallel
programming, WEN together with LD on each rising edge of WCLK, are used
to load the offset registers via Dn. REN together with LD on each rising edge
of RCLK can be used to read the offsets in parallel from Qn regardless of whether
serial or parallel offset loading has been selected.
During Master Reset (MRS) the following events occur: the read and write
pointers are set to the first location of the FIFO. The FWFT pin selects IDT
Standard mode or FWFT mode.
The Partial Reset (PRS) also sets the read and write pointers to the first
location of the memory. However, the timing mode, programmable flag
programming method, and default or programmed offset settings existing before
Partial Reset remain unchanged. The flags are updated according to the timing
mode and offsets in effect. PRS is useful for resetting a device in mid-operation,
when reprogramming programmable flags would be undesirable.
It is also possible to select the timing mode of the PAE (Programmable Almost-
Empty flag) and PAF (Programmable Almost-Full flag) outputs. The timing
modes can be set to be either asynchronous or synchronous for the PAE and
PAF flags.
If asynchronous PAE/PAF configuration is selected, the PAE is asserted
LOW on the LOW-to-HIGH transition of RCLK. PAE is reset to HIGH on the LOW-
to-HIGH transition of WCLK. Similarly, the PAF is asserted LOW on the LOW-
to-HIGH transition of WCLK and PAF is reset to HIGH on the LOW-to-HIGH
transition of RCLK.
4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T36105/72T36115/72T36125 2.5V TeraSync 36-BIT FIFO
65,536 x 36, 131,072 x 36, 262,144 x 36
DESCRIPTION (CONTINUED)
If synchronous PAE/PAF configuration is selected , the PAE is asserted and
updated on the rising edge of RCLK only and not WCLK. Similarly, PAF is
asserted and updated on the rising edge of WCLK only and not RCLK. The mode
desired is configured during MasterReset by the state of the Programmable Flag
Mode (PFM) pin.
This device includes a Retransmit from Mark feature that utilizes two control
inputs, MARK and , RT (Retransmit). If the MARK input is enabled with respect
to the RCLK, the memory location being read at that point will be marked. Any
subsequent retransmit operation, RT goes LOW, will reset the read pointer to
this ‘marked’ location.
The device can be configured with different input and output bus widths as
shown in Table 1.
A Big-Endian/Little-Endian data word format is provided. This function is
useful when data is written into the FIFO in long word format (x36/x18) and read
out of the FIFO in small word (x18/x9) format. If Big-Endian mode is selected,
then the most significant byte (word) of the long word written into the FIFO will
be read out of the FIFO first, followed by the least significant byte. If Little-Endian
format is selected, then the least significant byte of the long word written into the
FIFO will be read out first, followed by the most significant byte. The mode desired
is configured during master reset by the state of the Big-Endian (BE) pin. See
Figure 5 for Bus-Matching Byte Arrangement.
The Interspersed/Non-Interspersed Parity (IP) bit function allows the user
to select the parity bit in the word loaded into the parallel port (D0-Dn) when
programming the flag offsets. If Interspersed Parity mode is selected, then the
FIFO will assume that the parity bit is located in bit positions D8, D17, D26 and
D35 during the parallel programming of the flag offsets. If Non-Interspersed
Parity mode is selected, then D8, D17 and D26 are assumed to be valid bits
and D32, D33, D34 and D35 are ignored. IP mode is selected during Master
Reset by the state of the IP input pin.
If, at any time, the FIFO is not actively performing an operation, the chip will
automatically power down. Once in the power down state, the standby supply
current consumption is minimized. Initiating any operation (by activating control
inputs) will immediately take the device out of the power down state.
Both an Asynchronous Output Enable pin (OE) and Synchronous Read
Chip Select pin (RCS) are provided on the FIFO. The Synchronous Read Chip
Select is synchronized to the RCLK. Both the output enable and read chip select
control the output buffer of the FIFO, causing the buffer to be either HIGH
impedance or LOW impedance.
A JTAG test port is provided, here the FIFO has fully functional Boundary
Scan feature, compliant with IEEE 1449.1 Standard Test Access Port and
Boundary Scan Architecture.
The TeraSync FIFO has the capability of operating its ports (write and/or
read) in either LVTTL or HSTL mode, each ports selection independent of the
other. The write port selection is made via WHSTL and the read port selection
via RHSTL. An additional input SHSTL is also provided, this allows the user
to select HSTL operation for other pins on the device (not associated with the
write or read ports).
The IDT72T36105/72T36115/72T36125 are fabricated using IDT’s high
speed submicron CMOS technology.
5
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T36105/72T36115/72T36125 2.5V TeraSync 36-BIT FIFO
65,536 x 36, 131,072 x 36, 262,144 x 36
BM IW OW Write Port Width Read Port Width
L L L x36 x36
H L L x36 x18
H L H x36 x9
H H L x18 x36
H H H x9 x36
TABLE 1  BUS-MATCHING CONFIGURATION MODES
NOTE:
1. Pin status during Master Reset.
Figure 1. Single Device Configuration Signal Flow Diagram
(x36, x18, x9) DATA OUT (Q
0
- Q
n
)(x36, x18, x9) DATA IN (D
0
- D
n
)
MASTER RESET (MRS)
READ CLOCK (RCLK/RD)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
EMPTY FLAG/OUTPUT READY (EF/OR)
PROGRAMMABLE ALMOST-EMPTY (PAE)
WRITE CLOCK (WCLK/WR)
WRITE ENABLE (WEN)
LOAD (LD)
FULL FLAG/INPUT READY (FF/IR)
PROGRAMMABLE ALMOST-FULL (PAF)
IDT
72T36105
72T36115
72T36125
PARTIAL RESET (PRS)
FIRST WORD FALL THROUGH/
SERIAL INPUT (FWFT/SI) RETRANSMIT (RT)
5993 drw03
HALF-FULL FLAG (HF)
SERIAL ENABLE(SEN)
INPUT WIDTH (IW) OUTPUT WIDTH (OW)
BIG-ENDIAN/LITTLE-ENDIAN (BE)
INTERSPERSED/
NON-INTERSPERSED PARITY (IP)
BUS-
MATCHING
(BM)
SERIAL CLOCK (SCLK)
MARK
READ CHIP SELECT (RCS)
RCLK ECHO, ERCLK
REN ECHO, EREN
WRITE CHIP SELECT (WCS)
6
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T36105/72T36115/72T36125 2.5V TeraSync 36-BIT FIFO
65,536 x 36, 131,072 x 36, 262,144 x 36
PIN DESCRIPTION
Symbol Name I/O TYPE Description
ASYR(1) Asynchronous LVTTL A HIGH on this input during Master Reset will select Synchronous read operation for the output port. A LOW
Read Port INPUT will select Asynchronous operation. If Asynchronous is selected the FIFO must operate in IDT Standard mode.
ASYW(1) Asynchronous LVTTL A HIGH on this input during Master Reset will select Synchronous write operation for the input port. A LOW
Write Port INPUT will select Asynchronous operation.
BE(1) Big-Endian/ LVTTL During Master Reset, a LOW on BE will select Big-Endian operation. A HIGH on BE during Master Reset
Little-Endian INPUT will select Little-Endian format.
BM(1) Bus-Matching LVTTL BM works with IW and OW to select the bus sizes for both write and read ports. See Table 1 for bus size
INPUT configuration.
D0–D35 Data Inputs HSTL-LVTTL Data inputs for a 36-, 18- or 9-bit bus. When in 18- or 9-bit mode, the unused input pins are in a don’t care
INPUT state.
EF/OR Empty Flag/ HSTL-LVTTL In the IDT Standard mode, the EF function is selected. EF indicates whether or not the FIFO memory is empty.
Output Ready OUTPUT In FWFT mode, the OR function is selected. OR indicates whether or not there is valid data available at the
outputs.
ERCLK RCLK Echo HSTL-LVTTL Read clock Echo output, only available when the Read is setup for Synchronous mode.
OUTPUT
EREN Read Enable Echo HSTL-LVTTL Read Enable Echo output, only available when the Read is setup for Synchronous mode.
OUTPUT
FF/IR Full Flag/ HSTL-LVTTL In the IDT Standard mode, the FF function is selected. FF indicates whether or not the FIFO memory is
Input Ready OUTPUT full. In the FWFT mode, the IR function is selected. IR indicates whether or not there is space available for
writing to the FIFO memory.
FSEL0(1) Flag Select Bit 0 LVTTL During Master Reset, this input along with FSEL1 and the LD pin, will select the default offset values for the
INPUT programmable flags PAE and PAF. There are up to eight possible settings available.
FSEL1(1) Flag Select Bit 1 LVTTL During Master Reset, this input along with FSEL0 and the LD pin will select the default offset values for the
INPUT programmable flags PAE and PAF. There are up to eight possible settings available.
FWFT/ First Word Fall HSTL-LVTTL During Master Reset, selects First Word Fall Through or IDT Standard mode. After Master Reset, this pin
SI Through/Serial In INPUT functions as a serial input for loading offset registers. If Asynchronous operation of the read port has been
selected then the FIFO must be set-up in IDT Standard mode.
HF Half-Full Flag HSTL-LVTTL HF indicates whether the FIFO memory is more or less than half-full.
OUTPUT
IP(1) Interspersed Parity LVTTL During Master Reset, a LOW on IP will select Non-Interspersed Parity mode. A HIGH will select Interspersed
INPUT Parity mode.
IW(1) Input Width LVTTL This pin, along with OW and BM, selects the bus width of the write port. See Table 1 for bus size configuration.
INPUT
LD Load HSTL-LVTTL This is a dual purpose pin. During Master Reset, the state of the LD input along with FSEL0 and FSEL1,
INPUT determines one of eight default offset values for the PAE and PAF flags, along with the method by which these
offset registers can be programmed, parallel or serial (see Table 2). After Master Reset, this pin enables writing
to and reading from the offset registers.
MARK Mark for Retransmit HSTL-LVTTL When this pin is asserted the current location of the read pointer will be marked. Any subsequent Retransmit
INPUT operation will reset the read pointer to this position.
MRS Master Reset HSTL-LVTTL MRS initializes the read and write pointers to zero and sets the output register to all zeroes. During Master
INPUT Reset, the FIFO is configured for either FWFT or IDT Standard mode, Bus-Matching configurations,
Synchronous/Asynchronous operation of the read or write port, one of eight programmable flag default settings,
serial or parallel programming of the offset settings, Big-Endian/Little-Endian format, zero latency timing mode,
interspersed parity, and synchronous versus asynchronous programmable flag timing modes.
OE Output Enable HSTL-LVTTL OE provides Asynchronous three-state control of the data outputs, Qn. During a Master or Partial Reset the
INPUT OE input is the only input that provide High-Impedance control of the data outputs.
OW(1) Output Width LVTTL This pin, along with IW and BM, selects the bus width of the read port. See Table 1 for bus size configuration.
INPUT
PAE Programmable HSTL-LVTTL PAE goes LOW if the number of words in the FIFO memory is less than offset n, which is stored in the Empty
Almost-Empty Flag OUTPUT Offset register. PAE goes HIGH if the number of words in the FIFO memory is greater than or equal to offset n.
PAF Programmable HSTL-LVTTL PAF goes HIGH if the number of free locations in the FIFO memory is more than offset m, which is stored in
Almost-Full Flag OUTPUT the Full Offset register. PAF goes LOW if the number of free locations in the FIFO memory is less than or equal
to m.
NOTE:
1. Inputs should not change state after Master Reset.
7
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T36105/72T36115/72T36125 2.5V TeraSync 36-BIT FIFO
65,536 x 36, 131,072 x 36, 262,144 x 36
Symbol Name I/O TYPE Description
PFM(1) Programmable LVTTL During Master Reset, a LOW on PFM will select Asynchronous Programmable flag timing mode. A HIGH on
Flag Mode INPUT PFM will select Synchronous Programmable flag timing mode.
PRS Partial Reset HSTL-LVTTL PRS initializes the read and write pointers to zero and sets the output register to all zeroes. During Partial Reset,
INPUT the existing mode (IDT or FWFT), programming method (serial or parallel), and programmable flag settings
are all retained.
Q0–Q35 Data Outputs HSTL-LVTTL Data outputs for an 36-, 18- or 9-bit bus. When in 18- or 9-bit mode, any unused output pins should not be
OUTPUT connected. Outputs are not 5V tolerant regardless of the state of OE and RCS.
RCLK/ Read Clock/ HSTL-LVTTL If Synchronous operation of the read port has been selected, when enabled by REN, the rising edge of RCLK
RD Read Stobe INPUT reads data from the FIFO memory and offsets from the programmable registers. If LD is LOW, the values loaded
into the offset registers is output on a rising edge of RCLK.If Asynchronous operation of the read port has been
selected, a rising edge on RD reads data from the FIFO in an Asynchronous manner. REN should be tied LOW.
RCS Read Chip Select HSTL-LVTTL RCS provides synchronous control of the read port and output impedance of Qn, synchronous to RCLK. During
INPUT a Master Reset or Partial Reset the RCS input is don’t care, if OE is LOW the data outputs will be Low-Impedance
regardless of RCS.
REN Read Enable HSTL-LVTTL If Synchronous operation of the read port has been selected, REN enablesRCLK for reading data from the
INPUT FIFO memory and offset registers. If Asynchronous operation of the read port has been selected, the REN
input should be tied LOW.
RHSTL(1) Read Port HSTL LVTTL This pin is used to select HSTL or 2.5v LVTTL outputs for the FIFO. If HSTL inputs are required, this input
Select INPUT must be tied HIGH. Otherwise it should be tied LOW.
RT Retransmit HSTL-LVTTL RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets the EF flag to LOW (OR to HIGH
INPUT in FWFT mode) and doesn’t disturb the write pointer, programming method, existing timing mode orprogrammable
flag settings. If a mark has been set via the MARK input pin, then the read pointer will jump to the ‘mark’ location.
SCLK Serial Clock HSTL-LVTTL A rising edge on SCLK will clock the serial data present on the SI input into the offset registers providing that
INPUT SEN is enabled.
SEN Serial Enable HSTL-LVTTL SEN enables serial loading of programmable flag offsets.
INPUT
SHSTL System HSTL LVTTL All inputs not associated with the write or read port can be selected for HSTL operation via the SHSTL input.
Select INPUT
TCK(2) JTAG Clock HSTL-LVTTL Clock input for JTAG function. TMS and TDI are sampled on the rising edge of TCK. Data is output on
INPUT TDO on the falling edge.
TRST(2) JTAG Reset HSTL-LVTTL TRST is an asynchronous reset pin for the JTAG controller.
INPUT
TMS JTAG Mode HSTL-LVTTL TMS is a serial input pin. Bits are serially loaded on the rising edge of TCK, which selects 1 of 5 modes of
Select INPUT operation for the JTAG boundary scan.
TDI Test Data Input HSTL-LVTTL During JTAG boundary scan operation test data is serially loaded via TDI on the rising edge of TCK.
INPUT This is also the data for the Instruction Register, ID Register and Bypass Register.
TDO Test Data Output HSTL-LVTTL During JTAG boundary scan operation test data is serially output via TDO on the falling edge of TCK.
OUTPUT This output is in High-Z except when shifting, while in SHIFT-DR and SHIFT-IR controller states.
WEN Write Enable HSTL-LVTTL When Synchronous operation of the write port has been selected, WEN enables WCLK for writing data into
INPUT theFIFO memory and offset registers. If Asynchronous operation of the write port has been selected, the
WEN input should be tied LOW.
WCS Write Chip Select HSTL-LVTTL This pin disables the write port data inputs when the device write port is configured for HSTL mode. This
INPUT provides added power savings.
WCLK/ Write Clock/ HSTL-LVTTL If Synchronous operation of the write port has been selected, when enabled by WEN, the rising edge of WCLK
WR Write Strobe INPUT writes data into the FIFO. If Asynchronous operation of the write port has been selected, WR writes data into
the FIFO on a rising edge in an Asynchronous manner, (WEN should be tied to its active state).
WHSTL(1) Write Port HSTL LVTTL This pin is used to select HSTL or 2.5V LVTTL inputs for the FIFO. If HSTL inputs are required, this input must
Select INPUT be tied HIGH. Otherwise it should be tied LOW.
Vcc +2.5v Supply I These are Vcc supply inputs and must be connected to the 2.5V supply rail.
GND Ground Pin I These are Ground pins an dmust be connected to the GND rail.
Vref Reference I This is a Voltage Reference input and must be connected to a voltage level determined from the table,
Voltage “Recommended DC Operating Conditions”. This provides the reference voltage when using HSTL class
inputs. If HSTL class inputs are not being used, this pin should be tied LOW.
VDDQ O/P Rail Voltage I This pin should be tied to the desired voltage rail for providing power to the output drivers.
PIN DESCRIPTION (CONTINUED)
NOTES:
1. Inputs should not change state after Master Reset.
2. If the JTAG feature is not being used, TCK and TRST should be tied LOW.
CORPORATE HEADQUARTERS for SALES: for Tech Support:
2975 Stender Way 800-345-7015 or 408-727-6116 408-330-1753
Santa Clara, CA 95054 fax: 408-492-8674 email: FIFOhelp@idt.com
www.idt.com* BB Pkg: www.idt.com/docs/PSC40__.pdf
*To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2.
The TeraSync FIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
8
ORDERING INFORMATION
Plastic Ball Grid Array (PBGA, BB240-1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Low Power
5993 drw42
Com’l Only
Com’l and Ind’l
Com’l Only
5
6-7
10
IDT XXXXX
Device Type
X
Power
XX
Speed
X
Package
X
Process /
Temperature
Range BLANK
I
72T36105 65,536 x 36 2.5V TeraSync FIFO
72T36115 131,072 x 36 2.5V TeraSync FIFO
72T36125 262,144 x 36 2.5V TeraSync FIFO
Clock Cycle Time (tCLK)
Speed in Nanoseconds
BB
L