2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 36-BIT CONFIGURATIONS 65,536 x 36, 131,072 x 36, 262,144 x 36 FEATURES: * * * * * * * * * * * * * * Choose among the following memory organizations: IDT72T36105 65,536 x 36 IDT72T36115 131,072 x 36 IDT72T36125 262,144 x 36 Up to 200 MHz Operation of Clocks Functionally compatible to the 32,768 x36 TeraSync devices User selectable HSTL/LVTTL Input and/or Output Read Enable & Read Clock Echo outputs aid high speed operation User selectable Asynchronous read and/or write port timing Mark & Retransmit, resets read pointer to user marked position Write Chip Select (WCS) input disables Write Port HSTL inputs Read Chip Select (RCS) synchronous to RCLK Programmable Almost-Empty and Almost-Full flags, each flag can default to one of eight preselected offsets Program programmable flags by either serial or parallel means Selectable synchronous/asynchronous timing modes for AlmostEmpty and Almost-Full flags Separate SCLK input for Serial programming of flag offsets * * * * * * * * * * * * * ADVANCE INFORMATION IDT72T36105 IDT72T36115 IDT72T36125 User selectable input and output port bus-sizing - x36 in to x36 out - x36 in to x18 out - x36 in to x9 out - x18 in to x36 out - x9 in to x36 out Big-Endian/Little-Endian user selectable byte representation Auto power down minimizes standby power consumption Master Reset clears entire FIFO Partial Reset clears data, but retains programmable settings Empty, Full and Half-Full flags signal FIFO status Select IDT Standard timing (using EF and FF flags) or First Word Fall Through timing (using OR and IR flags) Output enable puts data outputs into high impedance state JTAG port, provided for Boundary Scan function Available in 240-pin (19mm x 19mm)Plastic Ball Grid Array (PBGA) Easily expandable in depth and width Independent Read and Write Clocks (permit reading and writing simultaneously) High-performance submicron CMOS technology Industrial temperature range (-40C to +85C) is available FUNCTIONAL BLOCK DIAGRAM D0 -Dn (x36, x18 or x9) LD WEN WCLK/WR SEN SCLK WCS INPUT REGISTER ASYW WRITE CONTROL LOGIC IP BUS CONFIGURATION MRS RESET LOGIC PRS TCK TRST TMS TDO RAM ARRAY 65,536 x 36 131,072 x 36 262,144 x 36 CONTROL LOGIC BM IW OW OUTPUT REGISTER READ POINTER RT MARK ASYR READ CONTROL LOGIC JTAG CONTROL (BOUNDARY SCAN) RCLK/RD REN RCS TDI Vref WHSTL RHSTL SHSTL FF/IR PAF EF/OR PAE HF FWFT/SI PFM FSEL0 FSEL1 FLAG LOGIC WRITE POINTER BE OFFSET REGISTER HSTL I/0 CONTROL EREN OE Q0 -Qn (x36, x18 or x9) The IDT logo is a registered trademark and the TeraSync FIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 1 2001 Integrated Device Technology, Inc. 5993 drw01 ERCLK MAY 2001 DSC-5993/- IDT72T36105/72T36115/72T36125 2.5V TeraSync 36-BIT FIFO 65,536 x 36, 131,072 x 36, 262,144 x 36 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES PIN CONFIGURATION A1 BALL PAD CORNER A V CC V CC V CC V CC V CC V CC WCLK PRS GND FF EREN RCLK OE VDDQ VDDQ VDDQ VDDQ VDDQ V CC V CC V CC V CC V CC V CC WEN MRS GND PAF EF REN RCS VDDQ VDDQ VDDQ VDDQ VDDQ V CC V CC V CC V CC V CC V CC WCS LD GND HF PAE MARK RT VDDQ VDDQ VDDQ VDDQ VDDQ V CC V CC V CC FWFT/SI OW FS0 SHSTL FS1 GND BE IP BM RHSTL ASYR PFM VDDQ VDDQ VDDQ V CC V CC V CC GND GND VDDQ VDDQ VDDQ V CC V CC V CC GND GND VDDQ VDDQ VDDQ V CC SEN SCLK WHSTL GND VDDQ VDDQ VDDQ V CC V CC ASYW GND GND GND GND GND VDDQ VDDQ VDDQ V CC V CC V CC VREF GND GND GND GND GND VDDQ VDDQ VDDQ V CC V CC V CC IW GND GND GND GND GND VDDQ VDDQ VDDQ D33 D34 D35 GND GND GND GND GND GND VDDQ Q35 Q34 D30 D31 D32 GND GND Q33 Q32 Q31 D27 D28 D29 GND GND Q30 Q29 Q28 D24 D25 D26 GND GND Q27 Q26 Q25 D21 D22 D23 GND GND GND GND GND GND GND GND GND GND GND GND Q24 Q23 Q22 D19 D20 D13 D10 D5 D4 D1 TMS TDO GND Q0 Q2 Q3 Q8 Q11 Q14 Q21 Q20 D18 D17 D14 D11 D7 D8 D2 TRST TDI GND Q1 Q6 Q5 Q9 Q12 Q15 Q18 Q19 V CC D16 D15 D12 D9 D6 D3 D0 TCK GND ERCLK Q4 Q7 Q10 Q13 Q16 Q17 VDDQ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 B C D E F G H V CC J K L M N P R T U V 18 5993 drw02 PBGA: 1mm pitch, 19mm x 19mm (BB240-1, order code: BB) TOP VIEW 2 IDT72T36105/72T36115/72T36125 2.5V TeraSync 36-BIT FIFO 65,536 x 36, 131,072 x 36, 262,144 x 36 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES DESCRIPTION: The frequencies of both the RCLK and the WCLK signals may vary from 0 to fMAX with complete independence. There are no restrictions on the frequency of the one clock input with respect to the other. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through (FWFT) mode. In IDT Standard mode, the first word written to an empty FIFO will not appear on the data output lines unless a specific read operation is performed. A read operation, which consists of activating REN and enabling a rising RCLK edge, will shift the word from internal memory to the data output lines. In FWFT mode, the first word written to an empty FIFO is clocked directly to the data output lines after three transitions of the RCLK signal. A REN does not have to be asserted for accessing the first word. However, subsequent words written to the FIFO do require a LOW on REN for access. The state of the FWFT/SI input during Master Reset determines the timing mode in use. For applications requiring more data storage capacity than a single FIFO can provide, the FWFT timing mode permits depth expansion by chaining FIFOs in series (i.e. the data outputs of one FIFO are connected to the corresponding data inputs of the next). No external logic is required. These FIFOs have five flag pins, EF/OR (Empty Flag or Output Ready), FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable Almost-Empty flag) and PAF (Programmable Almost-Full flag). The EF and FF functions are selected in IDT Standard mode. The IR and OR functions are selected in FWFT mode. HF, PAE and PAF are always available for use, irrespective of timing mode. PAE and PAF can be programmed independently to switch at any point in memory. Programmable offsets determine the flag switching threshold and can be loaded by two methods: parallel or serial. Eight default offset settings are also provided, so that PAE can be set to switch at a predefined number of locations from the empty boundary and the PAF threshold can also be set at similar predefined values from the full boundary. The default offset values are set during Master Reset by the state of the FSEL0, FSEL1, and LD pins. For serial programming, SEN together with LD on each rising edge of SCLK, are used to load the offset registers via the Serial Input (SI). For parallel programming, WEN together with LD on each rising edge of WCLK, are used to load the offset registers via Dn. REN together with LD on each rising edge of RCLK can be used to read the offsets in parallel from Qn regardless of whether serial or parallel offset loading has been selected. During Master Reset (MRS) the following events occur: the read and write pointers are set to the first location of the FIFO. The FWFT pin selects IDT Standard mode or FWFT mode. The Partial Reset (PRS) also sets the read and write pointers to the first location of the memory. However, the timing mode, programmable flag programming method, and default or programmed offset settings existing before Partial Reset remain unchanged. The flags are updated according to the timing mode and offsets in effect. PRS is useful for resetting a device in mid-operation, when reprogramming programmable flags would be undesirable. It is also possible to select the timing mode of the PAE (Programmable AlmostEmpty flag) and PAF (Programmable Almost-Full flag) outputs. The timing modes can be set to be either asynchronous or synchronous for the PAE and PAF flags. If asynchronous PAE/PAF configuration is selected, the PAE is asserted LOW on the LOW-to-HIGH transition of RCLK. PAE is reset to HIGH on the LOWto-HIGH transition of WCLK. Similarly, the PAF is asserted LOW on the LOWto-HIGH transition of WCLK and PAF is reset to HIGH on the LOW-to-HIGH transition of RCLK. The IDT72T36105/72T36115/72T36125 are exceptionally deep, extrememly high speed, CMOS First-In-First-Out (FIFO) memories with clocked read and write controls and a flexible Bus-Matching x36/x18/x9 data flow. These FIFOs offer several key user benefits: * Flexible x36/x18/x9 Bus-Matching on both read and write ports * A user selectable MARK location for retransmit * User selectable I/O structure for HSTL or LVTTL * Asynchronous/Synchronous translation on the read or write ports * The first word data latency period, from the time the first word is written to an empty FIFO to the time it can be read, is fixed and short. * High density offerings up to 9 Mbit Bus-Matching TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes. Each FIFO has a data input port (Dn) and a data output port (Qn), both of which can assume either a 36-bit, 18-bit or a 9-bit width as determined by the state of external control pins Input Width (IW), Output Width (OW), and BusMatching (BM) pin during the Master Reset cycle. The input port can be selected as either a Synchronous (clocked) interface, or Asynchronous interface. During Synchronous operation the input port is controlled by a Write Clock (WCLK) input and a Write Enable (WEN) input. Data present on the Dn data inputs is written into the FIFO on every rising edge of WCLK when WEN is asserted. During Asynchronous operation only the WR input is used to write data into the FIFO. Data is written on a rising edge of WR, the WEN input should be tied to its active state, (LOW). The input port can be selected for either 2.5V LVTTL or HSTL operation, this operation is selected by the state of the WHSTL input during a master reset. A Write Chip Select input (WCS) is provided for use when the write port is in HSTL mode. During HSTL operation the WCS input can be used to disable write port inputs (data only). The output port can be selected as either a Synchronous (clocked) interface, or Asynchronous interface. During Synchronous operation the output port is controlled by a Read Clock (RCLK) input and Read Enable (REN) input. Data is read from the FIFO on every rising edge of RCLK when REN is asserted. During Asynchronous operation only the RD input is used to read data from the FIFO. Data is read on a rising edge of RD, the REN input should be tied to its active state, LOW. When Asynchronous operation is selected on the output port the FIFO must be configured for Standard IDT mode, also the RCS should be tied LOW and the OE input used to provide three-state control of the outputs, Qn. The output port can be selected for either 2.5V LVTTL or HSTL operation, this operation is selected by the state of the RHSTL input during a master reset. An Output Enable (OE) input is provided for three-state control of the outputs. A Read Chip Select (RCS) input is also provided, the RCS input is synchronized to the read clock, and also provides three-state control of the Qn data outputs. When RCS is disabled, the data outputs will be high impedance. During Asynchronous operation of the output port, RCS should be enabled, held LOW. Echo Read Enable, EREN and Echo Read Clock, ERCLK outputs are provided. These are outputs from the read port of the FIFO that are required for high speed data communication, to provide tighter synchronization between the data being transmitted from the Qn outputs and the data being received by the input device. Data read from the read port is available on the output bus with respect to EREN and ERCLK, this is very useful when data is being read at high speed. The ERCLK and EREN outputs are non-functional when the Read port is setup for Asynchronous mode. 3 IDT72T36105/72T36115/72T36125 2.5V TeraSync 36-BIT FIFO 65,536 x 36, 131,072 x 36, 262,144 x 36 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES DESCRIPTION (CONTINUED) FIFO will assume that the parity bit is located in bit positions D8, D17, D26 and D35 during the parallel programming of the flag offsets. If Non-Interspersed Parity mode is selected, then D8, D17 and D26 are assumed to be valid bits and D32, D33, D34 and D35 are ignored. IP mode is selected during Master Reset by the state of the IP input pin. If, at any time, the FIFO is not actively performing an operation, the chip will automatically power down. Once in the power down state, the standby supply current consumption is minimized. Initiating any operation (by activating control inputs) will immediately take the device out of the power down state. Both an Asynchronous Output Enable pin (OE) and Synchronous Read Chip Select pin (RCS) are provided on the FIFO. The Synchronous Read Chip Select is synchronized to the RCLK. Both the output enable and read chip select control the output buffer of the FIFO, causing the buffer to be either HIGH impedance or LOW impedance. A JTAG test port is provided, here the FIFO has fully functional Boundary Scan feature, compliant with IEEE 1449.1 Standard Test Access Port and Boundary Scan Architecture. The TeraSync FIFO has the capability of operating its ports (write and/or read) in either LVTTL or HSTL mode, each ports selection independent of the other. The write port selection is made via WHSTL and the read port selection via RHSTL. An additional input SHSTL is also provided, this allows the user to select HSTL operation for other pins on the device (not associated with the write or read ports). The IDT72T36105/72T36115/72T36125 are fabricated using IDT's high speed submicron CMOS technology. If synchronous PAE/PAF configuration is selected , the PAE is asserted and updated on the rising edge of RCLK only and not WCLK. Similarly, PAF is asserted and updated on the rising edge of WCLK only and not RCLK. The mode desired is configured during MasterReset by the state of the Programmable Flag Mode (PFM) pin. This device includes a Retransmit from Mark feature that utilizes two control inputs, MARK and , RT (Retransmit). If the MARK input is enabled with respect to the RCLK, the memory location being read at that point will be marked. Any subsequent retransmit operation, RT goes LOW, will reset the read pointer to this `marked' location. The device can be configured with different input and output bus widths as shown in Table 1. A Big-Endian/Little-Endian data word format is provided. This function is useful when data is written into the FIFO in long word format (x36/x18) and read out of the FIFO in small word (x18/x9) format. If Big-Endian mode is selected, then the most significant byte (word) of the long word written into the FIFO will be read out of the FIFO first, followed by the least significant byte. If Little-Endian format is selected, then the least significant byte of the long word written into the FIFO will be read out first, followed by the most significant byte. The mode desired is configured during master reset by the state of the Big-Endian (BE) pin. See Figure 5 for Bus-Matching Byte Arrangement. The Interspersed/Non-Interspersed Parity (IP) bit function allows the user to select the parity bit in the word loaded into the parallel port (D0-Dn) when programming the flag offsets. If Interspersed Parity mode is selected, then the 4 IDT72T36105/72T36115/72T36125 2.5V TeraSync 36-BIT FIFO 65,536 x 36, 131,072 x 36, 262,144 x 36 PARTIAL RESET (PRS) COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES MASTER RESET (MRS) WRITE CLOCK (WCLK/WR) READ CLOCK (RCLK/RD) WRITE ENABLE (WEN) READ ENABLE (REN) WRITE CHIP SELECT (WCS) OUTPUT ENABLE (OE) LOAD (LD) READ CHIP SELECT (RCS) (x36, x18, x9) DATA IN (D0 - Dn) IDT 72T36105 72T36115 72T36125 SERIAL CLOCK (SCLK) SERIAL ENABLE(SEN) FIRST WORD FALL THROUGH/ SERIAL INPUT (FWFT/SI) (x36, x18, x9) DATA OUT (Q0 - Qn) RCLK ECHO, ERCLK REN ECHO, EREN MARK RETRANSMIT (RT) EMPTY FLAG/OUTPUT READY (EF/OR) PROGRAMMABLE ALMOST-EMPTY (PAE) FULL FLAG/INPUT READY (FF/IR) PROGRAMMABLE ALMOST-FULL (PAF) HALF-FULL FLAG (HF) BIG-ENDIAN/LITTLE-ENDIAN (BE) INTERSPERSED/ NON-INTERSPERSED PARITY (IP) 5993 drw03 OUTPUT WIDTH (OW) BUSMATCHING (BM) INPUT WIDTH (IW) Figure 1. Single Device Configuration Signal Flow Diagram TABLE 1 BUS-MATCHING CONFIGURATION MODES BM IW OW Write Port Width Read Port Width L L L x36 x36 H L L x36 x18 H L H x36 x9 H H L x18 x36 H H H x9 x36 NOTE: 1. Pin status during Master Reset. 5 IDT72T36105/72T36115/72T36125 2.5V TeraSync 36-BIT FIFO 65,536 x 36, 131,072 x 36, 262,144 x 36 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES PIN DESCRIPTION Symbol Name (1) ASYR Asynchronous Read Port (1) ASYW Asynchronous Write Port (1) BE Big-Endian/ Little-Endian BM(1) Bus-Matching D0-D35 Data Inputs EF/OR Empty Flag/ Output Ready ERCLK RCLK Echo EREN Read Enable Echo FF/IR Full Flag/ Input Ready FSEL0(1) Flag Select Bit 0 FSEL1(1) Flag Select Bit 1 FWFT/ SI First Word Fall Through/Serial In HF Half-Full Flag IP(1) Interspersed Parity IW(1) Input Width LD Load MARK Mark for Retransmit MRS Master Reset OE Output Enable OW(1) Output Width PAE Programmable Almost-Empty Flag Programmable Almost-Full Flag PAF I/O TYPE LVTTL INPUT LVTTL INPUT LVTTL INPUT LVTTL INPUT HSTL-LVTTL INPUT HSTL-LVTTL OUTPUT Description A HIGH on this input during Master Reset will select Synchronous read operation for the output port. A LOW will select Asynchronous operation. If Asynchronous is selected the FIFO must operate in IDT Standard mode. A HIGH on this input during Master Reset will select Synchronous write operation for the input port. A LOW will select Asynchronous operation. During Master Reset, a LOW on BE will select Big-Endian operation. A HIGH on BE during Master Reset will select Little-Endian format. BM works with IW and OW to select the bus sizes for both write and read ports. See Table 1 for bus size configuration. Data inputs for a 36-, 18- or 9-bit bus. When in 18- or 9-bit mode, the unused input pins are in a don't care state. In the IDT Standard mode, the EF function is selected. EF indicates whether or not the FIFO memory is empty. In FWFT mode, the OR function is selected. OR indicates whether or not there is valid data available at the outputs. HSTL-LVTTL Read clock Echo output, only available when the Read is setup for Synchronous mode. OUTPUT HSTL-LVTTL Read Enable Echo output, only available when the Read is setup for Synchronous mode. OUTPUT HSTL-LVTTL In the IDT Standard mode, the FF function is selected. FF indicates whether or not the FIFO memory is OUTPUT full. In the FWFT mode, the IR function is selected. IR indicates whether or not there is space available for writing to the FIFO memory. LVTTL During Master Reset, this input along with FSEL1 and the LD pin, will select the default offset values for the INPUT programmable flags PAE and PAF. There are up to eight possible settings available. LVTTL During Master Reset, this input along with FSEL0 and the LD pin will select the default offset values for the INPUT programmable flags PAE and PAF. There are up to eight possible settings available. HSTL-LVTTL During Master Reset, selects First Word Fall Through or IDT Standard mode. After Master Reset, this pin INPUT functions as a serial input for loading offset registers. If Asynchronous operation of the read port has been selected then the FIFO must be set-up in IDT Standard mode. HSTL-LVTTL HF indicates whether the FIFO memory is more or less than half-full. OUTPUT LVTTL During Master Reset, a LOW on IP will select Non-Interspersed Parity mode. A HIGH will select Interspersed INPUT Parity mode. LVTTL This pin, along with OW and BM, selects the bus width of the write port. See Table 1 for bus size configuration. INPUT HSTL-LVTTL This is a dual purpose pin. During Master Reset, the state of the LD input along with FSEL0 and FSEL1, INPUT determines one of eight default offset values for the PAE and PAF flags, along with the method by which these offset registers can be programmed, parallel or serial (see Table 2). After Master Reset, this pin enables writing to and reading from the offset registers. HSTL-LVTTL When this pin is asserted the current location of the read pointer will be marked. Any subsequent Retransmit INPUT operation will reset the read pointer to this position. HSTL-LVTTL MRS initializes the read and write pointers to zero and sets the output register to all zeroes. During Master INPUT Reset, the FIFO is configured for either FWFT or IDT Standard mode, Bus-Matching configurations, Synchronous/Asynchronous operation of the read or write port, one of eight programmable flag default settings, serial or parallel programming of the offset settings, Big-Endian/Little-Endian format, zero latency timing mode, interspersed parity, and synchronous versus asynchronous programmable flag timing modes. HSTL-LVTTL OE provides Asynchronous three-state control of the data outputs, Qn. During a Master or Partial Reset the INPUT OE input is the only input that provide High-Impedance control of the data outputs. LVTTL This pin, along with IW and BM, selects the bus width of the read port. See Table 1 for bus size configuration. INPUT HSTL-LVTTL PAE goes LOW if the number of words in the FIFO memory is less than offset n, which is stored in the Empty OUTPUT Offset register. PAE goes HIGH if the number of words in the FIFO memory is greater than or equal to offset n. HSTL-LVTTL PAF goes HIGH if the number of free locations in the FIFO memory is more than offset m, which is stored in OUTPUT the Full Offset register. PAF goes LOW if the number of free locations in the FIFO memory is less than or equal to m. NOTE: 1. Inputs should not change state after Master Reset. 6 IDT72T36105/72T36115/72T36125 2.5V TeraSync 36-BIT FIFO 65,536 x 36, 131,072 x 36, 262,144 x 36 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES PIN DESCRIPTION (CONTINUED) Symbol Name PFM(1) Programmable Flag Mode PRS Partial Reset I/O TYPE LVTTL INPUT HSTL-LVTTL INPUT Q0-Q35 Data Outputs RCLK/ RD Read Clock/ Read Stobe HSTL-LVTTL OUTPUT HSTL-LVTTL INPUT RCS Read Chip Select HSTL-LVTTL INPUT REN Read Enable HSTL-LVTTL INPUT LVTTL RHSTL(1) Read Port HSTL Select INPUT RT Retransmit HSTL-LVTTL INPUT SCLK SEN SHSTL TCK(2) TRST(2) TMS TDI TDO WEN WCS WCLK/ WR WHSTL(1) Vcc GND Vref VDDQ Serial Clock HSTL-LVTTL INPUT Serial Enable HSTL-LVTTL INPUT System HSTL LVTTL Select INPUT JTAG Clock HSTL-LVTTL INPUT JTAG Reset HSTL-LVTTL INPUT JTAG Mode HSTL-LVTTL Select INPUT Test Data Input HSTL-LVTTL INPUT Test Data Output HSTL-LVTTL OUTPUT Write Enable HSTL-LVTTL INPUT Description During Master Reset, a LOW on PFM will select Asynchronous Programmable flag timing mode. A HIGH on PFM will select Synchronous Programmable flag timing mode. PRS initializes the read and write pointers to zero and sets the output register to all zeroes. During Partial Reset, the existing mode (IDT or FWFT), programming method (serial or parallel), and programmable flag settings are all retained. Data outputs for an 36-, 18- or 9-bit bus. When in 18- or 9-bit mode, any unused output pins should not be connected. Outputs are not 5V tolerant regardless of the state of OE and RCS. If Synchronous operation of the read port has been selected, when enabled by REN, the rising edge of RCLK reads data from the FIFO memory and offsets from the programmable registers. If LD is LOW, the values loaded into the offset registers is output on a rising edge of RCLK.If Asynchronous operation of the read port has been selected, a rising edge on RD reads data from the FIFO in an Asynchronous manner. REN should be tied LOW. RCS provides synchronous control of the read port and output impedance of Qn, synchronous to RCLK. During a Master Reset or Partial Reset the RCS input is don't care, if OE is LOW the data outputs will be Low-Impedance regardless of RCS. If Synchronous operation of the read port has been selected, REN enablesRCLK for reading data from the FIFO memory and offset registers. If Asynchronous operation of the read port has been selected, the REN input should be tied LOW. This pin is used to select HSTL or 2.5v LVTTL outputs for the FIFO. If HSTL inputs are required, this input must be tied HIGH. Otherwise it should be tied LOW. RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets the EF flag to LOW (OR to HIGH in FWFT mode) and doesn't disturb the write pointer, programming method, existing timing mode orprogrammable flag settings. If a mark has been set via the MARK input pin, then the read pointer will jump to the `mark' location. A rising edge on SCLK will clock the serial data present on the SI input into the offset registers providing that SEN is enabled. SEN enables serial loading of programmable flag offsets. All inputs not associated with the write or read port can be selected for HSTL operation via the SHSTL input. Clock input for JTAG function. TMS and TDI are sampled on the rising edge of TCK. Data is output on TDO on the falling edge. TRST is an asynchronous reset pin for the JTAG controller. TMS is a serial input pin. Bits are serially loaded on the rising edge of TCK, which selects 1 of 5 modes of operation for the JTAG boundary scan. During JTAG boundary scan operation test data is serially loaded via TDI on the rising edge of TCK. This is also the data for the Instruction Register, ID Register and Bypass Register. During JTAG boundary scan operation test data is serially output via TDO on the falling edge of TCK. This output is in High-Z except when shifting, while in SHIFT-DR and SHIFT-IR controller states. When Synchronous operation of the write port has been selected, WEN enables WCLK for writing data into theFIFO memory and offset registers. If Asynchronous operation of the write port has been selected, the WEN input should be tied LOW. Write Chip Select HSTL-LVTTL This pin disables the write port data inputs when the device write port is configured for HSTL mode. This INPUT provides added power savings. Write Clock/ HSTL-LVTTL If Synchronous operation of the write port has been selected, when enabled by WEN, the rising edge of WCLK Write Strobe INPUT writes data into the FIFO. If Asynchronous operation of the write port has been selected, WR writes data into the FIFO on a rising edge in an Asynchronous manner, (WEN should be tied to its active state). Write Port HSTL LVTTL This pin is used to select HSTL or 2.5V LVTTL inputs for the FIFO. If HSTL inputs are required, this input must Select INPUT be tied HIGH. Otherwise it should be tied LOW. +2.5v Supply I These are Vcc supply inputs and must be connected to the 2.5V supply rail. Ground Pin I These are Ground pins an dmust be connected to the GND rail. Reference I This is a Voltage Reference input and must be connected to a voltage level determined from the table, Voltage "Recommended DC Operating Conditions". This provides the reference voltage when using HSTL class inputs. If HSTL class inputs are not being used, this pin should be tied LOW. O/P Rail Voltage I This pin should be tied to the desired voltage rail for providing power to the output drivers. NOTES: 1. Inputs should not change state after Master Reset. 2. If the JTAG feature is not being used, TCK and TRST should be tied LOW. 7 ORDERING INFORMATION IDT XXXXX X XX X Device Type Power Speed Package X Process / Temperature Range BLANK I Commercial (0C to +70C) Industrial (-40C to +85C) BB Plastic Ball Grid Array (PBGA, BB240-1) 5 6-7 10 Com'l Only Com'l and Ind'l Com'l Only L Low Power 72T36105 72T36115 72T36125 Clock Cycle Time (tCLK) Speed in Nanoseconds 65,536 x 36 2.5V TeraSync FIFO 131,072 x 36 2.5V TeraSync FIFO 262,144 x 36 2.5V TeraSync FIFO 5993 drw42 CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com* for Tech Support: 408-330-1753 email: FIFOhelp@idt.com BB Pkg: www.idt.com/docs/PSC40__.pdf *To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2. The TeraSync FIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc. 8