© Semiconductor Components Industries, LLC, 2014
April, 2014 − Rev. 2 1Publication Order Number:
NCP1592/D
NCP1592
3 V to 6 V Input, 6 A Output
Synchronous Buck PWM
Switcher with Integrated
FETs
NCP1592 is a low input voltage 6 A synchronous buck converter
that integrates both 30 mW high side and low side MOSFETs.
NCP1592 is designed for space sensitive and high efficiency
applications. The main features include: a high performance voltage
error amplifier; an under−voltage−lockout circuit to prevent start−up
until the input voltage reaches 3 V; an internally or externally
programmable soft−start circuit to limit inrush currents; and a power
good output monitor signal. NCP1592 is available in thermally
enhanced 28−pin TSSOP package.
Features
•30 mW, 12 A Peak MOSFET Switches for High to Efficiency at 6 A
Continuous Output Source or Sink Current
•Adjustable Output Voltage Down to 0.891 V With 1.0% Accuracy
•Wide PWM Frequency: Fixed 350 kHz, 550 kHz or Adjustable
280 kHz to 700 kHz
•Synchronizable to 700 kHz
•Load Protected by Peak Current Limit and Thermal Shutdown
•Integrated Solution Reduces Board Area and Component Count
•This is a Pb−Free Device
Application
•Low−Voltage, High−Density Distributed Power Systems
•High Performance Point of Load Regulation for DSPs, FPGAs,
ASICs and Microprocessors
• Broadband, Networking and Optical Communications Infrastructure
•Portable Computing/Notebook PCs
PH
AGND
VBIAS
VIN
BOOT
PGND
VSENSE
COMP
Input Output
NCP1592
Figure 2. Typical Application Circuit
MARKING
DIAGRAM
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TSSOP−28 EP
CASE 948BG
See detailed ordering and shipping information in the package
dimensions section on page 18 of this data sheet.
ORDERING INFORMATION
Figure 1. Efficiency at 350 kHz
LOAD CURRENT (A)
EFFICIENCY
1592G
ALYW
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
VI = 5 V,
VO = 3.3 V
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BLOCK DIAGRAM
VIN
−
+
1.2 V
Falling
Edge
Deglitch
Hysteresis 30 mV
Enable
Comparator
−
+
Hysteresis 160 mV
VIN UVLO
Comparator
2.95 V
VIN Falling
and
Rising
Edge
Deglitch
Thermal
Shutdown
150C
Reference
Vref = 0.891V
_
+−
+
OSC
Adaptive Dead−Time
and
Control Logic
−
+
Hysteresis 30 mV
Powergood
Comparator
0.9*Vref
VSENSE
SHUTDOWN
Falling
Edge
Deglitch
VIN
−
+
PH
Leading
Edge
Blanking
REG
VBIAS
VBIAS
ILIM
Comparator
AGND
SHUTDOWN
SS/ENA
Error
Amplifier
Vo
PWRGD
PGND
PH
BOOT
VIN 3V − 6V
VSENSE COMP RT SYNC
Figure 3. Typical Application Circuit
35 ms
100 ns
2.5 ms
2.5 ms
Internal/External
Slow−start
(Internal Slow−Start Time = 3.35 ms)
30 mW
30 mW
5 mA
R
SQ
PWM
Comparator
NCP1592
SS_DIS
LOUT
CO
SHUTDOWN
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Figure 4. Pin Connections
AGND
VSENSE
RT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
COMP
PWRGD
BOOT
PH
PH
PH
PH
PH
PH
PH
PH
PH
SYNC
SS/ENA
VBIAS
VIN
VIN
VIN
VIN
VIN
PGND
PGND
PGND
PGND
PGND
Thermal
PAD
(Top View)
PIN DESCRIPTION
Pin No. Symbol Description
1 AGND Analog ground. Return for compensation network/output divider, slow−start capacitor. VBIAS capacitor, RT
resistor, and SYNC pin. Connect PowerPAD to AGND.
2 VSENSE Error amplifier inverting input. Connect to output voltage through compensation network/output divider.
3 COMP Error amplifier output. Connect frequency compensation network from COMP to VSENSE.
4 PWRGD Power good open drain output. High when VSENSE ≥ 90% V ref otherwise PWRGD is low. Note that output is
low when SS/ENA is low or the internal shutdown signal is active.
5 BOOT Bootstrap output. 0.022 mF ~ 0.1 mF ceramic capacitor is recommended to connect between BOOT and PH
generates floating drive for the high−side FET drive.
6 ~ 14 PH Phase output. Junction of the internal high−side and low−side power MOSFETs, and output inductor.
15 ~ 19 PGND Power ground. High current return for the low−side driver and power MOSFET. Connect PGND with large
copper areas to the input and output supply returns, and negative terminals of the input and output capacitors.
A single point connection to AGND is recommended.
20 ~ 24 VIN Input supply for the power MOSFET switches and internal bias regulator . Bypass VIN pins to PGND with X5R
or higher quality 10 mF ceramic capacitors.
25 VBIAS Internal bias voltage output. 0.1 mF ~ 1.0 mF low ESR ceramic capacitor is recommended to connect between
VBIAS to AGND.
26 SS/ENA Soft start/enable input/output. Dual function pin which provides logic input to enable/disable device operation
and capacitor input to externally set the start−up time.
27 SYNC Synchronization input. Dual function pin which provides logic input to synchronize to an external oscillator or
pin select between two internally set switching frequencies. When used to synchronize to an external signal, a
resistor must be connected to the RT pin.
28 RT Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency. When
using the SYNC pin, set the RT value for a frequency at or slightly lower than the external oscillator frequency.
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MAXIMUM RATINGS Over operating free−air temperature range unless otherwise noted
Rating Symbol Min Max Unit
Main supply voltage input VIN −0.3 7 V
Soft start and enable voltage SS / ENA −0.3 7 V
Synchronization voltage SYNC −0.3 7 V
Frequency setting voltage RT −0.3 6 V
Output divided voltage sense VSENSE −0.3 4 V
High side drive supply voltage BOOT −0.3 PH+7 V
Output voltage range VBIAS −0.3 7 V
Compensation Voltage COMP −0.3 7 V
Power Good open collector voltage PWRGD −0.3 7 V
Power Switching Node Transient voltage excursion PH
(Note 4) −3 10 V
Power Switching Node Source current PH Internally Limited A
Compensation Source current COMP 0 6 mA
Regulated voltage Source current VBIAS 0 6 mA
Power Switching node sink current PH 0 12 A
Compensation Sink current COMP 0 6 mA
Soft start and enable Sink current SS/ENA 0 10 mA
Power Good open collector Sink current PWRGD 0 10 mA
Voltage differential AGND to
PGND −0.3 0.3 V
Operating Junction Temperature Range (Note 1) TJ−40 150 °C
Operating Ambient Temperature Range TA−40 85 °C
Storage Temperature Range Tstg −55 150 °C
Thermal Characteristics (Note 2)
TSSOP 28−pin EP Plastic Package
Maximum Power Dissipation @ TA = 25°C
Thermal Resistance Junction−to−Air with Solder
Thermal Resistance Junction−to−Air without Solder
PD
RqJA
RqJA
5.49
18.2
40.5
W
°C/W
°C/W
Lead Temperature Soldering (10 sec):
Reflow (SMD styles only) Pb−Free (Note 3) RF 260 peak °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. 1: The maximum package power dissipation limit must not be exceeded.
PD+
TJ(max) *TA
RqJA
2. The value of qJA is measured with the device mounted on a 3in x 3in, 4 layer, 0.062 inch FR−4 board with 1.5 oz. copper on the top and
bottom layers and 0.5 ounce copper on the inner layers, in a still air environment with TA = 25°C. The PCB part layout had 12 thermal vias
(see Recommended Land Pattern in applications section of this data sheet
3. 60−180 seconds minimum above 237°C.
4. 10 V transients allowed for , 10 ns.
RECOMMENDED OPERATING CONDITIONS
Rating Symbol Min Typ Max Unit
Input voltage VI3 6 V
Operating junction temperature TJ–40 125 °C
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ELECTRICAL CHARACTERISTICS Over operating free−air temperature range unless otherwise noted
Parameter Symbol Test Conditions Min Typ MAX Unit
Power Supply, VIN
VIN Operation Voltage VIN 3 6 V
Quiescent Current I(QSW 350) Fs = 350 kHz, SYNC ≤ 0.8 V, RT
open, PH pin open 3.5 11.2 mA
I(QSW 550) Fs = 550 kHz, SYNC ≥ 2.5 V, RT
open, PH pin open 4.0 16 mA
I(QSD) Shutdown, SS / ENA = 0 V 1 1.4 mA
UNDERVOLTAGE LOCKOUT
Start Threshold UVLOR 2.95 3.0 V
Stop Threshold UVLOF 2.7 2.8 V
UVLO Hysteresis UVLOHYST 110 160 mV
Rising and falling edge deglitch
(Note 5) UVLORTD 2.5 ms
BIAS VOLTAGE
Output Voltage Vbias IVbias = 0 2.7 2.8 2.90 V
Output Current (Note 6) IVbias 100 mA
CUMULATIVE REFERENCE
Reference Voltage Accuracy Vref 0.882 0.891 0.900 V
REGULATION
Line regulation (Notes 6 and 7) IL = 3 A, Fs = 350 kHz, TJ = 85°C 0.04 %/V
IL = 3 A, Fs = 550 kHz, TJ = 85°C 0.04
Load regulation (Notes 5 and 7) IL = 0 A to 6 A, Fs = 350 kHz,
TJ = 85°C0.03 %/A
IL = 0 A to 6 A, fs = 550 kHz,
TJ = 85°C0.03
OSCILLATOR
Internally set FREQSYNC_LOW SYNC ≤ 0.8 V, RT open 280 350 420 kHz
FREQ_HIGH SYNC ≥ 2.5 V, RT open 440 550 660
Externally set FREQ180RT RT = 180 kW (1% resistor to
AGND) (Note 5) 252 280 308 kHz
FREQ100RT RT = 100 kW (1% resistor to
AGND) 460 500 540
FREQ68RT RT = 68 kW (1% resistor to
AGND) (Note 5) 663 700 762
High level threshold SYNCH 2.5 V
Low level threshold SYNCL 0.8 V
External synchronization pulse
duration (Note 5) SYNCMIN 50 ns
Frequency range (Note 5) SYNCFREQ 330 700 kHz
Ramp valley (Note 5) RAMP_Bot 0.441 V
Peak−to−peak ramp amplitude
(Note 5) RAMP_AMP 1 V
Minimum controllable on time
(Note 5) MIN_COT 200 ns
Maximum duty cycle DMAX 90%
5. Guaranteed by design.
6. Static resistive loads only.
7. Specified by the circuit used in Figure 14.
8. Matched MOSFETs low−side RDS(on) production tested, high−side RDS(on) specified by design.
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ELECTRICAL CHARACTERISTICS Over operating free−air temperature range unless otherwise noted
Parameter UnitMAXTypMinTest ConditionsSymbol
ERROR AMPLIFIER
Open loop voltage gain OLG 1 kW COMP to AGND (Note 5) 90 110 dB
Unity gain bandwidth UGBW Parallel 10 kW, 160 pF COMP to
AGND (Note 5) 3 5 MHz
Common mode input voltage
range CMIVR Powered by internal LDO
(Note 5) 0 VBIAS V
Input bias current IVSENSE VSENSE = Vref 60 250 nA
Output voltage slew rate
(Positives) EASRP 3.0 4.5 V/ms
Output voltage slew rate
(Negatives) EASRN 2.07 3.0 V/ms
PWM COMPARATOR
PWM comparator propagation
delay time, PWM comparator
input to PH pin (excluding
deadtime)
COMPDLY 10 mV overdrive (Note 5) 70 85 ns
SLOW−START/ENABLE
Enable threshold voltage ENTH 0.82 1.20 1.40 V
Enable hysteresis voltage ENHYS 0.03 V
Falling edge deglitch (Note 5) EN_DLY 2.5 ms
Internal soft−start time SSI 2.18 3.35 4.1 ms
Charge current EN_ICH SS/ENA = 0 V 3 5 8 mA
Discharge current EN_IDSCH SS/ENA = 1.2 V, VI = 2.7 V 2.3 3.1 5.4 mA
POWER GOOD
Power good threshold voltage VSENSE falling 90 %Vref
Power good hysteresis voltage
(Note 5) 3 %Vref
Power good falling edge deglitch
(Note 5) 39 ms
Output saturation voltage PWRGD I(sink) = 2.5 mA 166 225 mV
Leakage current PWRGD VI = 5.5 V 3mA
CURRENT LIMIT
Current limit trip point VI = 3 V, output shorted (Note 5) 7.2 10 A
VI = 6 V, Output shorted (Note 5) 10 12
Current limit leading edge
blanking time (Note 5) 100 ns
Current limit total response time
(Note 5) 200 ns
THERMAL SHUTDOWN
Thermal shutdown trip point
(Note 5) 135 150 165
°C
Hysteresis (Note 5) 10
OUTPUT POWER MOSFETs
Power MOSFETs RDS(on) High
Side VI = 6 V (Note 8) 26 47 mW
VI = 3 V (Note 8) 30 61 mW
5. Guaranteed by design.
6. Static resistive loads only.
7. Specified by the circuit used in Figure 14.
8. Matched MOSFETs low−side RDS(on) production tested, high−side RDS(on) specified by design.
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TYPICAL CHARACTERISTICS
Figure 5. Drain−Source ON−State Resistance
vs Junction Temperature Figure 6. Drain−Source ON−State Resistance
vs Junction Temperature
Figure 7. Internally Set Oscillator Frequency
vs Junction Temperature Figure 8. Externally Set Oscillator Frequency
vs Junction Temperature
Figure 9. Voltage Reference vs Junction
Temperature Figure 10. Device Power Losses at TJ = 1255C
vs Load Current
TJ, JUNCTION TEMPERATURE (°C)
36
−40 125−25 −10 5 1109520 35
DRAIN SOURCE ON−STATE
RESISTANCE (mW)
TJ, JUNCTION TEMPERATURE (°C)
32
DRAIN SOURCE ON−STATE
RESISTANCE (mW)
TJ, JUNCTION TEMPERATURE (°C)
750
INTERNALLY SET OSCILLATOR FREQUENCY (kHz)
650
550
450
350
250
SYNC ≥ 2.5 V
SYNC ≤ 0.8 V
800
EXTERNALLY SET OSCILLATOR
FREQUENCY (kHz)
700
600
500
400
300
200
RT = 100 kW
RT = 68 kW
RT = 180 kW
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
−40
Vref−VOLTAGE REFERENCE (mV)
125−25 −10 5 20 35 50 110958065
895
893
891
889
887
885
TJ, JUNCTION TEMPERATURE (°C)
01 8723 654
DEVICE POWER LOSSES (W)
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
TJ = 125°C
FS = 700 kHz
VI = 3.3 V
VI = 5 V
806550
34
32
30
28
26
24
22
20
18 −40 125−25 −10 5 1109520 35 806550
30
28
26
24
22
20
18
16
−40 125−25 −10 5 1109520 35 806550 −40 125−25 −10 5 1109520 35 806550
VIN = 3.3 V VIN = 5 V
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TYPICAL CHARACTERISTICS
Figure 11. Output Voltage Regulation vs. Input
Voltage
Figure 12. Error Amplifier Open Loop
Response
Figure 13. Internal Slow−Start Time vs
Junction Temperature
VI, NPUT VOLTAGE (V)
3 3.5
Vref−VOLTAGE REFERENCE (V)
895
4 4.5 5 5.5 6
INTERNAL SLOW−START TIME (ms)
3.9
−40 125−25 −10 5 20 35 50 110958065
TJ, JUNCTION TEMPERATURE (°C)
893
891
889
887
885
F, FREQUENCY (Hz)
110
GAIN (dB)
140
10k 100k 1M 10M 100M
120
100
80
60
40
20
0
−20
−40 1k100
160
140
120
100
80
60
40
20
0
−20
PHASE MARGIN (°)
3.8
3.7
3.6
3.5
3.4
TA = 85°C
IO = 3 A
FS = 550 kHz
RL = 10 kW
CL = 160 pF
TA = 25°C
Phase
Gain
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APPLICATION INFORMATION
Figure 14 shows the schematic diagram for a typical
NCP1592 application. The NCP1592 (U1) can provide
greater than 6 A of output current at a nominal output
voltage of 3.3 V. For proper thermal performance, the
exposed thermal PowerPAD underneath the integrated
circuit package must be soldered to the printed−circuit
board.
Figure 14. Application Circuit
24
16
17
15
18
19
5
6
7
8
9
10
11
12
13
14
20
21
22
23
1
2
3
4
25
26
27
28
C7
0.047 mF
L1
4.7
μH
R5
1.18 kW
R4
10 kW
C6
12 nF
C5
6.8 nF
C3
68 pF
R1
9.76 kW
C9
470 mF
4 V
C10
470 mF
4 V
C11
100 pF
C8
10 mF
C2200 mF
10 V
R2
10 kW
C4
0.1 mF
C1
0.047 mF
VI
Vo
PWRGD
U1
NCP1592
++
+
VIN
VIN
VIN
VIN
VIN
PH
PH
PH
PH
PH
PH
PH
PH
PH
BOOT
PGND
PGND
PGND
PGND
PGND
POWERPAD
RT
SYNC
SS/ENA
VBIAS
PWRGD
COMP
VSENSE
AGND
R2
3.74 kW
COMPONENT SELECTION
INPUT FILTER
The input to the circuit is a nominal 5 VDC. The input
filter C2 is a 220 μF POSCAP capacitor, with a maximum
allowable ripple current of 3 A. C8 provides high frequency
decoupling of the NCP1592 from the input supply and must
be located as close as possible to the device. Ripple current
is carried in both C2 and C8, and the return path to PGND
must avoid the current circulating in the output capacitors
C9 and C10.
FEEDBACK CIRCUIT
The resistor divider network of R3 and R4 sets the output
voltage for the circuit at 3.3 V. R4, along with R1, R5, C3,
C5, and C6 form the loop compensation network for the
circuit. For this design, a Type 3 topology is used.
OPERATING FREQUENCY
In the application circuit, the 350 kHz operation is
selected by leaving RT and SYNC open. Connecting a
180 kW to 68 kW resistor between RT (pin 28) and analog
ground can be used to set the switching frequency to
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280 kHz to 700 kHz. To calculate the RT resistor, use the
equation below:
R+500 kHz
Switching Frequency 100 [kW](eq. 1)
OUTPUT FILTER
The output filter is composed of a 4.7 μH inductor and t w o
470 μF capacitors. The inductor is a low dc resistance
(12 mW) type, Coiltronics UP3B−4R7. The capacitors used
are 4 V POSCAP types with a maximum ESR of 0.040 W.
The feedback loop is compensated so that the unity gain
frequency is approximately 25 kHz.
PCB LAYOUT
Figure 15 shows a generalized PCB layout guide for
NCP1592.
The VIN pins are connected together on the
printed−circuit board (PCB) and bypassed with a low−ESR
ceramic−bypass capacitor. Care should be taken to minimize
the loop area formed by the bypass capacitor connections,
the VIN pins, and the NCP1592 ground pins. The minimum
recommended bypass capacitance is 10 mF ceramic
capacitor with a X5R or X7R dielectric and the optimum
placement is closest to the VIN pins and the PGND pins.
The NCP1592 has two internal grounds (analog and
power). Inside the NCP1592, the analog ground ties to all o f
the noise sensitive signals, while the power ground ties to the
noisier power signals. Noise injected between the two
grounds can degrade the performance of the NCP1592,
particularly at higher output currents. However, ground
noise on an analog ground plane can also cause problems
with some of the control and bias signals. Therefore,
separate analog and power ground traces are recommended.
There is a n area of ground on the top layer directly under the
IC, with an exposed area for connection to the PowerPAD.
Use vias to connect this ground area to any internal ground
planes. Additional vias are also used at the ground side of the
input and output filter capacitors. The AGND and PGND
pins are tied to the PCB ground by connecting them to the
ground area under the device as shown. The only
components that tie directly to the power ground plane are
the input capacitors, the output capacitors, the input voltage
decoupling capacitor, and the PGND pins of the NCP1592.
Use a separate wide trace for the analog ground signal path.
The analog ground is used for the voltage set point divider,
timing resistor RT, slow−start capacitor and bias capacitor
grounds. Connect this trace directly to AGND (Pin 1).
The PH pins are tied together and routed to the output
inductor. Since the PH connection is the switching node, the
inductor is located close to the PH pins. The area of the PCB
conductor is minimized to prevent excessive capacitive
coupling. Connect the boot capacitor between the phase
node and the BOOT pin as shown. Keep the boot capacitor
close to the IC and minimize the conductor trace lengths.
Connect the output filter capacitor(s) as shown between
the VOUT trace and PGND. It is important to keep the loop
formed by the PH pins, LOUT, COUT and PGND as small
as practical.
Place the compensation components from the VOUT
trace to the VSENSE and COMP pins. Do not place these
components too close to the PH trace. Due to the s ize of the
IC package and the device pin−out, they must be routed
close, but maintain as much separation as possible while still
keeping the layout compact.
Connect the bias capacitor from the VBIAS pin to analog
ground using the isolated analog ground trace. If a
slow−start capacitor or RT resistor is used, or if the SYNC
pin is used to select 350 kHz operating frequency, connect
them to this trace.
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Figure 15. Recommended Land Pattern For 28−Pin PowerPAD
LAYOUT CONSIDERATIONS FOR THERMAL
PERFORMANCE
For operation at full rated load current, the analog ground
plane must provide an adequate heat dissipating area. A
3−inch by 3−inch plane of 1 copper is recommended, though
not mandatory, depending on ambient temperature and
airflow. Most applications have larger areas of internal
ground plane available, and the PowerPAD must be
connected to the largest area available. Additional areas on
the top or bottom layers also help dissipate heat, and any area
available must be used when 6 A or greater operation is
desired. Connection from the exposed area of the
PowerPAD to the analog ground
plane layer must be made using 0.013 inch diameter vias
to avoid solder wicking through the vias. Eight vias must be
in the PowerPAD area with four additional vias located
under the device package. The size of the vias under the
package, but not in the exposed thermal pad area, can be
increased to 0.018. Additional vias beyond the twelve
recommended that enhance thermal performance must be
included in areas not under the device package.
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Minimum Recommended Exposed
Copper Area for PowerPAD, 5 mm
Stencils May Require 10%
Larger Area
Minimum recommended Top
Side Analog Ground Area
Connect Pin 1 to Analog Ground
Plane in this Area for Optimum Performance
Minimum recommended Thermal Vias: 8x
0.013 Diameter Inside PowerPAD area 4 x
0.018 Diameter Under Device as Shown.
Additional 0.018 Diameter Vias May Be Used
if Top Side Analog Ground Area is Extended.
Figure 16. Recommended Land Pattern For 28−Pin PowerPAD
0.0339
0.0650
0.0500
0.0500
0.0500
0.0650
0.0339
0.34780.3820
0.1700
0.1340
0.0630
0.0400
0.0600
0.0150
0.0256
0.2090
q0.0130
q0.0180
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PERFORMANCE GRAPHS
Figure 17. Efficiency vs Output Current Figure 18. Efficiency vs Output Current
Figure 19. Load Regulation vs Input Voltage Figure 20. Loop Response
Figure 21. Ambient Temperature vs Load
Current
Figure 22. Output Ripple Voltage
01 23 456
100
IO, OUTPUT CURRENT (A)
EFFICIENCY (%)
VI = 5 V
f = 550 kHz
L = 4.7 mH
TA = 25°C
VO = 3.3 V
VO = 1.8 V VO = 1.2 V
7
90
80
70
60
50
LOAD REGULATION
01 23 456
1.004
IO, OUTPUT CURRENT (A)
1.003
1.002
1.001
1
0.999
0.998
0.997
0.996
01 23 456
100
IO, OUTPUT CURRENT (A)
EFFICIENCY (%)
VI = 3.3 V
f = 550 kHz
L = 4.7 mH
TA = 25°C
VO = 2.5 V
VO = 1.8 V VO = 1.2 V
90
80
70
60
50 7
VI = 5 V
VO = 3.3 V
TA = 25°C
Fs = 550 kHz
125
115
105
95
85
75
65
55
45
35
25 01 23 456 78
AMBIENT TEMPERATURE (°C)
IL, LOAD CURRENT (A)
TA = 125°C
Fs = 700 kHz
VI = 5.0 V
VI = 3.3 V
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PERFORMANCE GRAPHS
Figure 23. Line Regulation vs Output Current Figure 24. Load Transient Response
6 A
0 A 3 A
1.002
1.0015
1.001
1.0005
1
0.9995
0.999
0.9985
0.998
IOUT, OUTPUT CURRENT
VI, INPUT VOLTAGE (V)
4 4.5 5 5.5 6
Figure 25. Slow Start Timing
Figure 26 shows the schematic diagram for a reduced size,
high frequency application using the NCP1592. The
NCP1592 (U1) can provide up to 6 A of output current at a
nominal output voltage of 1.8 V. A small size 0.56 μH
inductor is used and the switching frequency is set to
680 kHz by R1. The compensation network is optimized for
fast transient response as shown in Figure 27. For good
thermal performance, the PowerPAD underneath the
integrated circuit NCP1592 needs to be soldered well to the
printed−circuit board.
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Figure 26. Small Size, High Frequency Design
Figure 27. Transient Response, 1.5 to 4.5 A Step
26 20
27
21
22
23
24
9
10
11
12
13
14
19
28
5
6
7
8
15
25
4
3
2
116
17
18
R1
68.1 kW
C2
10 mF
C1
10 mF
C3
22 nF
C4
100 nF
C5
1 nF
C6
150 pF
R2
3.4 kW
C12
5.6 nF
VI
C11
1000 pF
C7
100 nF
C9
470 mFC10
10 mF
L1
1 mH
Vo
U1
NCP1592
+
VIN
VIN
VIN
VIN
VIN
PH
PH
PH
PH
PH
PH
PH
PH
PH
BOOT
PGND
PGND
PGND
PGND
PGND
POWERPAD
RT
SYNC
SS/ENA
VBIAS
PWRGD
COMP
VSENSE
AGND
R3
332 W
R6
10 kW
R5
90.9 kW
R4
10 W
C2
10 mFC1
10 mF
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DETAILED DESCRIPTION
UNDERVOLTAGE LOCK OUT (UVLO)
The NCP1592 incorporates an under voltage lockout
circuit to keep the device disabled when the input voltage
(VIN) is insufficient. During power up, internal circuits ar e
held inactive until VIN exceeds the nominal UVLO
threshold voltage of 2.95 V. Once the UVLO start threshold
is reached, device start−up begins. The device operates until
VIN falls below the nominal UVLO stop threshold of 2.8 V.
Hysteresis in the UVLO comparator, and a 2.5 μs rising and
falling edge deglitch circuit reduce the likelihood of shutting
the device down due to noise on VIN.
SLOW−START/ENABLE (SS/ENA)
The slow−start/enable pin provides two functions. First,
the pin acts as an enable (shutdown) control by keeping the
device turned off until the voltage exceeds the start threshold
voltage of approximately 1.2 V. When SS/ENA exceeds the
enable threshold, device start−up begins. The reference
voltage fed to the error amplifier is linearly ramped up from
0 V to 0.891 V in 3.35 ms. Similarly, the converter output
voltage reaches regulation in approximately 3.35 ms.
Voltage hysteresis and a 2.5−μs falling edge deglitch
circuit reduce the likelihood of triggering the enable
due to noise.
The second function of the SS/ENA pin provides an
external means of extending the slow−start time with a
low−value capacitor connected between SS/ENA and
AGND.
Adding a capacitor to the SS/ENA pin has two effects on
start−up. First, a delay occurs between release of the
SS/ENA pin and start−up of the output. The delay is
proportional to the slow−start capacitor value and lasts until
the SS/ENA pin reaches the enable threshold. The start−up
delay is approximately:
td+C(SS) 1.2 V
5mA(eq. 2)
Second, as the output becomes active, a brief ramp−up at
the internal slow−start rate may be observed before the
externally set slow−start rate takes control and the output
rises at a rate proportional to the slow−start capacitor. The
slow−start time set by the capacitor is approximately:
t(SS) +C(SS) 0.7 V
5mA(eq. 3)
The actual slow−start time is likely to be less than the
above approximation due to the brief ramp−up at the internal
rate.
During the soft−start period the output voltage is closed
loop regulated from 0V to the output set voltage by slewing
the reference voltage from 0 V to 0.891 V. If output voltage
is not at 0 V during startup (pre-biased startup), output
capacitor will be discharged by the control loop. The energy
from the capacitors will flow from the output to ground and
input through the low-side and High side MOSFETs. Under
extreme conditions where pre-biased voltage is high with
large output capacitance MOSFETs can be damaged.
VBIAS REGULATOR (VBIAS)
The VBIAS regulator provides internal analog and digital
blocks with a stable supply voltage over variations in
junction temperature and input voltage.
A high quality, low−ESR, ceramic bypass capacitor is
required on the VBIAS pin. X7R or X5R grade dielectrics
are recommended because their values are more stable over
temperature. The bypass capacitor must be placed close to
the VBIAS pin and returned to AGND.
External loading on VBIAS is allowed, with the caution
that internal circuits require a minimum VBIAS of 2.70 V,
and external loads on VBIAS with ac or digital switching
noise may degrade performance. The VBIAS pin may be
useful as a reference voltage for external circuits.
VOLTAGE REFERENCE
The voltage reference system produces a precise Vref
signal by scaling the output of a temperature stable bandgap
circuit. During manufacture, the bandgap and scaling
circuits are trimmed to produce 0.891 V at the output of the
error amplifier, with the amplifier connected as a voltage
follower. The trim procedure adds to the high precision
regulation of the NCP1592, since it cancels offset errors in
the scale and error amplifier circuits.
0SCILLATOR AND PWM RAMP
The oscillator frequency can be set to internally fixed
values o f 350 kHz or 550 kHz using the SYNC pin as a static
digital input. If a d ifferent frequency of operation is required
for the application, the oscillator frequency can be
externally adjusted from 280 to 700 kHz by connecting a
resistor between the RT pin and AGND and floating the
SYNC pin. The switching frequency is approximated by the
following equation, where R is the resistance from RT to
AGND:
Switching Frequency +100 kW
R 500 [kHz] (eq. 4)
External synchronization of the PWM ramp is possible
over the frequency range of 330 kHz to 700 kHz by driving
a synchronization signal into SYNC and connecting a
resistor from RT to AGND. Choose a resistor between the
RT and AGND which sets the free running frequency to 80%
of the synchronization signal. The following table
summarizes the frequency selection configurations:
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Switching Frequency Sync Pin RT Pin
350 kHz, internally set Float or AGND Float
550 kHz, internally set ≥2.5 V Float
Externally set 280 kHz to 700 kHz Float R= 180 kW to 68 kW
Externally synchronized frequency Synchronization signal R = RT value for 80% of external
synchronization frequency
ERROR AMPLIFIER
The high performance, wide bandwidth, voltage error
amplifier sets the NCP1592 apart from most dc/dc
converters. The user is given the flexibility to use a wide
range of output L and C filter components to suit the
particular application needs. Type 2 or type 3 compensation
can be employed using external compensation components.
PWM CONTROL
Signals from the error amplifier output, oscillator, and
current limit circuit are processed by the PWM control logic.
Referring to the internal block diagram, the control logic
includes the PWM comparator, OR gate, PWM latch, and
portions of the adaptive dead−time and control logic block.
During steady−state operation below the current limit
threshold, the PWM comparator output and oscillator pulse
train alternately reset and set the PWM latch. Once the PWM
latch is reset, the low−side FET remains on for a minimum
duration set by the oscillator pulse width. During this period,
the PWM ramp discharges rapidly to its valley voltage.
When the ramp begins to char ge back up, the low−side FET
turns off and high−side FET turns on. As the PWM ramp
voltage exceeds the error amplifier output voltage, the P W M
comparator resets the latch, thus turning off the high−side
FET and turning on the low−side FET. The low−side FET
remains on until next oscillator pulse discharges the PWM
ramp.
During transient conditions, the error amplifier output
could be below the PWM ramp valley voltage or above the
PWM peak voltage. If the error amplifier is high, the PWM
latch is never reset, and the high−side FET remains on until
the oscillator pulse signals the control logic to turn the
high−side FET off and the low−side FET on. The device
operates at its maximum duty cycle until the output voltage
rises to the regulation set−point, setting VSENSE to
approximately the same voltage as VREF. If the error
amplifier output is low, the PWM latch is continually reset
and the high−side FET does not turn on. The low−side FET
remains on until the VSENSE voltage decreases to a range
that allows the PWM comparator to change states. The
NCP1592 is capable of sinking current continuously until
the output reaches the regulation set−point.
If the current limit comparator trips for longer than 100 ns,
the PWM latch resets before the PWM ramp exceeds the
error amplifier output. The high−side FET turns off and
low−side FET turns on to decrease the energy in the output
inductor and consequently output current. This process is
repeated each cycle in which the current limit comparator is
tripped.
DEAD−TIME CONTROL AND MOSFET DRIVERS
Adaptive dead−time control prevents shoot−through
current from flowing in both N−channel power MOSFETs
during the switching transitions by actively controlling the
turn−on times of the MOSFET drivers. The high−side driver
does not turn on until the voltage at the gate of the low−side
FET is below 2 V. While the low−side driver does not turn
on until the voltage at the gate of the high−side MOSFET is
below 2 V.
The high−side and low−side drivers are designed with
300 mA source and sink capability to quickly drive the
power MOSFETs gates. The low−side driver is supplied
from VIN, while the high−side driver is supplied from the
BOOT pin. A bootstrap circuit uses an external BOOT
capacitor and an internal 2.5 W bootstrap switch connected
between the VIN and BOOT pins. The integrated bootstrap
switch improves drive efficiency and reduces external
component count.
OVERCURRENT PROTECTION
The cycle−by−cycle current limiting is achieved by
sensing the current flowing through the high−side MOSFET
and comparing this signal to a preset overcurrent threshold.
The high side MOSFET is turned off within 200 ns of
reaching the current limit threshold. A 100 ns leading edge
blanking circuit prevents current limit false tripping.
Current limit detection occurs only when current flows from
VIN to PH when sourcing current to the output filter. Load
protection during current sink operation is provided by
thermal shutdown.
THERMAL SHUTDOWN
The device uses the thermal shutdown to turn off the
power MOSFETs and disable the controller if the junction
temperature exceeds 150°C. The device is released from
shutdown automatically when the junction temperature
decreases to 10°C below the low thermal shutdown trip
point, and starts up under control of the slow−start circuit.
Thermal shutdown provides protection when an overload
condition is sustained for several milliseconds. With a
persistent fault condition, the device cycles continuously;
starting up b y control of the soft−start circuit, heating up due
to the fault condition, and then shutting down upon reaching
NCP1592
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18
the thermal shutdown trip point. This sequence repeats until
the fault condition is removed.
POWER−GOOD (PWRGD)
The power good circuit monitors for under voltage
conditions on VSENSE. If the voltage on VSENSE is 10%
below the reference voltage, the open−drain PWRGD output
is pulled low. PWRGD is also pulled low if VIN is less than
the UVLO threshold or SS/ENA is low, or a thermal
shutdown occurs. When VIN ≥ UVLO threshold, SS/ENA
≥ enable threshold, and VSENSE > 90% of Vref, the open
drain output of the PWRGD pin is high. A hysteresis voltage
equal to 3 % o f Vref and a 35 μs falling edge deglitch circuit
prevent tripping of the power good comparator due to high
frequency noise.
ORDERING INFORMATION
Device Temperature
Range (5C) Package Shipping†
NCP1592PAR2G −40 to +125 TSSOP−28 EP
(Pb−Free) 2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
NCP1592
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19
PACKAGE DIMENSIONS
TSSOP28 9.7x4.4 EP
CASE 948BG
ISSUE O
ÇÇÇÇ
ÇÇÇÇ
0.20 A
e
15
28
14
PIN ONE
LOCATION
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION
SHALL BE 0.07 MAX AT MAXIMUM MATERIAL
CONDITION. DAMBAR CANNOT BE LOCATED
ON THE LOWER RADIUS OF THE FOOT. MIN-
IMUM SPACE BETWEEN PROTRUSION AND
ADJACENT LEAD IS 0.07.
4. DIMENSION D DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE
BURRS SHALL NOT EXCEED 0.15 PER SIDE.
DIMENSION D IS DETERMINED AT DATUM
PLANE H.
5. DIMENSION E1 DOES NOT INCLUDE INTER-
LEAD FLASH OR PROTRUSIONS. INTER-
LEAD FLASH OR PROTRUSIONS SHALL NOT
EXCEED 0.25 PER SIDE. DIMENSION E1 IS
DETERMINED AT DATUM PLANE H.
6. DATUMS A AND B TO BE DETERMINED AT
DATUM PLANE H.
7. A1 IS DEFINED AS THE VERTICAL DISTANCE
FROM THE SEATING PLANE TO THE LOW-
EST POINT ON THE PACKAGE BODY.
8. SECTION B−B TO BE DETERMINED AT 0.10
TO 0.25 FROM THE LEAD TIP.
E
E1
BC
1
0.10
SEATING
D
C
PLANE
A
A2
b
28X
0.10 ABC
DIM MIN MAX
MILLIMETERS
A−−− 1.20
A1 0.00 0.15
A2 0.80 1.05
b0.19 0.30
b1 0.19 0.25
c0.09 0.20
c1 0.09 0.16
D9.60 9.80
E6.40 BSC
E1 4.30 4.50
e0.65 BSC
L0.45 0.75
L2 0.25 BSC
D2 5.21 6.17
E2 1.44 2.40
M0 8
__
2X 14 TIPS
ÇÇÇ
ÇÇÇ
SECTION B−B
c
c1
b
b1
ÉÉÉ
ÉÉÉ
M
L
DETAIL A
END VIEW
c
DET AIL A
A1
B
B
GAUGE
PLANE
C
NOTE 7
HL2
NOTE 8
E2
BOTTOM VIEW
D2
6.70
28X
0.30
28X
1.15
0.65
DIMENSIONS: MILLIMETERS
1
PITCH
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
RECOMMENDED
2.70
6.47
B
A
TOP VIEW
NOTE 5
NOTE 6
NOTE 6
SIDE VIEW NOTE 3
NOTE 4
C
28X
0.05 C
NCP1592
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P
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USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
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Phone: 81−3−5817−1050
NCP1592/D
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