SCES204K − APRIL 1999 − REVISED SEPTEMBER 2003
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DAvailable in the Texas Instruments
NanoStarand NanoFreePackages
DSupports 5-V VCC Operation
DInputs Accept Voltages to 5.5 V
DMax tpd of 4.3 ns at 3.3 V
DLow Power Consumption, 10-µA Max ICC
D±24-mA Output Drive at 3.3 V
DTypical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
DTypical VOHV (Output VOH Undershoot)
>2 V at VCC = 3.3 V, TA = 25°C
DIoff Supports Partial-Power-Down Mode
Operation
DLatch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
DESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
description/ordering information
The SN74LVC2G125 is a dual bus buf fer gate, designed for 1.65-V t o 5.5-V VCC operation. This device features
dual line drivers with 3-state outputs. The outputs are disabled when the associated output-enable (OE) input
is high.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING‡
NanoStar − WCSP (DSBGA)
0.17-mm Small Bump − YEA SN74LVC2G125YEAR
NanoFree − WCSP (DSBGA)
0.17-mm Small Bump − YZA (Pb-free)
SN74LVC2G125YZAR
°
°
NanoStar − WCSP (DSBGA)
0.23-mm Large Bump − YEP
Reel of 3000 SN74LVC2G125YEPR _ _ _CM_
NanoFree − WCSP (DSBGA)
0.23-mm Large Bump − YZP (Pb-free) SN74LVC2G125YZPR
SSOP − DCT Reel of 3000 SN74LVC2G125DCTR C25_ _ _
Reel of 3000 SN74LVC2G125DCUR
Reel of 250 SN74LVC2G125DCUT
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
‡DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
DCU: The actual top-side marking has one additional character that designates the assembly/test site.
YEA/YZA, YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code,
and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition
(1 = SnPb, • = Pb-free).
Copyright 2003, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar and NanoFree are trademarks of Texas Instruments.
DCT OR DCU PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
1OE
1A
2Y
GND
VCC
2OE
1Y
2A
4
3
2
1
5
6
7
8
GND
2Y
1A
1OE
2A
1Y
2OE
VCC
YEA, YEP, YZA, OR YZP PACKAGE
(BOTTOM VIEW)
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