SCES204K - APRIL 1999 - REVISED SEPTEMBER 2003 D Available in the Texas Instruments D D D D D D D D D D DCT OR DCU PACKAGE (TOP VIEW) NanoStar and NanoFree Packages Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 4.3 ns at 3.3 V Low Power Consumption, 10-A Max ICC 24-mA Output Drive at 3.3 V Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25C Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25C Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 200-V Machine Model (A115-A) - 1000-V Charged-Device Model (C101) 1OE 1A 2Y GND 1 8 2 7 3 6 4 5 VCC 2OE 1Y 2A YEA, YEP, YZA, OR YZP PACKAGE (BOTTOM VIEW) GND 2Y 1A 1OE 4 5 3 6 2 7 1 8 2A 1Y 2OE VCC description/ordering information The SN74LVC2G125 is a dual bus buffer gate, designed for 1.65-V to 5.5-V VCC operation. This device features dual line drivers with 3-state outputs. The outputs are disabled when the associated output-enable (OE) input is high. ORDERING INFORMATION ORDERABLE PART NUMBER PACKAGE TA NanoStar - WCSP (DSBGA) 0.17-mm Small Bump - YEA SN74LVC2G125YEAR NanoFree - WCSP (DSBGA) 0.17-mm Small Bump - YZA (Pb-free) -40C to 85C NanoStar - WCSP (DSBGA) 0.23-mm Large Bump - YEP SN74LVC2G125YZAR Reel of 3000 VSSOP - DCU _ _ _CM_ SN74LVC2G125YEPR NanoFree - WCSP (DSBGA) 0.23-mm Large Bump - YZP (Pb-free) SSOP - DCT TOP-SIDE MARKING SN74LVC2G125YZPR Reel of 3000 SN74LVC2G125DCTR Reel of 3000 SN74LVC2G125DCUR Reel of 250 SN74LVC2G125DCUT C25_ _ _ C25_ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site. DCU: The actual top-side marking has one additional character that designates the assembly/test site. YEA/YZA, YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, * = Pb-free). Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoStar and NanoFree are trademarks of Texas Instruments. Copyright 2003, Texas Instruments Incorporated !"# $ %&'# "$ (&)*%"# +"#', +&%#$ %! # $('%%"#$ (' #-' #'!$ '."$ $#&!'#$ $#"+"+ /""#0, +&%# (%'$$1 +'$ # '%'$$"*0 %*&+' #'$#1 "** (""!'#'$, POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SCES204K - APRIL 1999 - REVISED SEPTEMBER 2003 description/ordering information (continued) NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. FUNCTION TABLE (each buffer) INPUTS OE A OUTPUT Y L H H L L L H X Z logic diagram (positive logic) 1 1OE 1A 2 6 1Y 7 2OE 5 3 2A 2Y absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6.5 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6.5 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6.5 V Voltage range applied to any output in the high or low state, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Package thermal impedance, JA (see Note 3): DCT package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220C/W DCU package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227C/W YEA/YZA package . . . . . . . . . . . . . . . . . . . . . . . . . . . 140C/W YEP/YZP package . . . . . . . . . . . . . . . . . . . . . . . . . . . 102C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The value of VCC is provided in the recommended operating conditions table. 3. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SCES204K - APRIL 1999 - REVISED SEPTEMBER 2003 recommended operating conditions (see Note 4) Operating VCC VIH Supply voltage High-level input voltage VIL Low-level input voltage VI Input voltage VO Output voltage Data retention only VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V High-level output current t/v Input transition rise or fall rate 5.5 UNIT V 1.5 0.65 x VCC 1.7 V 2 0.7 x VCC 0.35 x VCC 0.7 0.8 V 0.3 x VCC 0 5.5 V High or low state 0 3-state 0 VCC 5.5 V -4 -8 -16 VCC = 3 V VCC = 2.3 V Low-level output current 1.65 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V VCC = 4.5 V VCC = 1.65 V IOL MAX VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 1.65 V VCC = 2.3 V IOH MIN -32 4 8 16 VCC = 3 V mA -24 mA 24 VCC = 4.5 V VCC = 1.8 V 0.15 V, 2.5 V 0.2 V 32 VCC = 3.3 V 0.3 V VCC = 5 V 0.5 V 10 20 ns/V 5 TA Operating free-air temperature -40 85 C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 SCES204K - APRIL 1999 - REVISED SEPTEMBER 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 5.5 V IOH = -100 mA IOH = -4 mA IOH = -8 mA IOH = -16 mA VOH 1.9 3.8 0.1 1.65 V 0.45 2.3 V 0.3 IOL = 8 mA IOL = 16 mA 0.4 3V 0.55 5 mA 10 mA 10 mA 1.65 V to 5.5 V 10 mA 3 V to 5.5 V 500 mA VI = 5.5 V or GND VI or VO = 5.5 V 0 to 5.5 V IOZ ICC VO = 0 to 5.5 V VI = 5.5 V or GND, 3.6 V ICC One input at VCC - 0.6 V, 0 IO = 0 Other inputs at VCC or GND Data inputs Control inputs V 0.55 4.5 V IOL = 32 mA UNIT V 1.65 V to 5.5 V IOL = 24 mA Ci MAX 2.3 4.5 V IOL = 100 mA IOL = 4 mA A or OE inputs 2.3 V 3V IOH = -32 mA II Ioff 1.65 V VCC-0.1 1.2 TYP 2.4 IOH = -24 mA VOL MIN 3.5 VI = VCC or GND 3.3 V Co VO = VCC or GND All typical values are at VCC = 3.3 V, TA = 25C. pF 4 3.3 V 6.5 pF switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) FROM (INPUT) TO (OUTPUT) tpd A ten tdis PARAMETER VCC = 1.8 V 0.15 V VCC = 2.5 V 0.2 V VCC = 3.3 V 0.3 V VCC = 5 V 0.5 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX Y 3.3 9.1 1.5 4.8 1.4 4.3 1 3.7 ns OE Y 4 9.9 1.9 5.6 1.2 4.7 1.2 3.8 ns OE Y 1.5 11.6 1 5.8 1.4 4.6 1 3.4 ns operating characteristics, TA = 25 TEST CONDITIONS PARAMETER Cpd 4 Power dissipation capacitance Outputs enabled Outputs disabled f = 10 MHz POST OFFICE BOX 655303 VCC = 1.8 V TYP VCC = 2.5 V TYP VCC = 3.3 V TYP VCC = 5 V TYP 19 19 20 22 2 2 2 3 * DALLAS, TEXAS 75265 UNIT pF SCES204K - APRIL 1999 - REVISED SEPTEMBER 2003 PARAMETER MEASUREMENT INFORMATION RL From Output Under Test CL (see Note A) VLOAD Open S1 GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V 5 V 0.5 V VI tr/tf VCC VCC 3V VCC 2 ns 2 ns 2.5 ns 2.5 ns VM VLOAD CL RL V VCC/2 VCC/2 1.5 V VCC/2 2 x VCC 2 x VCC 6V 2 x VCC 30 pF 30 pF 50 pF 50 pF 1 k 500 500 500 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tw tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH tPHL VOH VM Output VM VOL tPHL Output Waveform 1 S1 at VLOAD (see Note B) tPLH VM VM VM 0V tPZL tPLZ VLOAD/2 VM tPZH VOH Output VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + V VOL tPHZ VM VOH - V VOH 0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 . D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 MECHANICAL DATA MPDS049B - MAY 1999 - REVISED OCTOBER 2002 DCT (R-PDSO-G8) PLASTIC SMALL-OUTLINE PACKAGE 0,30 0,15 0,65 8 0,13 M 5 0,15 NOM CCCCC CCCCC CCCCC CCCCC 2,90 2,70 4,25 3,75 Gage Plane PIN 1 INDEX AREA 1 0,25 4 0 - 8 3,15 2,75 0,60 0,20 1,30 MAX Seating Plane 0,10 0,10 0,00 NOTES: A. B. C. D. 4188781/C 09/02 All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion Falls within JEDEC MO-187 variation DA. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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