1
JUNE 2002
DSC-5907/14
2002 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
2.5 VOLT HIGH-SPEED TeraSyncTM
FIFO 36-BIT CONFIGURATIONS
1,024 x 36, 2,048 x 36, 4,096 x 36,
8,192 x 36, 16,384 x 36, 32,768 x 36,
65,536 x 36, 131,072 x 36 and 262,144 x 36
PRELIMINARY
IDT72T3645, IDT72T3655, IDT72T3665,
IDT72T3675, IDT72T3685, IDT72T3695,
IDT72T36105, IDT72T36115, IDT72T36125
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The TeraSync FIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
FEATURES:
••
••
•Choose among the following memory organizations:
IDT72T3645
1,024 x 36
IDT72T3655
2,048 x 36
IDT72T3665
4,096 x 36
IDT72T3675
8,192 x 36
IDT72T3685
16,384 x 36
IDT72T3695
32,768 x 36
IDT72T36105
65,536 x 36
IDT72T36115
131,072 x 36
IDT72T36125
262,144 x 36
••
••
•Up to 225 MHz Operation of Clocks
••
••
•User selectable HSTL/LVTTL Input and/or Output
••
••
•2.5V LVTTL or 1.8V, 1.5V HSTL Port Selectable Input/Ouput voltage
••
••
•3.3V Input tolerant
••
••
•Read Enable & Read Clock Echo outputs aid high speed operation
••
••
•User selectable Asynchronous read and/or write port timing
••
••
•Mark & Retransmit, resets read pointer to user marked position
••
••
•Write Chip Select (WCS) input enables/disables Write operations
••
••
•Read Chip Select (RCS) synchronous to RCLK
••
••
•Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of eight preselected offsets
••
••
•Program programmable flags by either serial or parallel means
••
••
•Selectable synchronous/asynchronous timing modes for Almost-
Empty and Almost-Full flags
••
••
•Separate SCLK input for Serial programming of flag offsets
••
••
•User selectable input and output port bus-sizing
- x36 in to x36 out
- x36 in to x18 out
- x36 in to x9 out
- x18 in to x36 out
- x9 in to x36 out
••
••
•Big-Endian/Little-Endian user selectable byte representation
••
••
•Auto power down minimizes standby power consumption
••
••
•Master Reset clears entire FIFO
••
••
•Partial Reset clears data, but retains programmable settings
••
••
•Empty, Full and Half-Full flags signal FIFO status
••
••
•Select IDT Standard timing (using EF and FF flags) or First Word
Fall Through timing (using OR and IR flags)
••
••
•Output enable puts data outputs into high impedance state
••
••
•JTAG port, provided for Boundary Scan function
••
••
•Available in 208-pin (17mm x 17mm) or 240-pin (19mm x 19mm)
Plastic Ball Grid Array (PBGA)
••
••
•Easily expandable in depth and width
••
••
•Independent Read and Write Clocks (permit reading and writing
simultaneously)
••
••
•High-performance submicron CMOS technology
••
••
•Industrial temperature range (–40°°
°°
°C to +85°°
°°
°C) is available
INPUT REGISTER
OUTPUT REGISTER
RAM ARRAY
1,024 x 36, 2,048 x 36
4,096 x 36, 8,192 x 36
16,384 x 36, 32,768 x 36
65,536 x 36, 131,072 x36
262,144 x 36
FLAG
LOGIC
FF/IR
PAF
EF/OR
PAE
HF
READ POINTER
READ
CONTROL
LOGIC
WRITE CONTROL
LOGIC
WRITE POINTER
RESET
LOGIC
WEN WCLK/WR
D
0
-D
n
(x36, x18 or x9)
LD
MRS
REN
RCLK/RD
OE
Q
0
-Q
n
(x36, x18 or x9)
OFFSET REGISTER
PRS
FWFT/SI
SEN
RT
5907 drw01
BUS
CONFIGURATION
BM
CONTROL
LOGIC
BE
OW
IP
PFM
FSEL0
FSEL1
IW
MARK
SCLK
RCS
JTAG CONTROL
(BOUNDARY SCAN)
TCK
TMS
TDO
TDI
TRST
ASYR
WCS
ERCLK
EREN
HSTL I/0
CONTROL
Vref
WHSTL
RHSTL
ASYW
SHSTL
FUNCTIONAL BLOCK DIAGRAM
2
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
PIN CONFIGURATION
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
WCS SCLK
VREF
SEN
D33
D31
D29
D14
D11
D9 D10 D8
PRS
TCK
FWFT/SI
ASYR
SHSTL
BE
TDI
RHSTL RT
TMS
EF
D3
PAE
WCLK
TRST
MRS
D0
D5
VCC
D7
REN RCLK
RCS
Q32
Q30
Q28
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
A1 BALL PAD CORNER
VDDQ
VCC
VCC
VCC
VCC
VCC
GND
GND
GND
GND
GND
GND
GND
GND GND
GND
GND
GND
GND
GND
GND
GND
HFLD
VCC
VCC
VCC
VCC
VCC
D13
IP
BM
VDDQ
VCC
D27
D24
D22
D20
D18
D16
IW
D34
D32
D30
D28
D26
D23
D25
D21
D19
D17
D15
D12
D1
Q12
Q10
Q8
Q26
Q24
Q21
Q19
Q17
Q15
ERCLK Q1 Q3 Q9Q7Q5
PFM MARK
EREN
VCC
VCC
VCC
VCC
VCC
ASYW WHSTL FF
VCCVCC VCCVCC VDDQVCC VDDQVDDQ Q35VDDQ VDDQVDDQ
GNDVCC GNDVCC GNDGND GNDGND Q33VCC VDDQVDDQ
GND
GND
GND
VCC
VDDQ
VDDQ
Q4
VCC
GND
GND
GND
D6 D2
D4 TDO Q2Q0 Q6 Q11
Q23
Q22
Q20
Q18
Q16
Q13
Q31
Q29
Q27
Q25
VCC
GND
GND
GND
GND
GND
VCC
GND
GNDVCC GND
VCC GNDGND GND
GND VCC
VCC VCCVCCVCC VDDQVCC VDDQVDDQ VDDQ Q14
VDDQ
WEN
OE
Q34
D35
OW FSI
PAF FSO
VCC
5907 drw02
IDT72T3645/72T3655/72T3665/72T3675/72T3685/72T3695 Only
PBGA: 1mm pitch, 17mm x 17mm (BB208-1, order code: BB)
TOP VIEW
3
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
IDT72T36105/72T36115/72T36125 Only
PBGA: 1mm pitch, 19mm x 19mm (BB240-1, order code: BB)
TOP VIEW
PIN CONFIGURATION (CONTINUED)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
D21
D19 D20 D13
GND
TDO
GND
D4 TMS
GND
D5D10
D23
D22
D1
Q24
Q14GND Q0 Q2 Q11Q8Q3
GND
GND GNDGND GND GND
GND GND GND
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
D24
V
CC
GND
GND
GND
GND
GND
GND
GND
GND GND
GND
GND
GND
GND
GND
GND
GND
V
CC
REN
GND
PAF
EREN V
DDQ
OE
RCLKV
CC
V
CC
V
CC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
12 345678910111213141516
A1 BALL PAD CORNER
MRS
V
CC
V
CC
D35
D32
D29
D26
FF
EF
V
CC
V
CC
V
CC
D33
D30
D27
V
CC
V
CC
V
CC
V
CC
SEN
V
CC
V
CC
V
CC
D34
D31
D28
D25 Q27
V
DDQ
V
DDQ
V
DDQ
V
DDQ
Q33
Q30
RCS V
DDQ
V
DDQ
V
CC
V
CC
V
CC
SCLK
V
CC
V
CC
V
CC
V
CC
WCS
V
CC
V
CC
V
CC
PAELD HF
GND V
DDQ
MARK V
DDQ
RT
SHSTLFWFT/SI FS0
OW IPFS1 BE
GND PFMBM ASYR
RHSTL
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
WHSTL
ASYW
VREF
IW
GND
GND
GND
GND
V
CC
V
DDQ
V
DDQ
V
CC
WEN GND
WCLK PRS
V
CC
5907 drw02A
U
V
D18
V
CC
D16 D15
TDI
TCK
TRST
D6 D0
D2
D9D12
D14D17
D3
Q15
Q16GND ERCLK Q4 Q13Q10Q7
Q5D11 D8D7 GND Q6Q1 Q9 Q12
17 18
Q22
Q20
Q21
Q23
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
Q25
V
DDQ
V
DDQ
V
DDQ
Q34
Q31
Q28
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
Q35
Q32
Q29
Q26
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
Q19
V
DDQ
Q17
Q18
4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
DESCRIPTION:
The IDT72T3645/72T3655/72T3665/72T3675/72T3685/72T3695/
72T36105/72T36115/72T36125 are exceptionally deep, extrememly high
speed, CMOS First-In-First-Out (FIFO) memories with clocked read and write
controls and a flexible Bus-Matching x36/x18/x9 data flow. These FIFOs offer
several key user benefits:
• Flexible x36/x18/x9 Bus-Matching on both read and write ports
• A user selectable MARK location for retransmit
• User selectable I/O structure for HSTL or LVTTL
• Asynchronous/Synchronous translation on the read or write ports
• The first word data latency period, from the time the first word is written to an
empty FIFO to the time it can be read, is fixed and short.
• High density offerings up to 9 Mbit
Bus-Matching TeraSync FIFOs are particularly appropriate for network,
video, telecommunications, data communications and other applications that
need to buffer large amounts of data and match busses of unequal sizes.
Each FIFO has a data input port (Dn) and a data output port (Qn), both of
which can assume either a 36-bit, 18-bit or a 9-bit width as determined by the
state of external control pins Input Width (IW), Output Width (OW), and Bus-
Matching (BM) pin during the Master Reset cycle.
The input port can be selected as either a Synchronous (clocked) interface,
or Asynchronous interface. During Synchronous operation the input port is
controlled by a Write Clock (WCLK) input and a Write Enable (WEN) input. Data
present on the Dn data inputs is written into the FIFO on every rising edge of
WCLK when WEN is asserted. During Asynchronous operation only the WR
input is used to write data into the FIFO. Data is written on a rising edge of WR,
the WEN input should be tied to its active state, (LOW).
The output port can be selected as either a Synchronous (clocked) interface,
or Asynchronous interface. During Synchronous operation the output port is
controlled by a Read Clock (RCLK) input and Read Enable (REN) input. Data
is read from the FIFO on every rising edge of RCLK when REN is asserted.
During Asynchronous operation only the RD input is used to read data from the
FIFO. Data is read on a rising edge of RD, the REN input should be tied to its
active state, LOW. When Asynchronous operation is selected on the output port
the FIFO must be configured for Standard IDT mode, also the RCS should be
tied LOW and the OE input used to provide three-state control of the outputs, Qn.
The output port can be selected for either 2.5V LVTTL or HSTL operation,
this operation is selected by the state of the RHSTL input during a master reset.
An Output Enable (OE) input is provided for three-state control of the outputs.
A Read Chip Select (RCS) input is also provided, the RCS input is synchronized
to the read clock, and also provides three-state control of the Qn data outputs.
When RCS is disabled, the data outputs will be high impedance. During
Asynchronous operation of the output port, RCS should be enabled, held LOW.
Echo Read Enable, EREN and Echo Read Clock, ERCLK outputs are
provided. These are outputs from the read port of the FIFO that are required
for high speed data communication, to provide tighter synchronization between
the data being transmitted from the Qn outputs and the data being received by
the input device. Data read from the read port is available on the output bus with
respect to EREN and ERCLK, this is very useful when data is being read at
high speed. The ERCLK and EREN outputs are non-functional when the Read
port is setup for Asynchronous mode.
The frequencies of both the RCLK and the WCLK signals may vary from 0
to fMAX with complete independence. There are no restrictions on the frequency
of the one clock input with respect to the other.
There are two possible timing modes of operation with these devices: IDT
Standard mode and First Word Fall Through (FWFT) mode.
In IDT Standard mode, the first word written to an empty FIFO will not appear
on the data output lines unless a specific read operation is performed. A read
operation, which consists of activating REN and enabling a rising RCLK edge,
will shift the word from internal memory to the data output lines.
In FWFT mode, the first word written to an empty FIFO is clocked directly
to the data output lines after three transitions of the RCLK signal. A REN does
not have to be asserted for accessing the first word. However, subsequent
words written to the FIFO do require a LOW on REN for access. The state of
the FWFT/SI input during Master Reset determines the timing mode in use.
For applications requiring more data storage capacity than a single FIFO
can provide, the FWFT timing mode permits depth expansion by chaining FIFOs
in series (i.e. the data outputs of one FIFO are connected to the corresponding
data inputs of the next). No external logic is required.
These FIFOs have five flag pins, EF/OR (Empty Flag or Output Ready),
FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable
Almost-Empty flag) and PAF (Programmable Almost-Full flag). The EF and FF
functions are selected in IDT Standard mode. The IR and OR functions are
selected in FWFT mode. HF, PAE and PAF are always available for use,
irrespective of timing mode.
PAE and PAF can be programmed independently to switch at any point in
memory. Programmable offsets determine the flag switching threshold and can
be loaded by two methods: parallel or serial. Eight default offset settings are also
provided, so that PAE can be set to switch at a predefined number of locations
from the empty boundary and the PAF threshold can also be set at similar
predefined values from the full boundary. The default offset values are set during
Master Reset by the state of the FSEL0, FSEL1, and LD pins.
For serial programming, SEN together with LD on each rising edge of
SCLK, are used to load the offset registers via the Serial Input (SI). For parallel
programming, WEN together with LD on each rising edge of WCLK, are used
to load the offset registers via Dn. REN together with LD on each rising edge
of RCLK can be used to read the offsets in parallel from Qn regardless of whether
serial or parallel offset loading has been selected.
During Master Reset (MRS) the following events occur: the read and write
pointers are set to the first location of the FIFO. The FWFT pin selects IDT
Standard mode or FWFT mode.
The Partial Reset (PRS) also sets the read and write pointers to the first
location of the memory. However, the timing mode, programmable flag
programming method, and default or programmed offset settings existing before
Partial Reset remain unchanged. The flags are updated according to the timing
mode and offsets in effect. PRS is useful for resetting a device in mid-operation,
when reprogramming programmable flags would be undesirable.
It is also possible to select the timing mode of the PAE (Programmable Almost-
Empty flag) and PAF (Programmable Almost-Full flag) outputs. The timing
modes can be set to be either asynchronous or synchronous for the PAE and
PAF flags.
If asynchronous PAE/PAF configuration is selected, the PAE is asserted
LOW on the LOW-to-HIGH transition of RCLK. PAE is reset to HIGH on the LOW-
to-HIGH transition of WCLK. Similarly, the PAF is asserted LOW on the LOW-
to-HIGH transition of WCLK and PAF is reset to HIGH on the LOW-to-HIGH
transition of RCLK.
If synchronous PAE/PAF configuration is selected , the PAE is asserted and
updated on the rising edge of RCLK only and not WCLK. Similarly, PAF is
asserted and updated on the rising edge of WCLK only and not RCLK. The mode
desired is configured during MasterReset by the state of the Programmable Flag
Mode (PFM) pin.
5
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
DESCRIPTION (CONTINUED)
This device includes a Retransmit from Mark feature that utilizes two control
inputs, MARK and , RT (Retransmit). If the MARK input is enabled with respect
to the RCLK, the memory location being read at that point will be marked. Any
subsequent retransmit operation, RT goes LOW, will reset the read pointer to
this ‘marked’ location.
The device can be configured with different input and output bus widths as
shown in Table 1.
A Big-Endian/Little-Endian data word format is provided. This function is
useful when data is written into the FIFO in long word format (x36/x18) and read
out of the FIFO in small word (x18/x9) format. If Big-Endian mode is selected,
then the most significant byte (word) of the long word written into the FIFO will
be read out of the FIFO first, followed by the least significant byte. If Little-Endian
format is selected, then the least significant byte of the long word written into the
FIFO will be read out first, followed by the most significant byte. The mode desired
is configured during master reset by the state of the Big-Endian (BE) pin. See
Figure 5 for Bus-Matching Byte Arrangement.
The Interspersed/Non-Interspersed Parity (IP) bit function allows the user
to select the parity bit in the word loaded into the parallel port (D0-Dn) when
programming the flag offsets. If Interspersed Parity mode is selected, then the
FIFO will assume that the parity bit is located in bit positions D8, D17, D26 and
D35 during the parallel programming of the flag offsets. If Non-Interspersed
Parity mode is selected, then D8, D17 and D26 are assumed to be valid bits
and D32, D33, D34 and D35 are ignored. IP mode is selected during Master
Reset by the state of the IP input pin.
If, at any time, the FIFO is not actively performing an operation, the chip will
automatically power down. Once in the power down state, the standby supply
current consumption is minimized. Initiating any operation (by activating control
inputs) will immediately take the device out of the power down state.
Both an Asynchronous Output Enable pin (OE) and Synchronous Read
Chip Select pin (RCS) are provided on the FIFO. The Synchronous Read Chip
Select is synchronized to the RCLK. Both the output enable and read chip select
control the output buffer of the FIFO, causing the buffer to be either HIGH
impedance or LOW impedance.
A JTAG test port is provided, here the FIFO has fully functional Boundary
Scan feature, compliant with IEEE 1449.1 Standard Test Access Port and
Boundary Scan Architecture.
The TeraSync FIFO has the capability of operating its ports (write and/or
read) in either LVTTL or HSTL mode, each ports selection independent of the
other. The write port selection is made via WHSTL and the read port selection
via RHSTL. An additional input SHSTL is also provided, this allows the user
to select HSTL operation for other pins on the device (not associated with the
write or read ports).
The IDT72T3645/72T3655/72T3665/72T3675/72T3685/72T3695/
72T36105/72T36115/72T36125 are fabricated using IDT’s high speed sub-
micron CMOS technology.
6
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
BM IW OW Write Port Width Read Port Width
L L L x36 x36
H L L x36 x18
H L H x36 x9
H H L x18 x36
H H H x9 x36
TABLE 1 — BUS-MATCHING CONFIGURATION MODES
NOTE:
1. Pin status during Master Reset.
Figure 1. Single Device Configuration Signal Flow Diagram
(x36, x18, x9) DATA OUT (Q
0
- Q
n
)(x36, x18, x9) DATA IN (D
0
- D
n
)
MASTER RESET (MRS)
READ CLOCK (RCLK/RD)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
EMPTY FLAG/OUTPUT READY (EF/OR)
PROGRAMMABLE ALMOST-EMPTY (PAE)
WRITE CLOCK (WCLK/WR)
WRITE ENABLE (WEN)
LOAD (LD)
FULL FLAG/INPUT READY (FF/IR)
PROGRAMMABLE ALMOST-FULL (PAF)
IDT
72T3645
72T3655
72T3665
72T3675
72T3685
72T3695
72T36105
72T36115
72T36125
PARTIAL RESET (PRS)
FIRST WORD FALL THROUGH/
SERIAL INPUT (FWFT/SI) RETRANSMIT (RT)
5907 drw03
HALF-FULL FLAG (HF)
SERIAL ENABLE(SEN)
INPUT WIDTH (IW) OUTPUT WIDTH (OW)
BIG-ENDIAN/LITTLE-ENDIAN (BE)
INTERSPERSED/
NON-INTERSPERSED PARITY (IP)
BUS-
MATCHING
(BM)
SERIAL CLOCK (SCLK)
MARK
READ CHIP SELECT (RCS)
RCLK ECHO, ERCLK
REN ECHO, EREN
WRITE CHIP SELECT (WCS)
7
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
PIN DESCRIPTION
Symbol Name I/O TYPE Description
ASYR(1) Asynchronous LVTTL A HIGH on this input during Master Reset will select Synchronous read operation for the output port. A LOW
Read Port INPUT will select Asynchronous operation. If Asynchronous is selected the FIFO must operate in IDT Standard mode.
ASYW(1) Asynchronous LVTTL A HIGH on this input during Master Reset will select Synchronous write operation for the input port. A LOW
Write Port INPUT will select Asynchronous operation.
BE(1) Big-Endian/ LVTTL During Master Reset, a LOW on BE will select Big-Endian operation. A HIGH on BE during Master Reset
Little-Endian INPUT will select Little-Endian format.
BM(1) Bus-Matching LVTTL BM works with IW and OW to select the bus sizes for both write and read ports. See Table 1 for bus size
INPUT configuration.
D0–D35 Data Inputs HSTL-LVTTL Data inputs for a 36-, 18- or 9-bit bus. When in 18- or 9-bit mode, the unused input pins should be tied to GND.
INPUT
EF/OR Empty Flag/ HSTL-LVTTL In the IDT Standard mode, the EF function is selected. EF indicates whether or not the FIFO memory is empty.
Output Ready OUTPUT In FWFT mode, the OR function is selected. OR indicates whether or not there is valid data available at the
outputs.
ERCLK RCLK Echo HSTL-LVTTL Read clock Echo output, only available when the Read is setup for Synchronous mode.
OUTPUT
EREN Read Enable Echo HSTL-LVTTL Read Enable Echo output, only available when the Read is setup for Synchronous mode.
OUTPUT
FF/IR Full Flag/ HSTL-LVTTL In the IDT Standard mode, the FF function is selected. FF indicates whether or not the FIFO memory is
Input Ready OUTPUT full. In the FWFT mode, the IR function is selected. IR indicates whether or not there is space available for
writing to the FIFO memory.
FSEL0(1) Flag Select Bit 0 LVTTL During Master Reset, this input along with FSEL1 and the LD pin, will select the default offset values for the
INPUT programmable flags PAE and PAF. There are up to eight possible settings available.
FSEL1(1) Flag Select Bit 1 LVTTL During Master Reset, this input along with FSEL0 and the LD pin will select the default offset values for the
INPUT programmable flags PAE and PAF. There are up to eight possible settings available.
FWFT/ First Word Fall HSTL-LVTTL During Master Reset, selects First Word Fall Through or IDT Standard mode. After Master Reset, this pin
SI Through/Serial In INPUT functions as a serial input for loading offset registers. If Asynchronous operation of the read port has been
selected then the FIFO must be set-up in IDT Standard mode.
HF Half-Full Flag HSTL-LVTTL HF indicates whether the FIFO memory is more or less than half-full.
OUTPUT
IP(1) Interspersed Parity LVTTL During Master Reset, a LOW on IP will select Non-Interspersed Parity mode. A HIGH will select Interspersed
INPUT Parity mode.
IW(1) Input Width LVTTL This pin, along with OW and BM, selects the bus width of the write port. See Table 1 for bus size configuration.
INPUT
LD Load HSTL-LVTTL This is a dual purpose pin. During Master Reset, the state of the LD input along with FSEL0 and FSEL1,
INPUT determines one of eight default offset values for the PAE and PAF flags, along with the method by which these
offset registers can be programmed, parallel or serial (see Table 2). After Master Reset, this pin enables writing
to and reading from the offset registers.
MARK Mark for Retransmit HSTL-LVTTL When this pin is asserted the current location of the read pointer will be marked. Any subsequent Retransmit
INPUT operation will reset the read pointer to this position.
MRS Master Reset HSTL-LVTTL MRS initializes the read and write pointers to zero and sets the output register to all zeroes. During Master
INPUT Reset, the FIFO is configured for either FWFT or IDT Standard mode, Bus-Matching configurations,
Synchronous/Asynchronous operation of the read or write port, one of eight programmable flag default settings,
serial or parallel programming of the offset settings, Big-Endian/Little-Endian format, zero latency timing mode,
interspersed parity, and synchronous versus asynchronous programmable flag timing modes.
OE Output Enable HSTL-LVTTL OE provides Asynchronous three-state control of the data outputs, Qn. During a Master or Partial Reset the
INPUT OE input is the only input that provide High-Impedance control of the data outputs.
OW(1) Output Width LVTTL This pin, along with IW and BM, selects the bus width of the read port. See Table 1 for bus size configuration.
INPUT
PAE Programmable HSTL-LVTTL PAE goes LOW if the number of words in the FIFO memory is less than offset n, which is stored in the Empty
Almost-Empty Flag OUTPUT Offset register. PAE goes HIGH if the number of words in the FIFO memory is greater than or equal to offset n.
PAF Programmable HSTL-LVTTL PAF goes HIGH if the number of free locations in the FIFO memory is more than offset m, which is stored in
Almost-Full Flag OUTPUT the Full Offset register. PAF goes LOW if the number of free locations in the FIFO memory is less than or equal
to m.
NOTE:
1. Inputs should not change state after Master Reset.
8
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
Symbol Name I/O TYPE Description
PFM(1) Programmable LVTTL During Master Reset, a LOW on PFM will select Asynchronous Programmable flag timing mode. A HIGH on
Flag Mode INPUT PFM will select Synchronous Programmable flag timing mode.
PRS Partial Reset HSTL-LVTTL PRS initializes the read and write pointers to zero and sets the output register to all zeroes. During Partial Reset,
INPUT the existing mode (IDT or FWFT), programming method (serial or parallel), and programmable flag settings
are all retained.
Q0–Q35 Data Outputs HSTL-LVTTL Data outputs for an 36-, 18- or 9-bit bus. When in 18- or 9-bit mode, any unused output pins should not be
OUTPUT connected. Outputs are not 5V tolerant regardless of the state of OE and RCS.
RCLK/ Read Clock/ HSTL-LVTTL If Synchronous operation of the read port has been selected, when enabled by REN, the rising edge of RCLK
RD Read Stobe INPUT reads data from the FIFO memory and offsets from the programmable registers. If LD is LOW, the values loaded
into the offset registers is output on a rising edge of RCLK.If Asynchronous operation of the read port has been
selected, a rising edge on RD reads data from the FIFO in an Asynchronous manner. REN should be tied LOW.
RCS Read Chip Select HSTL-LVTTL RCS provides synchronous control of the read port and output impedance of Qn, synchronous to RCLK. During
INPUT a Master Reset or Partial Reset the RCS input is don’t care, if OE is LOW the data outputs will be Low-Impedance
regardless of RCS.
REN Read Enable HSTL-LVTTL If Synchronous operation of the read port has been selected, REN enablesRCLK for reading data from the
INPUT FIFO memory and offset registers. If Asynchronous operation of the read port has been selected, the REN
input should be tied LOW.
RHSTL(1) Read Port HSTL LVTTL This pin is used to select HSTL or 2.5v LVTTL outputs for the FIFO. If HSTL or eHSTL outputs are
Select INPUT required, this input must be tied HIGH. Otherwise it should be tied LOW.
RT Retransmit HSTL-LVTTL RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets the EF flag to LOW (OR to HIGH
INPUT in FWFT mode) and doesn’t disturb the write pointer, programming method, existing timing mode orprogrammable
flag settings. If a mark has been set via the MARK input pin, then the read pointer will jump to the ‘mark’ location.
SCLK Serial Clock HSTL-LVTTL A rising edge on SCLK will clock the serial data present on the SI input into the offset registers providing that
INPUT SEN is enabled.
SEN Serial Enable HSTL-LVTTL SEN enables serial loading of programmable flag offsets.
INPUT
SHSTL System HSTL LVTTL All inputs not associated with the write or read port can be selected for HSTL operation via the SHSTL input.
Select INPUT
TCK(2) JTAG Clock HSTL-LVTTL Clock input for JTAG function. TMS and TDI are sampled on the rising edge of TCK. Data is output on
INPUT TDO on the falling edge.
TRST(2) JTAG Reset HSTL-LVTTL TRST is an asynchronous reset pin for the JTAG controller.
INPUT
TMS JTAG Mode HSTL-LVTTL TMS is a serial input pin. Bits are serially loaded on the rising edge of TCK, which selects 1 of 5 modes of
Select INPUT operation for the JTAG boundary scan.
TDI Test Data Input HSTL-LVTTL During JTAG boundary scan operation test data is serially loaded via TDI on the rising edge of TCK.
INPUT This is also the data for the Instruction Register, ID Register and Bypass Register.
TDO Test Data Output HSTL-LVTTL During JTAG boundary scan operation test data is serially output via TDO on the falling edge of TCK.
OUTPUT This output is in High-Z except when shifting, while in SHIFT-DR and SHIFT-IR controller states.
WEN Write Enable HSTL-LVTTL When Synchronous operation of the write port has been selected, WEN enables WCLK for writing data into
INPUT theFIFO memory and offset registers. If Asynchronous operation of the write port has been selected, the
WEN input should be tied LOW.
WCS Write Chip Select HSTL-LVTTL The WCS pin can be regarded as a second WEN input, enabling/disabling write operations.
INPUT
WCLK/ Write Clock/ HSTL-LVTTL If Synchronous operation of the write port has been selected, when enabled by WEN, the rising edge of WCLK
WR Write Strobe INPUT writes data into the FIFO. If Asynchronous operation of the write port has been selected, WR writes data into
the FIFO on a rising edge in an Asynchronous manner, (WEN should be tied to its active state).
WHSTL(1) Write Port HSTL LVTTL This pin is used to select HSTL or 2.5V LVTTL inputs for the FIFO. If HSTL inputs are required, this input must
Select INPUT be tied HIGH. Otherwise it should be tied LOW.
Vcc +2.5v Supply I These are Vcc supply inputs and must be connected to the 2.5V supply rail.
GND Ground Pin I These are Ground pins an dmust be connected to the GND rail.
Vref Reference I This is a Voltage Reference input and must be connected to a voltage level determined from the table,
Voltage “Recommended DC Operating Conditions”. This provides the reference voltage when using HSTL class
inputs. If HSTL class inputs are not being used, this pin should be tied LOW.
VDDQ O/P Rail Voltage I This pin should be tied to the desired voltage rail for providing power to the output drivers.
PIN DESCRIPTION (CONTINUED)
NOTES:
1. Inputs should not change state after Master Reset.
2. If the JTAG feature is not being used, TCK and TRST should be tied LOW.
9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
Symbol Rating Commercial Unit
VTERM Terminal Voltage –0.5 to +3.6(2) V
with respect to GND
TSTG Storage Temperature –55 to +125 °C
IOUT DC Output Current –50 to +50 mA
Symbol Parameter Min. Typ. Max. Unit
VCC Supply Voltage 2.375 2.5 2.625 V
GND Supply Voltage 0 0 0 V
VIH Input High Voltage LVTTL 1.7 — 3.45 V
eHSTL VREF+0.2 — VDDQ+0.3 V
HSTL VREF+0.2 — VDDQ+0.3 V
VIL Input Low Voltage LVTTL -0.3 — 0.7 V
eHSTL -0.3 — VREF-0.2 V
HSTL -0.3 — VREF-0.2 V
VREF(1) Voltage Reference Input eHSTL 0.8 0.9 1.0 V
HSTL 0.68 0.75 0.9 V
TAOperating Temperature Commercial 0 — 70 °C
TAOperating Temperature Industrial -40 — 85 °C
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED DC OPERATING CONDITIONS
NOTES:
1 . Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. Compliant with JEDEC JESD8-5. VCC terminal only.
NOTE:
1. VREF is only required for HSTL or eHSTL inputs. VREF should be tied LOW for LVTTL operation.
2. Outputs are not 3.3V tolerant.
Symbol Parameter(1) Conditions Max. Unit
CIN(2,3) Input VIN = 0V 10(3) pF
Capacitance
COUT(1,2) Output VOUT = 0V 10 pF
Capacitance
CAPACITANCE (TA = +25°C, f = 1.0MHz)
NOTES:
1. With output deselected, (OE ≥ VIH).
2. Characterized values, not currently tested.
3. CIN for Vref is 20pF.
10
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 2.5V ± 0.125V, T A = 0°C to +70°C;Industrial: VCC = 2.5V ± 0.125V, TA = -40°C to +85°C)
Symbol Parameter Min. Max. Unit
ILI Input Leakage Current –10 10 µA
ILO Output Leakage Current –10 10 µA
VOH(5) Output Logic “1” Voltage, IOH = –8 mA @VDDQ = 2.5V ± 0.125V (LVTTL) VDDQ -0.4 — V
IOH = –8 mA @VDDQ = 1.8V ± 0.1V (eHSTL) VDDQ -0.4 — V
IOH = –8 mA @VDDQ = 1.5V ± 0.1V (HSTL) VDDQ -0.4 — V
VOL Output Logic “0” Voltage, IOL = 8 mA @VDDQ = 2.5V ± 0.125V (LVTTL) — 0.4V V
IOL = 8 mA @VDDQ = 1.8V ± 0.1V (eHSTL) — 0.4V V
IOL = 8 mA @VDDQ = 1.5V ± 0.1V (HSTL) — 0.4V V
ICC1(1,2) Active VCC Current (VCC = 2.5V) I/O = LVTTL — 40 mA
I/O = HSTL — 70 mA
I/O = eHSTL — 70 mA
ICC2(1) Standby VCC Current (VCC = 2.5V) I/O = LVTTL — 10 mA
I/O = HSTL — 50 mA
I/O = eHSTL — 50 mA
NOTES:
1 . Both WCLK and RCLK toggling at 20MHz. Data inputs toggling at 10MHz. WCS = HIGH, REN or RCS = HIGH.
2. For the IDT72T36105/72T36115/72T36125, typical ICC1 calculation (with data outputs in Low-Impedance):
for LVTTL I/O ICC1 (mA) = 1.3 x fs, fs = WCLK = RCLK frequency (in MHz)
for HSTL or eHSTL I/O ICC1 (mA) = 30 + (1.3 x fs), fs = WCLK = RCLK frequency (in MHz)
For the IDT72T3645/72T3655/72T3665/72T3675/72T3685/72T3695, typical ICC1 calculation (with data outputs in Low-Impedance):
for LVTTL I/O ICC1 (mA) = 0.7mA x fs, fs = WCLK = RCLK frequency (in MHz)
for HSTL or eHSTL I/O ICC1 (mA) = 30 + (0.7 x fs), fs = WCLK = RCLK frequency (in MHz).
3. For all devices, typical IDDQ calculation: with data outputs in High-Impedance: IDDQ (mA) = 0.15 x fs, fs = WCLK = RCLK frequency (in MHz)
with data outputs in Low-Impedance: IDDQ (mA) = (CL x VDDQ x fs x N)/2000
fs = WCLK = RCLK frequency (in MHz), VDDQ = 2.5V for LVTTL; 1.5V for HSTL; 1.8V for eHSTL, CL = capacitive load (pf), tA = 25°C,
N = Number of outputs switching.
4 . Total Power consumed: PT = (VCC x ICC) + VDDQ x IDDQ).
5. Outputs are not 3.3V tolerant.
11
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
AC ELECTRICAL CHARACTERISTICS(1)
— SYNCHRONOUS TIMING
(Commercial: VCC = 2.5V ± 5%, TA = 0°C to +70°C;Industrial: VCC = 2.5V ± 5%, TA = -40°C to +85 °C)
NOTES:
1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.
2. Pulse widths less than minimum values are not allowed.
3. Values guaranteed by design, not currently tested.
4. Industrial temperature range product for the 5ns speed grade is available as a standard device. All other speed grades are available by special order.
P R E L I M I N A R Y
Commercial Com’l & Ind’l Commercial
IDT72T3645L4-4 IDT72T3645L5 IDT72T3645L6-7 IDT72T3645L10
IDT72T3655L4-4 IDT72T3655L5 IDT72T3655L6-7 IDT72T3655L10
IDT72T3665L4-4 IDT72T3665L5 IDT72T3665L6-7 IDT72T3665L10
IDT72T3675L4-4 IDT72T3675L5 IDT72T3675L6-7 IDT72T3675L10
IDT72T3685L4-4 IDT72T3685L5 IDT72T3685L6-7 IDT72T3685L10
IDT72T3695L4-4 IDT72T3695L5 IDT72T3695L6-7 IDT72T3695L10
IDT72T36105L4-4 IDT72T36105L5 IDT72T36105L6-7 IDT72T36105L10
IDT72T36115L4-4 IDT72T36115L5 IDT72T36115L6-7 IDT72T36115L10
IDT72T36125L4-4 IDT72T36125L5 IDT72T36125L6-7 IDT72T36125L10
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
fCClock Cycle Frequency (Synchronous) — 2 25 — 200 — 1 50 1 00 MHz
tAData Access Time 0.6 3.4 0.6 3.6 0.6 3.8 0.6 4.5 ns
tCLK Clock Cycle Time 4.44 — 5 — 6.7 — 10 — ns
tCLKH Clock High Time 2.0 — 2. 3 — 2 .8 — 4. 5 — n s
tCLKL Clock Low Time 2. 0 — 2. 3 — 2. 8 — 4. 5 — ns
tDS Data Setup Time 1.2 — 1.5 — 2.0 — 3.0 — ns
tDH Data Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns
tENS Enable Setup Time 1.2 — 1.5 — 2.0 — 3.0 — ns
tENH Enable Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns
tLDS Load Setup Time 1.2 — 1.5 — 2.0 — 3.0 — ns
tLDH Load Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns
tWCSS WCS setup time 1.2 — 1.5 — 2.0 — 3.0 — ns
tWCSH WCS hold time 0.5 — 0.5 — 0.5 — 0.5 — ns
fSClock Cycle Frequency (SCLK) — 10 — 10 — 10 — 10 M Hz
tSCLK Serial Clock Cycle 100 — 100 — 100 — 100 — ns
tSCKH Serial Clock High 45 — 45 — 45 — 45 — n s
tSCKL Serial Clock Low 45 — 45 — 45 — 45 — ns
tSDS Serial Data In Setup 15 — 15 — 15 — 15 — ns
tSDH Serial Data In Hold 5 — 5 — 5 — 5 — ns
tSENS Serial Enable Setup 5 — 5 — 5 — 5 — ns
tSENH Serial Enable Hold 5 — 5 — 5 — 5 — ns
tRS Reset Pulse Width(2) 30 — 30 — 30 — 30 — ns
tRSS Reset Setup Time 15 — 15 — 15 — 15 — ns
tHRSS HSTL Reset Setup Time 4 — 4 — 4 — 4 — µs
tRSR Reset Recovery Time 1 0 — 10 — 10 — 10 — ns
tRSF Reset to Flag and Output Time — 10 — 12 — 15 — 15 ns
tWFF Write Clock to FF or IR — 3.4 — 3.6 — 3.8 — 4.5 ns
tREF Read Clock to EF or OR — 3.4 — 3.6 — 3.8 — 4.5 ns
tPAFS Write Clock to Synchronous Programmable Almost-Full Flag — 3.4 — 3.6 — 3.8 — 4.5 ns
tPAES Read Clock to Synchronous Programmable Almost-Empty Flag — 3.4 — 3.6 — 3.8 — 4.5 ns
tERCLK RCLK to Echo RCLK output — 3. 8 — 4 — 4. 3 — 5 n s
tCLKEN RCLK to Echo REN output — 3. 4 — 3.6 — 3. 8 — 4. 5 ns
tRCSLZ RCLK to Active from High-Z(3) — 3.4 — 3.6 — 3.8 — 4.5 ns
tRCSHZ RCLK to High-Z(3) — 3.4 — 3.6 — 3.8 — 4.5 ns
tSKEW1 Skew time between RCLK and WCLK for EF/OR and FF/IR 3.5— 4 —5 —7 —ns
tSKEW2 Skew time between RCLK and WCLK for PAE and PAF 4—5—6 —8—ns
12
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
P R E L I M I N A R Y
AC ELECTRICAL CHARACTERISTICS — ASYNCHRONOUS TIMING
(Commercial: VCC = 2.5V ± 5%, TA = 0°C to +70°C;Industrial: VCC = 2.5V ± 5%, TA = -40°C to +85°C)
Commercial Com’l & Ind’l Commercial
IDT72T3645L4-4 IDT72T3645L5 IDT72T3645L6-7 IDT72T3645L10
IDT72T3655L4-4 IDT72T3655L5 IDT72T3655L6-7 IDT72T3655L10
IDT72T3665L4-4 IDT72T3665L5 IDT72T3665L6-7 IDT72T3665L10
IDT72T3675L4-4 IDT72T3675L5 IDT72T3675L6-7 IDT72T3675L10
IDT72T3685L4-4 IDT72T3685L5 IDT72T3685L6-7 IDT72T3685L10
IDT72T3695L4-4 IDT72T3695L5 IDT72T3695L6-7 IDT72T3695L10
IDT72T36105L4-4 IDT72T36105L5 IDT72T36105L6-7 IDT72T36105L10
IDT72T36115L4-4 IDT72T36115L5 IDT72T36115L6-7 IDT72T36115L10
IDT72T36125L4-4 IDT72T36125L5 IDT72T36125L6-7 IDT72T36125L10
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
fACycle Frequency (Asynchronous) — 1 0 0 — 8 3 — 6 6 — 50 MHz
tAA Data Access Time 0.6 8 0.6 10 0.6 1 2 0.6 14 ns
tCYC Cycle Time 10 — 12 — 15 — 20 — ns
tCYH Cycle HIGH Time 4.5 — 5 — 7 — 8 — ns
tCYL Cycle LOW Time 4.5 — 5 — 7 — 8 — ns
tRPE Read Pulse after EF HIGH 8 — 10 — 12 — 14 — ns
tFFA Clock to Asynchronous FF —8—10—12—14ns
tEFA Clock to Asynchronous EF —8—10—12—14ns
tPAFA Clock to Asynchronous Programmable Almost-Full Flag — 8 — 10 — 12 — 1 4 ns
tPAEA Clock to Asynchronous Programmable Almost-Empty Flag — 8 — 1 0 — 1 2 — 14 ns
tOLZ Output Enable to Output in Low Z(1) 0—0—0— 0—ns
tOE Output Enable to Output Valid — 3.4 — 3.6 — 3.8 — 4.5 ns
tOHZ Output Enable to Output in High Z(1) — 3.4 — 3.6 — 3.8 — 4.5 ns
tHF Clock to HF —8—10—12—14ns
NOTES:
1. Values guaranteed by design, not currently tested.
2. Industrial temperature range product for the 5ns speed grade is available as a standard device. All other speed grades are available by special order.
13
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
Input Pulse Levels 0.25 to 1.25V
Input Rise/Fall Times 0.4ns
Input Timing Reference Levels 0.75
Output Reference Levels VDDQ/2
HSTL
1.5V AC TEST CONDITIONS
Figure 2b. Lumped Capacitive Load, Typical Derating
AC TEST LOADS
Figure 2a. AC Test Load
Input Pulse Levels 0.4 to 1.4V
Input Rise/Fall Times 0.4ns
Input Timing Reference Levels 0.9
Output Reference Levels VDDQ/2
EXTENDED HSTL
1.8V AC TEST CONDITIONS
Input Pulse Levels GND to 2.5V
Input Rise/Fall Times 1ns
Input Timing Reference Levels VCC/2
Output Reference Levels VDDQ/2
2.5V LVTTL
2.5V AC TEST CONDITIONS
5907 drw04
50
Ω
V
DDQ
/2
I/O Z
0
= 50
Ω
5907 drw04a
6
5
4
3
2
1
20 30 50 80 100 200
Capacitance (pF)
tCD
(Typical, ns)
NOTE:
1. VDDQ = 1.5V±.
NOTE:
1. VDDQ = 1.8V±.
NOTE:
1. For LVTTL VCC = VDDQ.
14
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
OUTPUT ENABLE & DISABLE TIMING
VIH
OE
VIL
t
OE &
t
OLZ
V
CC
2
V
CC
2
100mV
100mV
t
OHZ
100mV
100mV
Output
Normally
LOW
Output
Normally
HIGH
VOL
VOH
V
CC
2
V
CC
2
5907 drw04b
Output
Enable
Output
Disable
READ CHIP SELECT ENABLE & DISABLE TIMING
V
IH
RCS
V
IL
t
ENS
t
ENH
t
RCSLZ
RCLK
V
CC
2
V
CC
2
100mV
100mV
t
RCSHZ
100mV
100mV
Output
Normally
LOW
Output
Normally
HIGH
V
OL
V
OH
V
CC
2
V
CC
2
5907 drw04c
NOTES:
1. REN is HIGH.
2. RCS is LOW.
NOTES:
1. REN is HIGH.
2. OE is LOW.
15
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
FUNCTIONAL DESCRIPTION
TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH
(FWFT) MODE
The IDT72T3645/55/65/75/85/95/105/115/125 support two different tim-
ing modes of operation: IDT Standard mode or First Word Fall Through
(FWFT) mode. The selection of which mode will operate is determined during
Master Reset, by the state of the FWFT/SI input.
If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard mode
will be selected. This mode uses the Empty Flag (EF) to indicate whether or not
there are any words present in the FIFO. It also uses the Full Flag function (FF)
to indicate whether or not the FIFO has any free space for writing. In IDT
Standard mode, every word read from the FIFO, including the first, must be
requested using the Read Enable (REN) and RCLK.
If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will be
selected. This mode uses Output Ready (OR) to indicate whether or not there
is valid data at the data outputs (Qn). It also uses Input Ready (IR) to indicate
whether or not the FIFO has any free space for writing. In the FWFT mode, the
first word written to an empty FIFO goes directly to Qn after three RCLK rising
edges, REN = LOW is not necessary. Subsequent words must be accessed
using the Read Enable (REN) and RCLK.
Various signals, both input and output signals operate differently depending
on which timing mode is in effect.
IDT STANDARD MODE
In this mode, the status flags, FF, PAF, HF, PAE, and EF operate in the
manner outlined in Table 3. To write data into to the FIFO, Write Enable (WEN)
must be LOW. Data presented to the DATA IN lines will be clocked into the FIFO
on subsequent transitions of the Write Clock (WCLK). After the first write is
performed, the Empty Flag (EF) will go HIGH. Subsequent writes will continue
to fill up the FIFO. The Programmable Almost-Empty flag (PAE) will go HIGH
after n + 1 words have been loaded into the FIFO, where n is the empty offset
value. The default setting for these values are stated in the footnote of Table 2.
This parameter is also user programmable. See section on Programmable Flag
Offset Loading.
If one continued to write data into the FIFO, and we assumed no read
operations were taking place, the Half-Full flag (HF) would toggle to LOW once
the 513rd word for IDT72T3645, 1,025th word for IDT72T3655, 2,049th word
for IDT72T3665, 4,097th word for IDT72T3675, 8,193th word for the
IDT72T3685, 16,385th word for the IDT72T3695, 32,769th word for the
IDT72T36105, 65,537th word for the IDT72T36115 and 131,073rd word for
the IDT72T36125, respectively was written into the FIFO. Continuing to write
data into the FIFO will cause the Programmable Almost-Full flag (PAF) to go
LOW. Again, if no reads are performed, the PAF will go LOW after (1,024-m)
writes for the IDT72T3645, (2,048-m) writes for the IDT72T3655, (4,096-m)
writes for the IDT72T3665, (8,192-m) writes for the IDT72T3675, (16,384-m)
writes for the IDT72T3685, (32,768-m) writes for the IDT72T3695, (65,536-m)
writes for the IDT72T36105, (131,072-m) writes for the IDT72T36115 and
(262,144-m) writes for the IDT72T36125. The offset “m” is the full offset value.
The default setting for these values are stated in the footnote of Table 2. This
parameter is also user programmable. See section on Programmable Flag
Offset Loading.
When the FIFO is full, the Full Flag (FF) will go LOW, inhibiting further write
operations. If no reads are performed after a reset, FF will go LOW after D writes
to the FIFO. D = 1,024 writes for the IDT72T3645, 2,048 writes for the
IDT72T3655, 4,096 writes for the IDT72T3665, 8,192 writes for the IDT72T3675,
16,384 writes for the IDT72T3685, 32,768 writes for the IDT72T3695, 65,536
writes for the IDT72T36105, 131,072 writes for the IDT72T36115 and 262,144
writes for the IDT72T36125, respectively.
If the FIFO is full, the first read operation will cause FF to go HIGH.
Subsequent read operations will cause PAF and HF to go HIGH at the conditions
described in Table 3. If further read operations occur, without write operations,
PAE will go LOW when there are n words in the FIFO, where n is the empty
offset value. Continuing read operations will cause the FIFO to become empty.
When the last word has been read from the FIFO, the EF will go LOW inhibiting
further read operations. REN is ignored when the FIFO is empty.
When configured in IDT Standard mode, the EF and FF outputs are double
register-buffered outputs.
Relevant timing diagrams for IDT Standard mode can be found in Figure
11, 12, 13 and 18.
FIRST WORD FALL THROUGH MODE (FWFT)
In this mode, the status flags, IR, PAF, HF, PAE, and OR operate in the
manner outlined in Table 4. To write data into to the FIFO, WEN must be LOW.
Data presented to the DATA IN lines will be clocked into the FIFO on subsequent
transitions of WCLK. After the first write is performed, the Output Ready (OR)
flag will go LOW. Subsequent writes will continue to fill up the FIFO. PAE will go
HIGH after n + 2 words have been loaded into the FIFO, where n is the empty
offset value. The default setting for these values are stated in the footnote of
Table 2. This parameter is also user programmable. See section on Program-
mable Flag Offset Loading.
If one continued to write data into the FIFO, and we assumed no read
operations were taking place, the HF would toggle to LOW once the 514th word
for the IDT72T3645, 1,026th word for the IDT72T3655, 2,050th word for the
IDT72T3665, 4,098th word for the IDT72T3675, 8,194th word for the
IDT72T3685, 16,386th word for the IDT72T3695, 32,770th word for the
IDT72T36105, 65,538th word for the IDT72T36115 and 131,074th word for
the IDT72T36125, respectively was written into the FIFO. Continuing to write
data into the FIFO will cause the PAF to go LOW. Again, if no reads are
performed, the PAF will goLOW after (1,025-m) writes for the IDT72T3645,
(2,049-m) writes for the IDT72T3655, (4,097-m) writes for the IDT72T3665
and (8,193-m) writes for the IDT72T3675, (16,385-m) writes for the IDT72T3685,
(32,769-m) writes for the IDT72T3695, (65,537-m) writes for the IDT72T36105,
(131,073-m) writes for the IDT72T36115 and (262,145-m) writes for the
IDT72T36125, where m is the full offset value. The default setting for these values
are stated in the footnote of Table 2.
When the FIFO is full, the Input Ready (IR) flag will go HIGH, inhibiting further
write operations. If no reads are performed after a reset, IR will go HIGH after
D writes to the FIFO. D = 1,025 writes for the IDT72T3645, 2,049 writes for
the IDT72T3655, 4,097 writes for the IDT72T3665 and 8,193 writes for the
IDT72T3675,16,385 writes for the IDT72T3685, 32,769 writes for the
IDT72T3695, 65,537 writes for the IDT72T36105, 131,073 writes for the
IDT72T36115 and 262,145 writes for the IDT72T36125, respectively. Note
that the additional word in FWFT mode is due to the capacity of the memory plus
output register.
If the FIFO is full, the first read operation will cause the IR flag to go LOW.
Subsequent read operations will cause the PAF and HF to go HIGH at the
conditions described in Table 4. If further read operations occur, without write
operations, the PAE will go LOW when there are n + 1 words in the FIFO, where
n is the empty offset value. Continuing read operations will cause the FIFO to
become empty. When the last word has been read from the FIFO, OR will go
HIGH inhibiting further read operations. REN is ignored when the FIFO is empty.
When configured in FWFT mode, the OR flag output is triple register-
buffered, and the IR flag output is double register-buffered.
Relevant timing diagrams for FWFT mode can be found in Figure 14, 15,
16 and 19.
16
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
PROGRAMMING FLAG OFFSETS
Full and Empty Flag offset values are user programmable. The IDT72T3645/
72T3655/72T3665/72T3675/72T3685/72T3695/72T36105/72T36115/
72T36125 have internal registers for these offsets. There are eight default offset
values selectable during Master Reset. These offset values are shown in Table
2. Offset values can also be programmed into the FIFO in one of two ways; serial
or parallel loading method. The selection of the loading method is done using
the LD (Load) pin. During Master Reset, the state of the LD input determines
whether serial or parallel flag offset programming is enabled. A HIGH on LD
during Master Reset selects serial loading of offset values. A LOW on LD during
Master Reset selects parallel loading of offset values.
In addition to loading offset values into the FIFO, it is also possible to read
the current offset values. Offset values can be read via the parallel output port
Q0-Qn, regardless of the programming mode selected (serial or parallel). It is
not possible to read the offset values in serial fashion.
Figure 3, Programmable Flag Offset Programming Sequence, summaries
the control pins and sequence for both serial and parallel programming modes.
For a more detailed description, see discussion that follows.
The offset registers may be programmed (and reprogrammed) any time
after Master Reset, regardless of whether serial or parallel programming has
been selected. Valid programming ranges are from 0 to D-1.
SYNCHRONOUS vs ASYNCHRONOUS PROGRAMMABLE FLAG
TIMING SELECTION
The IDT72T3645/72T3655/72T3665/72T3675/72T3685/72T3695/
72T36105/72T36115/72T36125 can be configured during the Master Reset
cycle with either synchronous or asynchronous timing for PAF and PAE flags
by use of the PFM pin.
If synchronous PAF/PAE configuration is selected (PFM, HIGH during
MRS), the PAF is asserted and updated on the rising edge of WCLK only and
not RCLK. Similarly, PAE is asserted and updated on the rising edge of RCLK
only and not WCLK. For detail timing diagrams, see Figure 23 for synchronous
PAF timing and Figure 24 for synchronous PAE timing.
If asynchronous PAF/PAE configuration is selected (PFM, LOW during
MRS), the PAF is asserted LOW on the LOW-to-HIGH transition of WCLK and
PAF is reset to HIGH on the LOW-to-HIGH transition of RCLK. Similarly, PAE
is asserted LOW on the LOW-to-HIGH transition of RCLK. PAE is reset to HIGH
on the LOW-to-HIGH transition of WCLK. For detail timing diagrams, see
Figure 25 for asynchronous PAF timing and Figure 26 for asynchronous PAE
timing.
IDT72T3645, 72T3655
LD FSEL1 FSEL0 Offsets n,m
LH L511
L L H 255
L L L 127
LHH63
HL L31
HH L15
HLH7
HH H3
LD FSEL1 FSEL0 Program Mode
H X X Serial(3)
L X X Parallel(4)
IDT72T3665,72T3675,72T3685,72T3695, 72T36105,
72T361 15, 72T36125
LD FSEL1 FSEL0 Offsets n,m
H L L 1,023
LH L511
L L H 255
L L L 127
LHH63
HH L31
HLH15
HH H7
LD FSEL1 FSEL0 Program Mode
H X X Serial(3)
L X X Parallel(4)
TABLE 2 — DEFAULT PROGRAMMABLE
FLAG OFFSETS
NOTES:
1. n = empty offset for PAE.
2 . m = full offset for PAF.
3. As well as selecting serial programming mode, one of the default values will also
be loaded depending on the state of FSEL0 & FSEL1.
4. As well as selecting parallel programming mode, one of the default values will
also be loaded depending on the state of FSEL0 & FSEL1.
17
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
IDT72T3645 IDT72T3655
0
1 to n (1)
(n+1) to 1,024
1,025 to (2048-(m+1))
(2048-m) to 2,047
2,048
0
1 to n (1)
(n+1) to 512
513 to (1,024-(m+1))
(1024-m) to 1,023
1,024
IDT72T3665
0
1 to n (1)
(n+1) to 2,048
2,049 to (4,096-(m+1))
(4,096-m) to 4,095
4,096
TABLE 3 STATUS FLAGS FOR IDT STANDARD MODE
IDT72T3645 IDT72T3655
00 0
1 to n+1 1 to n+1 1 to n+1
(n+2) to 1,025 (n+2) to 2,049 (n+2) to 4,097
1,026 to (2,049-(m+1)) 2,050 to (4,097-(m+1)) 4,098 to (8,193-(m+1))
(2,049-m) to 2,048 (4,097-m) to 4,096 (8,193-m) to 8,192
2,049 4,097 8,193
IDT72T3665 IDT72T3675
0
1 to n+1
(n+2) to 513
514 to (1,025-(m+1))
(1,025-m) to 1,024
1,025
IR PAF HF PAE OR
LHHL H
LHHL L
LHHHL
LHLH L
LLLH L
HLLH L
Number of
Words in
FIFO
TABLE 4 STATUS FLAGS FOR FWFT MODE
FF PAF HF PAE EF
HHHL L
HHHL H
HHHHH
HHL HH
HLLHH
LLLHH
5907 drw05
0
1 to n+1
(n+2) to 8,193
8,194 to (16,385-(m+1))
(16,385-m) to 16,384
16,385
IDT72T3685
IDT72T3675
0
1 to n
(1)
(n+1) to 4,096
4,097 to (8,192-(m+1))
(8,192-m) to 8,191
8,192
0
1 to n (
1)
(n+1) to 8,192
8,193 to (16,384-(m+1))
(16,384-m) to 16,383
16,384
IDT72T3685
Number of
Words in
FIFO
IDT72T36105
0
1 to n
(1)
(n+1) to 32,768
32,769 to (65,536-(m+1))
(65,536-m) to 65,535
65,536
IDT72T36115
0
1 to n
(1)
(n+1) to 65,536
65,537 to (131,072-(m+1))
(131,072-m) to 131,071
131,072
FF PAF HF PAE EF
HHHLL
HHHLH
HHHHH
HH L HH
HLLHH
LLLHH
IDT72T36125
0
1 to n
(1)
(n+1) to 131,072
131,073 to (262,144-(m+1))
262,144
Number of
Words in
FIFO
0
1 to n
(1)
(n+1) to 16,384
16,385 to (32,768-(m+1))
(32,768-m) to 32,767
32,768
IDT72T3695
(262,144-m) to 262,143
00 0
1 to n+1 1 to n+1 1 to n+1
IR PAF HF PAE OR
LHHL H
LHHL L
LHHHL
LHLH L
LLLH L
HLLH L
0
1 to n+1
(n+2) to 16,385
16,386 to (32,769-(m+1))
(32,769-m) to 32,768
32,769
IDT72T3695
Number of
Words in
FIFO
(n+2) to 32,769
32,770 to (65,537-(m+1))
(65,537-m) to 65,536
65,537
(n+2) to 65,537
65,538 to (131,073-(m+1))
(131,073-m) to 131,072
131,073
(n+2) to 131,073
131,074 to (262,145-(m+1))
262,145
(262,145-m) to 262,144
IDT72T36105 IDT72T36115 IDT72T36125
NOTE:
1. See table 2 for values for n, m.
NOTE:
1. See table 2 for values for n, m.