NB100LVEP91DWG - ON SEMICONDUCTOR

July, 2008 − Rev. 18

1Publication Order Number:

NB100LVEP91/D

NB100LVEP91

2.5 V/3.3 V Any Level

Positive Input to

-2.5 V/-3.3 V LVNECL

Output Translator

Description

The NB100LVEP91 is a triple any level positive input to NECL

output translator. The device accepts LVPECL, LVTTL, LVCMOS,

HSTL, CML or LVDS signals, and translates them to differential

LVNECL output signals (−2.5 V / −3.3 V).

To accomplish the level translation the LVEP91 requires three

power rails. The VCC pins should be connected to the positive power

supply, and the VEE pin should be connected to the negative power

supply. The GND pins are connected to the system ground plane. Both

VEE and VCC should be bypassed to ground via 0.01 mF capacitors.

Under open input conditions, the D input will be biased at VCC/2

and the D input will be pulled to GND. These conditions will force the

Q outputs to a low state, and Q outputs to a high state, which will

ensure stability.

The VBB pin, an internally generated voltage supply, is available to

this device only. For single-ended input conditions, the unused

differential input is connected to VBB as a switching reference voltage.

VBB may also rebias AC coupled inputs. When used, decouple VBB

and VCC via a 0.01 mF capacitor and limit current sourcing or sinking

to 0.5 mA. When not used, VBB should be left open.

Features

•Maximum Input Clock Frequency > 2.0 GHz Typical

•Maximum Input Data Rate > 2.0 Gb/s Typical

•500 ps Typical Propagation Delay

•Operating Range: VCC = 2.375 V to 3.8 V;

VEE = −2.375 V to −3.8 V; GND = 0 V

•Q Output will Default LOW with Inputs Open or at GND

•Pb−Free Packages are Available*

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

MARKING DIAGRAMS*

*For additional marking information, refer to

Application Note AND8002/D.

SO−20 WB

DW SUFFIX

CASE 751D

A = Assembly Location

WL, L = Wafer Lot

YY, Y = Year

WW, W = Work Week

G or G= Pb−Free Package

N100

VP91

ALYWG

24 PIN QFN

MN SUFFIX

CASE 485L

24 1

See detailed ordering and shipping information in the package

dimensions section on page 8 of this data sheet.

ORDERING INFORMATION

NB100LVEP91

AWLYYWWG

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(Note: Microdot may be in either location)

NB100LVEP91

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VEE

VCC

Figure 1. Logic Diagram

GND

VBB

Positive Level

Input NECL Output

Table 1. PIN DESCRIPTION

Name I/O

Default

State Description

SOIC QFN

1, 20 3, 4, 12 VCC − − Positive Supply Voltage. All VCC Pins must be Externally

Connected to Power Supply to Guarantee Proper Opera-

tion.

10 15, 16 VEE − − Negative Supply Voltage. All VEE Pins must be Externally

Connected to Power Supply to Guarantee Proper Opera-

tion.

14, 17 19, 20, 23,

GND − − Ground.

4, 7 7, 11 VBB − − ECL Reference Voltage Output

2, 5, 8 5, 8, 13 D[0:2] LVPECL, LVDS, LVTTL,

LVCMOS, CML, HSTL Input

Low Noninverted Differential Inputs [0:2]. Internal 75 kW to GND.

3, 6, 9 6, 9, 14 D[0:2] LVPECL, LVDS,

LVTTL,LVCMOS, CML,

HSTL Input

High Inverted Differential Inputs [0:2]. Internal 75 kW to GND and

75 kW to VCC. When Inputs are Left Open They Default to

(VCC − GND) / 2.

19,16,13 2, 22, 18 Q[0:2] LVNECL Output −Noninverted Differential Outputs [0:2]. Typically Terminated

with 50 W to VTT = VCC − 2 V

18,15,12 1, 21, 17 Q[0:2] LVNECL Output −Inverted Differential Outputs [0:2]. Typically Terminated with

50 W to VTT = VCC − 2 V

11 10 NC − − No Connect. The NC Pin is NOT Electrically Connected to

the Die and may Safely be Connected to Any Voltage from

VEE to VCC.

N/A −EP −Exposed Pad. (Note 1)

1. The thermally conductive exposed pad on the package bottom (see case drawing) must be attached to a heat sinking conduit and may

only be electrically connected to VEE (not GND).

NB100LVEP91

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D1D1 D2

1718 16 15 14 13 12

43 56789

Q1 Q1 Q2 Q2 NC

VEE

1920

VCC Q0

D0 D2VCC VBB

NB100LVEP91

GNDGND

VBB

Figure 2. SOIC−20 Lead Pinout (Top View)*

VEE

GND

VCC

GND GND Q1

VBB

NCVBB VCC

GNDQ1

VEE

NB100LVEP91

Figure 3. QFN−24 Lead Pinout (Top View)*

789 1110

1924 23 22 2021

Exposed Pad

(EP)

*All VCC, VEE and GND pins must be externally connected to

a power supply. The thermally conductive exposed pad on the

package bottom (see case drawing) must be attached to a

sufficient heat−sinking conduit and may only be electronically

connected to VEE (not GND).

*All VCC, VEE and GND pins must be externally connected to

a power supply.

Table 2. ATTRIBUTES

Characteristics Value

Internal Input Pulldown Resistor (R1) 75 kW

Internal Input Pullup Resistor (R2) 75 kW

ESD Protection Human Body Model

Machine Model

Charged Device Model

> 2 kV

> 150 V

> 2 kV

Moisture Sensitivity (Note 2) Pb Pkg Pb−Free Pkg

SO−20 WB

QFN−24

Level 1

Level 3

Level 1

Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in

Transistor Count 446 Devices

Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

2. For additional information, see Application Note AND8003/D.

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Table 3. MAXIMUM RATINGS

Symbol Parameter Condition 1 Condition 2 Rating Unit

VCC Positive Power Supply GND = 0 V 3.8 to 0 V

VEE Negative Power Supply GND = 0 V −3.8 to 0 V

VIPositive Input Voltage GND = 0 V VI  VCC 3.8 to 0 V

VOP Operating Voltage GND = 0 V VCC − VEE 7.6 to 0 V

Iout Output Current Continuous

Surge

100

IBB PECL VBB Sink/Source ± 0.5 mA

TAOperating Temperature Range −40 to +85 °C

Tstg Storage Temperature Range −65 to +150 °C

qJA Thermal Resistance (Junction−to−Ambient)

JESD 51−3 (1S−Single Layer Test Board)

0 lfpm

500 lfpm

SOIC−20

°C/W

qJA Thermal Resistance (Junction−to−Ambient)

JESD 51−6 (2S2P Multilayer Test Board) with Filled Thermal Vias

0 lfpm

500 lfpm

QFN−24

°C/W

qJC Thermal Resistance (Junction−to−Case) Standard Board SOIC−20

QFN−24

30 to 35

°C/W

Tsol Wave Solder Pb

Pb−Free

225

°C

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

Table 4. DC CHARACTERISTICS POSITIVE INPUTS VCC = 2.5 V, VEE = −2.375 to −3.8 V, GND = 0 V (Note 3)

Symbol Characteristic

−40°C 25°C 85°C

Unit

Min Typ Max Min Typ Max Min Typ Max

ICC Positive Power Supply Current 10 14 20 10 14 20 10 14 20 mA

VIH Input HIGH Voltage (Single−Ended) 1335 VCC 1335 VCC 1335 VCC mV

VIL Input LOW Voltage (Single−Ended) GND 875 GND 875 GND 875 mV

VIHCMR Input HIGH Voltage Common Mode Range

(Differential Configuration) (Note 4)

0 2.5 0 2.5 0 2.5 V

IIH Input HIGH Current (@ VIH) 150 150 150 mA

IIL Input LOW Current (@ VIL)D

0.5

−150

0.5

−150

0.5

−150

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

3. Input parameters vary 1:1 with VCC. VCC can vary +1.3 V / −0.125 V.

4. VIHCMR min varies 1:1 with GND. VIHCMR max varies 1:1 with VCC.

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Table 5. DC CHARACTERISTICS POSITIVE INPUT VCC = 3.3 V; VEE = −2.375 V to −3.8 V; GND = 0 V (Note 5)

Symbol Characteristic

−40°C 25°C 85°C

Unit

Min Typ Max Min Typ Max Min Typ Max

ICC Positive Power Supply Current 10 16 24 10 16 24 10 16 24 mA

VIH Input HIGH Voltage (Single−Ended) 2135 VCC 2135 VCC 2135 VCC mV

VIL Input LOW Voltage (Single−Ended) GND 1675 GND 1675 GND 1675 mV

VBB PECL Output Voltage Reference 1775 1875 1975 1775 1875 1975 1775 1875 1975 mV

VIHCMR Input HIGH Voltage Common Mode Range

(Differential Configuration) (Note 6)

0 3.3 0 3.3 0 3.3 V

IIH Input HIGH Current (@ VIH) 150 150 150 mA

IIL Input LOW Current (@ VIL)D

0.5

−150

0.5

−150

0.5

−150

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

5. Input parameters vary 1:1 with VCC. VCC can vary +0.5 / −0.925 V.

6. VIHCMR min varies 1:1 with GND. VIHCMR max varies 1:1 with VCC.

Table 6. DC CHARACTERISTICS NECL OUTPUT VCC = 2.375 V to 3.8 V; VEE = −2.375 V to −3.8 V; GND = 0 V (Note 7)

Symbol Characteristic

−40°C 25°C 85°C

Unit

Min Typ Max Min Typ Max Min Typ Max

IEE Negative Power Supply Current 40 50 60 38 50 68 38 50 68 mA

VOH Output HIGH Voltage (Note 8) −1145 −1020 −895 −1145 −1020 −895 −1145 −1020 −895 mV

VOL Output LOW Voltage (Note 8) −1945 −1770 −1600 −1945 −1770 −1600 −1945 −1770 −1600 mV

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

7. Output parameters vary 1:1 with GND.

8. All loading with 50 W resistor to GND − 2.0 V.

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Table 7. AC CHARACTERISTICS VCC = 2.375 V to 3.8 V; VEE = −2.375 V to −3.8 V; GND = 0 V

Symbol Characteristic

−40°C 25°C 85°C

Unit

Min Typ Max Min Typ Max Min Typ Max

VOUTPP Output Voltage Amplitude fin v 1.0 GHz

(Figure 4) fin v 1.5 GHz

(Note 9) fin v 2.0 GHz

575

525

300

800

750

600

525

250

800

750

550

400

150

800

750

500

tPLH

tPHL0

Propagation Delay Differential

D to Q Single−Ended

375

300

500

450

600

650

375

300

500

450

600

675

400

300

550

500

650

750

tSKEW Pulse Skew (Note 10)

Output−to−Output (Note 11)

Part−to−Part (Diff) (Note 11)

125

105

125

105

150

tJITTER RMS Random Clock Jitter (Note 12) fin = 2.0 GHz

Peak−to−Peak Data Dependant Jitter fin = 2.0 Gb/s

(Note 13)

0.5

2.0 0.5

2.0 ps

VINPP Input Voltage Swing (Differential Configuration)

(Note 14)

200 800 1200 200 800 1200 200 800 1200 mV

tr, tfOutput Rise/Fall Times @ 50 MHz

(20% − 80%) Q, Q

75 150 250 75 150 250 75 150 275 ps

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

9. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to GND − 2.0 V. Input edge rates 150 ps (20% − 80%).

10.Pulse Skew = |tPLH − tPHL|

11. Skews are valid across specified voltage range, part−to−part skew is for a given temperature.

12.RMS Jitter with 50% Duty Cycle Input Clock Signal.

13.Peak−to−Peak Jitter with input NRZ PRBS 231−1 at 2.0 Gb/s.

14.Input voltage swing is a single−ended measurement operating in differential mode. The device has a DC gain of ≈50.

Figure 4. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs.

Input Frequency (fin) at Ambient Temperature (Typical)

INPUT FREQUENCY (GHz)

0.5 1.0 1.5 2.0 2.5

250

350

450

550

650

750

850

OUTPUT VOLTAGE AMPLITUDE

(mV)

RMS JITTER (ps)

9.0

8.0

7.0

6.0

5.0

4.0

3.0

2.0

1.0

RMS JITTER

AMP

Figure 5. AC Reference Measurement

tPHL

tPLH

VINPP = VIH(D) − VIL(D)

VOUTPP = VOH(Q) − VOL(Q)

NB100LVEP91

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Application Information

All NB100LVEP91 inputs can accept LVPECL, LVTTL,

LVCMOS, HSTL, CML, or LVDS signal levels. The

limitations for differential input signal (LVDS, HSTL,

LVPECL, or CML) are the minimum input swing of 150 mV

and the maximum input swing of 3.0 V. Within these

conditions, the input voltage can range from VCC to GND.

Examples interfaces are illustrated below in a 50 W

environment (Z = 50 W)

VEE

GND GND VEE

VCC VCC

GND

LVPECL

Driver

LVEP91

50 W

VTT = VCC − 2.0 V

50 W

VCC VCC

LVDS

Driver

LVEP91

100 W

Figure 6. Standard LVPECL Interface

VCC VCC

HSTL

Driver

LVEP91

50 W50 W

GND

VCC VCC

CML

Driver

LVEP91

50 W

VCC

50 W

Figure 7. Standard LVDS Interface

Figure 8. Standard HSTL Interface Figure 9. Standard 50 W Load CML Interface

GND VEE GND GND VEE

GND GND

VEE

GND VEE

GND GND

VCC VCC

LVTTL

Driver

LVEP91

1.5 V

Figure 10. Standard LVTTL Interface

VCC VCC

LVCMOS

Driver

LVEP91

Open

Figure 11. Standard LVCMOS Interface

(D will default to VCC/2 when left open.

A reference voltage of VCC/2 should be applied

to D input, if D is interfaced to CMOS signals.)

GND

(externally generated

reference voltage)

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ORDERING INFORMATION

Device Package Shipping†

NB100LVEP91DW SO−20 38 Units / Rail

NB100LVEP91DWG SO−20

(Pb−Free)

38 Units / Rail

NB100LVEP91DWR2 SO−20 1000 / Tape & Reel

NB100LVEP91DWR2G SO−20

(Pb−Free)

1000 / Tape & Reel

NB100LVEP91MN QFN−24 92 Units / Rail

NB100LVEP91MNG QFN−24

(Pb−Free)

92 Units / Rail

NB100LVEP91MNR2 QFN−24 3000 / Tape & Reel

NB100LVEP91MNR2G QFN−24

(Pb−Free)

3000 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

Figure 12. Typical Termination for Output Driver and Device Evaluation

(See Application Note AND8020/D − Termination of ECL Logic Devices.)

Driver

Device

Receiver

Device

Q D

Zo = 50 W

50 W50 W

VTT

VTT = GND − 2.0 V

Resource Reference of Application Notes

AN1405/D −ECL Clock Distribution Techniques

AN1406/D −Designing with PECL (ECL at +5.0 V)

AN1503/D −ECLinPSt I/O SPiCE Modeling Kit

AN1504/D −Metastability and the ECLinPS Family

AN1568/D −Interfacing Between LVDS and ECL

AN1672/D −The ECL Translator Guide

AND8001/D −Odd Number Counters Design

AND8002/D −Marking and Date Codes

AND8020/D −Termination of ECL Logic Devices

AND8066/D −Interfacing with ECLinPS

AND8090/D −AC Characteristics of ECL Devices

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PACKAGE DIMENSIONS

B20X

H10X

18X A1

SEATING

PLANE

hX 45_

0.25 M

0.25 S

DIM MIN MAX

MILLIMETERS

A2.35 2.65

A1 0.10 0.25

B0.35 0.49

C0.23 0.32

D12.65 12.95

E7.40 7.60

e1.27 BSC

H10.05 10.55

h0.25 0.75

L0.50 0.90

q0 7

NOTES:

1. DIMENSIONS ARE IN MILLIMETERS.

2. INTERPRET DIMENSIONS AND TOLERANCES

PER ASME Y14.5M, 1994.

3. DIMENSIONS D AND E DO NOT INCLUDE MOLD

PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

5. DIMENSION B DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE PROTRUSION

SHALL BE 0.13 TOTAL IN EXCESS OF B

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

SO−20 WB

CASE 751D−05

ISSUE G

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PACKAGE DIMENSIONS

QFN 24

MN SUFFIX

24 PIN QFN, 4x4

CASE 485L−01

ISSUE O

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME

Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED TERMINAL

AND IS MEASURED BETWEEN 0.25 AND 0.30 MM

FROM TERMINAL.

4. COPLANARITY APPLIES TO THE EXPOSED PAD

AS WELL AS THE TERMINALS.

SEATING

PLANE

0.15 C

PIN 1

IDENTIFICATION

2X 0.15 C

0.08 C

0.10 C

A1 C

DIM MIN MAX

MILLIMETERS

A0.80 1.00

A1 0.00 0.05

A2 0.60 0.80

A3 0.20 REF

b0.23 0.28

D4.00 BSC

D2 2.70 2.90

E4.00 BSC

E2 2.70 2.90

e0.50 BSC

L0.35 0.45

24X

0.10 B

0.05

REF

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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent

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PUBLICATION ORDERING INFORMATION

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Europe, Middle East and Africa Technical Support:

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Phone: 81−3−5773−3850

NB100LVEP91/D

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