July 2009 Doc ID 12266 Rev 6 1/37
1
VND5050J-E
VND5050K-E
Double channel high side driver
for automotive applications
Features
■Main
– Inrush current active management by
power limitation
– Very low standby current
– 3.0 V CMOS compatible input
– Optimized electromagnetic emission
– Very low electromagnetic susceptibility
– In compliance with the 2002/95/EC
European directive
■Diagnostic functions
– Open drain status output
– On-state open load detection
– Off-state open load detection
– Thermal shutdown indication
■Protections
– Undervoltage shutdown
– Overvoltage clamp
– Output stuck to VCC detection
– Load current limitation
– Self limiting of fast thermal transients
– Protection against loss of ground and loss
of VCC
– Thermal shutdown
– Reverse battery protection (see Figure 28)
– Electrostatic discharge protection
Applications
■All types of resistive, inductive and capacitive
loads
Description
The VND5050K-E and VND5050J-E are
monolithic devices made using
STMicroelectronics VIPower M0-5 technology.
they are intended for driving resistive or inductive
loads with one side connected to ground. Active
VCC pin voltage clamp protects the devices
against low energy spikes (see ISO7637 transient
compatibility table). The devices detect open load
condition both in on and off-state, when
STAT_DIS is left open or driven low. Output
shorted to VCC is detected in the off-state.
When STAT_DIS is driven high, STATUS pin is in
high impedance state.
Output current limitation protects the devices in
overload condition. In case of long overload
duration, the devices limit the dissipated power to
a safe level up to thermal shutdown intervention.
Thermal shutdown with automatic restart allows
the devices to recover normal operation as soon
as fault conditions disappear.
Max supply voltage VCC 41 V
Operating voltage range VCC 4.5 to 36 V
Max on-State resistance (per ch.)
RON 50 mΩ
Current limitation (typ) ILIMH 18 A
Off-state supply current IS2µA
(1)
1. Typical value with all loads connected.
PowerSSO-24PowerSSO-12
Table 1. Device summary
Package
Order code
Tube Tape and reel
PowerSSO-12 VND5050J-E VND5050JTR-E
PowerSSO-24 VND5050K-E VND5050KTR-E
www.st.com
Contents VND5050J-E / VND5050K-E
2/37 Doc ID 12266 Rev 6
Contents
1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 20
3.1.1 Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 20
3.1.2 Solution 2: a diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . 21
3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.3 Microcontroller I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.4 Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.5 Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . 23
4 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.1 PowerSSO-12™ thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.2 PowerSSO-24™ thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.1 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.2 PowerSSO-12™ package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.3 PowerSSO-24™ package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.4 PowerSSO-12™ packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.5 PowerSSO-24™ packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
VND5050J-E / VND5050K-E List of tables
Doc ID 12266 Rev 6 3/37
List of tables
Table 2. Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 3. Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 5. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 6. Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 7. Switching (VCC = 13V; Tj = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 8. Status pin (VSD=0V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 9. Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 10. Openload detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 11. Logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 12. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 13. Electrical transient requirements (part 1/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 14. Electrical transient requirements (part 2/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 15. Electrical transient requirements (part 3/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 16. PowerSSO-12™ thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 17. PowerSSO-24™ thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 18. PowerSSO-12™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 19. PowerSSO-24™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 20. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
List of figures VND5050J-E / VND5050K-E
4/37 Doc ID 12266 Rev 6
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. Status timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5. Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 6. Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 7. Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 8. Off-state output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 9. High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 10. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 11. Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 12. Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 13. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 14. Status low output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 15. On-state resistance vs Tcase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 16. Status leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 17. On-state resistance vs VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 18. Status clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 19. Openload on-state detection threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 20. Openload off-state voltage detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 21. ILIM vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 22. Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 23. Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 24. Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 25. STAT_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 26. High level STAT_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 27. Low level STAT_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 28. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 29. Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 30. Maximum turn-off current versus inductance (for each channel) . . . . . . . . . . . . . . . . . . . . 23
Figure 31. PowerSSO-12™ PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 32. Rthj-amb vs PCB copper area in open box free air condition (one channel on). . . . . . . . . 24
Figure 33. PowerSSO-12™ thermal impedance junction ambient single pulse (one channel on). . . . 25
Figure 34. Thermal fitting model of a double channel HSD in PowerSSO-12™ . . . . . . . . . . . . . . . . . 25
Figure 35. PowerSSO-24™ PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 36. Rthj-amb vs PCB copper area in open box free air condition (one channel on). . . . . . . . . 27
Figure 37. PowerSSO-24™ thermal impedance junction ambient single pulse (one channel on). . . . 28
Figure 38. Thermal fitting model of a double channel HSD in PowerSSO-24™ . . . . . . . . . . . . . . . . . 28
Figure 39. PowerSSO-12™ package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 40. PowerSSO-24™ package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 41. PowerSSO-12™ tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 42. PowerSSO-12™ tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 43. PowerSS0-24™ tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 44. PowerSSO-24™ tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
VND5050J-E / VND5050K-E Block diagram and pin description
Doc ID 12266 Rev 6 5/37
1 Block diagram and pin description
Figure 1. Block diagram
Table 2. Pin function
Name Function
VCC Battery connection.
OUTPUTn Power output.
GND Ground connection. Must be reverse battery protected by an external diode/resistor
network.
INPUTn Voltage controlled input pin with hysteresis, CMOS compatible. Controls output
switch state.
STATUSn Open drain digital diagnostic pin.
STAT_DIS Active high CMOS compatible pin, to disable the STATUS pin.
OVERTEMP. 1
V
CC
GND
LOGIC
DRIVER 1
V
CC
CLAMP
UNDERVOLTAGE
CLAMP 1
OPENLOAD ON 1
CURRENT LIMITER 1
OPENLOAD OFF 1
CONTROL & PROTECTION
EQUIVALENT TO
CHANNEL1
INPUT2
STATUS2
V
CC
INPUT2
STATUS2
INPUT1
STATUS1
OUTPUT1
OUTPUT2
STAT_DIS
PWR
LIM
1
Block diagram and pin description VND5050J-E / VND5050K-E
6/37 Doc ID 12266 Rev 6
Figure 2. Configuration diagram (top view)
Table 3. Suggested connections for unused and not connected pins
Connection/pin STATUS N.C. OUTPUT INPUT STAT_DIS
Floating X X X X X
To ground N.R.(1)
1. Not recommended.
XN.R.
Through 10KΩ
resistor
Through 10KΩ
resistor
PowerSSO-12 PowerSSO-24
INPUT1
STATUS1
GND.
V
CC
N.C.
STAT_DIS
N.C.
V
CC
STATUS2
N.C.
N.C.
INPUT2
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
TAB = V
CC
TA B = V
cc
V
cc
OUTPUT 1
OUTPUT 2
OUTPUT 2
V
cc
OUTPUT 1
12
11
10
9
8
7
1
2
3
4
5
6
INPUT 2
GND
INPUT 1
STATUS 1
STAT_DIS
STATUS 2
VND5050J-E / VND5050K-E Electrical specifications
Doc ID 12266 Rev 6 7/37
2 Electrical specifications
Figure 3. Current and voltage conventions
Note: VFn = VOUTn - VCCn during reverse battery condition.
2.1 Absolute maximum ratings
Stressing the device above the rating listed in the “Absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to the conditions in table below for extended
periods may affect device reliability. Refer also to the STMicroelectronics SURE Program
and other relevant quality document.
IGND
VCC
GND
OUTPUTnSTAT_DIS
ISD
INPUTn
IINn
VSD
VINn
IOUTn
VOUTn
STATUSn
ISTATn
VSTATn
VCC
IS
VFn
Table 4. Absolute maximum ratings
Symbol Parameter Value Unit
VCC DC supply voltage 41 V
- VCC Reverse DC supply voltage 0.3 V
- IGND DC reverse ground pin current 200 mA
IOUT DC output current Internally limited A
- IOUT Reverse dc output current 15 A
IIN DC input current +10 / -1 mA
ISTAT DC status current +10 / -1 mA
ISTAT_DIS DC status disable current +10 / -1 mA
EMAX
Maximum switching energy
(L=3mH; RL=0Ω; Vbat=13.5V; Tjstart=150ºC; IOUT = IlimL(Typ.))104 mJ
Electrical specifications VND5050J-E / VND5050K-E
8/37 Doc ID 12266 Rev 6
2.2 Thermal data
2.3 Electrical characteristics
8V<V
CC<36 V; -40 °C<Tj<150 °C, unless otherwise specified.
.
VESD
Electrostatic discharge (Human Body Model: R=1.5KΩ;
C=100pF)
– Input
– Status
–STAT_DIS
– Output
–V
CC
4000
4000
4000
5000
5000
V
V
V
V
V
VESD Charge device model (CDM-AEC-Q100-011) 750 V
TjJunction operating temperature -40 to 150 °C
Tstg Storage temperature - 55 to 150 °C
Table 4. Absolute maximum ratings (continued)
Symbol Parameter Value Unit
Table 5. Thermal data
Symbol Parameter
Value
Unit
PowerSSO-12 PowerSSO-24
Rthj-case
Thermal resistance junction case (max)
(with one channel on) 2.8 2.8 °C/W
Rthj-amb
Thermal resistance junction ambient
(max) See Figure 32 See Figure 36 °C/W
Table 6. Power section
Symbol Parameter Test conditions Min. Typ. Max. Unit
VCC Operating supply voltage 4.5 13 36 V
VUSD Undervoltage shutdown 3.5 4.5 V
VUSDhyst
Undervoltage shutdown
hysteresis 0.5 V
RON On-state resistance
(2)
IOUT=2A; Tj=25°C
IOUT=2A; Tj=150°C
IOUT=2A; VCC=5V; Tj=25°C
50
100
65
mΩ
mΩ
mΩ
Vclamp Clamp voltage IS=20mA 41 46 52 V
ISSupply current
Off-state; VCC=13V; Tj=25°C;
VIN=VOUT=VSENSE=VCSD=0V
On-state; VCC=13V; VIN=5V;
IOUT=0A
2(1)
3
5(1)
6
µA
mA
VND5050J-E / VND5050K-E Electrical specifications
Doc ID 12266 Rev 6 9/37
IL(off1)
Off-state output
current(2)
VIN=VOUT=0V; VCC=13V;
Tj=25°C
VIN=VOUT=0V; VCC=13V;
Tj=125°C
0
0
0.01 3
5µA
IL(off2)
Off-state output
current
(2)
VIN=0V; VOUT=4V -75 0
VF
Output - V
CC
diode
voltage
(2)
-IOUT=4A; Tj=150°C 0.7 V
1. PowerMOS leakage included.
2. For each channel.
Table 7. Switching (VCC =13V; T
j= 25°C)
Symbol Parameter Test conditions Min. Typ. Max. Unit
td(on) Turn-on delay time RL= 6.5Ω (see Figure 5)20µs
td(off) Turn-off delay time RL= 6.5Ω (see Figure 5)40µs
dVOUT/dt(on) Turn-on voltage slope RL= 6.5Ω See Figure 22 V/µs
dVOUT/dt(off) Turn-off voltage slope RL= 6.5Ω See Figure 24 V/µs
WON
Switching energy losses
during twon
RL= 6.5Ω (see Figure 5)0.21mJ
WOFF
Switching energy losses
during twoff
RL= 6.5Ω (see Figure 5)0.28mJ
Table 8. Status pin (VSD=0V)
Symbol Parameter Test conditions Min. Typ. Max. Unit
VSTAT
Status low output
voltage ISTAT= 1.6 mA, VSD=0V 0.5 V
ILSTAT Status leakage current Normal operation or VSD=5V,
VSTAT= 5V 10 µA
CSTAT
Status pin input
capacitance
Normal operation or VSD=5V,
VSTAT= 5V 100 pF
VSCL Status clamp voltage ISTAT= 1mA
ISTAT= -1mA
5.5
-0.7
7V
V
Table 6. Power section (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
Electrical specifications VND5050J-E / VND5050K-E
10/37 Doc ID 12266 Rev 6
Table 9. Protections(1)
1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related
diagnostic signals must be used together with a proper software strategy. If the device is subjected to
abnormal conditions, this software must limit the duration and number of activation cycles.
Symbol Parameter Test conditions Min. Typ. Max. Unit
IlimH DC short circuit current VCC=13V
5V<VCC<36V
12 18 24
24
A
A
IlimL
Short circuit current
during thermal cycling
VCC=13V
TR<Tj<TTSD
7A
TTSD Shutdown temperature 150 175 200 °C
TRReset temperature
T
RS
+ 1 T
RS
+ 5
°C
TRS Thermal reset of STATUS 135 °C
THYST
Thermal hysteresis
(TTSD-TR)7°C
tSDL
Status delay in overload
conditions Tj>TTSD (see Figure 4)20µs
VDEMAG
Turn-off output voltage
clamp IOUT=2A; VIN=0; L=6mH
V
CC
-41 V
CC
-46 V
CC
-52
V
VON
Output voltage drop
limitation
IOUT= 0.1A;
Tj= -40°C...+150°C
(see Figure 6)
25 mV
Table 10. Openload detection
Symbol Parameter Test conditions Min. Typ. Max. Unit
IOL
Openload on-state
detection threshold VIN = 5V,8V<VCC<18V 10 See
Figure 19
70 mA
tDOL(on)
Openload on-state
detection delay
I
OUT
= 0A, V
CC
=13V
(see Figure 4)
200 µs
tPOL
Delay between INPUT
falling edge and STATUS
rising edge in Openload
condition
IOUT = 0A (see Figure 4) 200 500 1000 µs
VOL
Openload off-state
voltage detection
threshold
VIN = 0V, 8V<VCC<16V 2 See
Figure 20
4V
tDSTKON
Output short circuit to
VCC detection delay at
turn-off
(see Figure 4)180t
POL µs
Table 11. Logic input
Symbol Parameter Test conditions Min. Typ. Max. Unit
VIL Input low level 0.9 V
IIL Low level input current VIN =0.9 V 1 µA
VND5050J-E / VND5050K-E Electrical specifications
Doc ID 12266 Rev 6 11/37
Figure 4. Status timings
VIH Input high level 2.1 V
IIH High level input current VIN = 2.1 V 10 µA
VI(hyst) Input hysteresis voltage 0.25 V
VICL Input clamp voltage IIN = 1mA
IIN = -1mA 5.5 -0.7
7V
V
VSDL
STAT_DIS low level
voltage 0.9 V
ISDL
Low level STAT_DIS
current VSD = 0.9 V 1 µA
VSDH
STAT_DIS high level
voltage 2.1 V
ISDH
High level STAT_DIS
current VSD = 2.1 V 10 µA
VSD(hyst)
STAT_DIS hysteresis
voltage 0.25 V
VSDCL STAT_DIS clamp voltage ISD= 1mA
ISD= -1mA
5.5
-0.7
7V
V
Table 11. Logic input (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
VIN
VSTAT
tPOL
OPEN LOAD STATUS TIMING (without external pull-up)
IOUT < IOL
VOUT < VOL
tDOL(on)
VIN
VSTAT
OPEN LOAD STATUS TIMING (with external pull-up)
IOUT < IOL
VOUT > VOL
tDOL(on)
VIN
VSTAT
OVER TEMP STATUS TIMING
tSDL
tSDL
Tj > TTSD
VIN
VSTAT
tDSTKON
OUTPUT STUCK TO VCC
IOUT > IOL
VOUT > VOL
tDOL(on)
Electrical specifications VND5050J-E / VND5050K-E
12/37 Doc ID 12266 Rev 6
Figure 5. Switching characteristics
Table 12. Truth table
Conditions Input Output Sense (VCSD=0V)(1)
1. If the VCSD is high, the SENSE output is at a high impedance, its potential depends on leakage currents
and external circuit.
Normal operation L
H
L
H
H
H
Current limitation L
H
L
X
H
H
Over temperature L
H
L
L
H
L
Undervoltage L
H
L
L
X
X
Output voltage > VOL
L
H
H
H
L(2)
H
2. The STATUS pin is low with a delay equal to tDSTKON after INPUT falling edge.
Output current < IOL
L
H
L
H
H (3)
L
3. The STATUS pin becomes high with a delay equal to tPOL after INPUT falling edge.
VOUT
dVOUT/dt(on)
tr
80%
10% tf
dVOUT/dt(off)
td(off)
td(on)
INPUT
t
t
90%
VND5050J-E / VND5050K-E Electrical specifications
Doc ID 12266 Rev 6 13/37
Figure 6. Output voltage drop limitation
Table 13. Electrical transient requirements (part 1/3)
ISO 7637-2:
2004(E)
test pulse
Test levels(1) Number of
pulses or
test times
Burst cycle/pulse
repetition time
Delays and
Impedance
III IV
1 -75V -100V 5000 pulses 0.5 s 5 s 2 ms, 10 Ω
2a +37V +50V 5000 pulses 0.2 s 5 s 50 μs, 2 Ω
3a -100V -150V 1h 90 ms 100 ms 0.1 μs, 50 Ω
3b +75V +100V 1h 90 ms 100 ms 0.1 μs, 50 Ω
4-6V-7V1 pulse 100 ms, 0.01
Ω
5b(2) +65V +87V 1 pulse 400 ms, 2 Ω
Table 14. Electrical transient requirements (part 2/3)
ISO 7637-2:
2004(E)
test pulse
Test level results(1)
1. The above test levels must be considered referred to VCC = 13.5V except for pulse 5b.
III IV
1C C
2a C C
3a C C
3b C C
4C C
5b(2)
2. Valid in case of external load dump clamp: 40V maximum referred to ground.
CC
V
on
I
out
V
cc
-V
out
T
j
=150
o
CT
j
=25
o
C
T
j
=-40
o
C
V
on
/R
on(T)
Electrical specifications VND5050J-E / VND5050K-E
14/37 Doc ID 12266 Rev 6
Table 15. Electrical transient requirements (part 3/3)
Class Contents
C All functions of the device are performed as designed after exposure to disturbance.
EOne or more functions of the device are not performed as designed after exposure to
disturbance and cannot be returned to proper operation without replacing the device.
VND5050J-E / VND5050K-E Electrical specifications
Doc ID 12266 Rev 6 15/37
Figure 7. Waveforms
STATUS
INPUT
NORMAL OPERATION
UNDERVOLTAGE
V
CC
V
USD
V
USDhyst
INPUT
STATUS
LOAD CURRENT
LOAD CURRENT
STAT_DIS
STAT_DIS
undefined
OPEN LOAD without external pull-up
STATUS
INPUT
STATUS
INPUT
OPEN LOAD with external pull-up
LOAD VOLTAGE
LOAD VOLTAGE
V
OL
V
OUT
>V
OL
STAT_DIS
STAT_DIS
LOAD CURRENT I
OUT
<I
OL
STATUS
INPUT
RESISTIVE SHORT TO Vcc, NORMAL LOAD
LOAD VOLTAGE V
OL
V
OUT
>V
OL
STAT_DIS
I
OUT
>I
OL
t
DSTKON
t
POL
OVERLOAD OPERATION
INPUT
STATUS
T
TSD
T
R
T
j
LOAD CURRENT
STAT_DIS
T
RS
I
LIMH
I
LIML
thermal cycling
power
limitation
current
limitation
SHORTED LOAD NORMAL LOAD
Electrical specifications VND5050J-E / VND5050K-E
16/37 Doc ID 12266 Rev 6
2.4 Electrical characteristics curves
Figure 8. Off-state output current Figure 9. High level input current
Figure 10. Input clamp voltage Figure 11. Input high level
Figure 12. Input low level Figure 13. Input hysteresis voltage
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
0.125
0.25
0.375
0.5
0.625
0.75
0.875
1
Iloff1 (uA)
Off state
Vcc=13V
Vin=Vout=0V
-50 -25 0 25 50 75 100 125 150 175
Tc (° C )
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
lih (uA)
Vin=2.1V
-50 -25 0 25 50 75 100 125 150 175
Tc ( ° C )
6
6.25
6.5
6.75
7
7.25
7.5
7.75
8
Vicl (V)
lin=1mA
-50 -25 0 25 50 75 100 125 150 175
Tc (° C )
0
0.5
1
1.5
2
2.5
3
3.5
4
Vih (V)
-50 -25 0 25 50 75 100 125 150 175
Tc (° C )
0
0.5
1
1.5
2
2.5
3
3.5
4
Vil (V)
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
Vihyst (V)
VND5050J-E / VND5050K-E Electrical specifications
Doc ID 12266 Rev 6 17/37
Figure 14. Status low output voltage Figure 15. On-state resistance vs Tcase
Figure 16. Status leakage current Figure 17. On-state resistance vs VCC
Figure 18. Status clamp voltage Figure 19. Openload on-state detection
threshold
-50 -25 0 25 50 75 100 125 150 175
Tc (° C )
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
Vstat (V)
Istat=1.6mA
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
10
20
30
40
50
60
70
80
90
100
Ron (mOhm)
Iout=2A
Vcc=13V
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0.025
0.03
0.035
0.04
0.045
0.05
0.055
Ilstat (uA)
Vstat=5V
0 5 10 15 20 25 30 35 40
Vcc (V)
0
10
20
30
40
50
60
70
80
90
100
Ron (mOhm)
Tc= 150°C
Tc= 125°C
Tc= 25°C
Tc= -40°C
-50 -25 0 25 50 75 100 125 150 175
Tc (° C )
4
4.5
5
5.5
6
6.5
7
7.5
8
8.5
9
Vscl (V)
Istat=1mA
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
10
20
30
40
50
60
70
80
90
100
Iol (mA)
Vin=5V
Electrical specifications VND5050J-E / VND5050K-E
18/37 Doc ID 12266 Rev 6
Figure 20. Openload off-state voltage
detection threshold
Figure 21. ILIM vs Tcase
Figure 22. Turn-on voltage slope Figure 23. Undervoltage shutdown
Figure 24. Turn-off voltage slope Figure 25. STAT_DIS clamp voltage
-50 -25 0 25 50 75 100 125 150 175
Tc (° C )
1
1.5
2
2.5
3
3.5
4
4.5
5
Vol (V)
Vin=0V
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
5
7.5
10
12.5
15
17.5
20
22.5
25
Ilimh (A)
Vcc=13V
-50 -25 0 25 50 75 100 125 150 175
Tc (° C )
0
100
200
300
400
500
600
700
800
900
1000
dVout/dt(on) (V/ms)
Vcc=13V
RI=6.5Ohm
-50 -25 0 25 50 75 100 125 150 175
Tc (° C )
0
2
4
6
8
10
12
14
Vusd (V)
-50 -25 0 25 50 75 100 125 150 175
Tc (° C )
0
100
200
300
400
500
600
700
800
900
1000
dVout/dt(off) (V/ms)
Vcc=13V
RI=6.5Ohm
-50 -25 0 25 50 75 100 125 150 175
Tc (° C )
0
2
4
6
8
10
12
14
Vsdcl(V)
Isd=1mA
VND5050J-E / VND5050K-E Electrical specifications
Doc ID 12266 Rev 6 19/37
Figure 26. High level STAT_DIS voltage Figure 27. Low level STAT_DIS voltage
-50 -25 0 25 50 75 100 125 150 175
Tc ( °C )
0
1
2
3
4
5
6
7
8
Vsdh(V)
-50 -25 0 25 50 75 100 125 150 175
Tc ( °C )
0
1
2
3
4
5
6
7
8
Vsdl(V)
Application information VND5050J-E / VND5050K-E
20/37 Doc ID 12266 Rev 6
3 Application information
Figure 28. Application schematic
Note: Channel 2 has the same internal circuit as channel 1.
3.1 GND protection network against reverse battery
3.1.1 Solution 1: resistor in the ground line (RGND only)
This can be used with any type of load.
The following is an indication on how to dimension the RGND resistor.
1. RGND ≤ 600mV / (IS(on)max).
2. RGND ≥ (−VCC) / (-IGND)
where -IGND is the DC reverse ground pin current and can be found in the absolute
maximum rating section of the device datasheet.
Power Dissipation in RGND (when VCC<0: during reverse battery situations) is:
PD= (-VCC)2/RGND
This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the
maximum on-state currents of the different devices.
Please note that if the microprocessor ground is not shared by the device ground then the
RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output
values. This shift will vary depending on how many devices are ON in the case of several
high side drivers sharing the same RGND.
V
CC
GND
OUTPUT
D
GND
R
GND
D
ld
μ
C
+5V
V
GND
STAT_DIS
INPUT
R
prot
R
prot
R
prot
+5V
STATUS
VND5050J-E / VND5050K-E Application information
Doc ID 12266 Rev 6 21/37
If the calculated power dissipation leads to a large resistor or several devices have to share
the same resistor then ST suggests to utilize Solution 2 (see below).
3.1.2 Solution 2: a diode (DGND) in the ground line
A resistor (RGND=1kΩ) should be inserted in parallel to DGND if the device drives an
inductive load.
This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network will produce a shift (≈600mV) in the input
threshold and in the status output values if the microprocessor ground is not common to the
device ground. This shift will not vary if more than one HSD shares the same diode/resistor
network.
3.2 Load dump protection
Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the
VCC max DC rating. The same applies if the device is subject to transients on the VCC line
that are greater than the ones shown in the ISO 7637-2: 2004(E) table.
3.3 Microcontroller I/Os protection
If a ground protection network is used and negative transient are present on the VCC line,
the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to
prevent the µC I/Os pins to latch-up.
The value of these resistors is a compromise between the leakage current of μC and the
current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of μC
I/Os.
-VCCpeak/Ilatchup ≤ Rprot ≤ (VOHμC-VIH-VGND) / IIHmax
Calculation example:
For VCCpeak= - 100V and Ilatchup ≥ 20mA; VOHμC ≥ 4.5V
5kΩ ≤ Rprot ≤ 180kΩ
Recommended values: Rprot =10kΩ.
3.4 Open-load detection in off-state
Off-state open load detection requires an external pull-up resistor (RPU) connected between
OUTPUT pin and a positive supply voltage (VPU) like the +5V line used to supply the
microprocessor.
The external resistor has to be selected according to the following requirements:
1. no false open load indication when load is connected: in this case we have to avoid
VOUT to be higher than VOlmin; this results in the following condition
VOUT=(VPU/(RL+RPU))RL<VOlmin.
2. no misdetection when load is disconnected: in this case the VOUT has to be higher than
VOLmax; this results in the following condition RPU<(VPU–VOLmax)/IL(off2).
Application information VND5050J-E / VND5050K-E
22/37 Doc ID 12266 Rev 6
Because Is(OFF) may significantly increase if Vout is pulled high (up to several mA), the pull-
up resistor RPU should be connected to a supply that is switched OFF when the module is in
standby.
The values of VOLmin, VOLmax and IL(off2) are available in the Electrical Characteristics
section.
Figure 29. Open-load detection in off-state
VOL
V batt. VPU
RPU
RL
R
DRIVER
+
LOGIC
+
-
INPUT
STATUS
VCC
OUT
GROUND
IL(off2)
VND5050J-E / VND5050K-E Application information
Doc ID 12266 Rev 6 23/37
3.5 Maximum demagnetization energy (VCC = 13.5V)
Figure 30. Maximum turn-off current versus inductance (for each channel)
Note: Values are generated with RL =0 Ω.In case of repetitive pulses, Tjstart (at beginning of each
demagnetization) of every pulse must not exceed the temperature specified above for
curves A and B.
1
10
100
0,1 1 10 100
L (mH)
I (A)
C: Tjstart = 125°C repetitive pulse
A: Tjstart = 150°C single pulse
B: Tjstart = 100°C repetitive pulse
Demagnetization Demagnetization Demagnetization
t
VIN, IL
A
B
C
Package and PCB thermal data VND5050J-E / VND5050K-E
24/37 Doc ID 12266 Rev 6
4 Package and PCB thermal data
4.1 PowerSSO-12™ thermal data
Figure 31. PowerSSO-12™ PC board
Note: Layout condition of Rth and Zth measurements (PCB: Double layer, Thermal Vias, FR4
area= 77mm x 86mm,PCB thickness=1.6mm, Cu thickness=70μm (front and back side),
Copper areas: from minimum pad lay-out to 8cm2).
Figure 32. Rthj-amb vs PCB copper area in open box free air condition (one channel
on)
30
35
40
45
50
55
60
65
70
0246810
RTHj_amb(°C/ W)
PCB Cu heatsink area (cm^ 2)
VND5050J-E / VND5050K-E Package and PCB thermal data
Doc ID 12266 Rev 6 25/37
Figure 33. PowerSSO-12™ thermal impedance junction ambient single pulse (one
channel on)
Equation 1: pulse calculation formula
where δ = tP/T
Figure 34. Thermal fitting model of a double channel HSD in PowerSSO-12™(a)
a. The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded
protections (power limitation or thermal cycling during thermal shutdown) are not triggered.
0,1
1
10
100
0,0001 0,001 0,01 0,1 1 10 100 1000
Time ( s)
ZTH (°C/ W)
Footprint
8 cm
2
2 cm
2
ZTHδRTH δZTHtp 1δ–()+⋅=
Package and PCB thermal data VND5050J-E / VND5050K-E
26/37 Doc ID 12266 Rev 6
Table 16. PowerSSO-12™ thermal parameters
Area/island (cm2)Footprint28
R1= R7 (°C/W) 0.7
R2= R8 (°C/W) 2.8
R3 (°C/W) 4
R4 (°C/W) 8 8 7
R5 (°C/W) 22 15 10
R6 (°C/W) 26 20 15
C1= C7 (W.s/°C) 0.001
C2= C8 (W.s/°C) 0.0025
C3 (W.s/°C) 0.05
C4 (W.s/°C) 0.2 0.1 0.1
C5 (W.s/°C) 0.27 0.8 1
C6 (W.s/°C) 3 6 9
VND5050J-E / VND5050K-E Package and PCB thermal data
Doc ID 12266 Rev 6 27/37
4.2 PowerSSO-24™ thermal data
Figure 35. PowerSSO-24™ PC board
Note: Layout condition of Rth and Zth measurements (PCB: Double layer, Thermal Vias, FR4
area= 77mm x 86mm, PCB thickness=1.6mm, Cu thickness=70µm (front and back side),
Copper areas: from minimum pad lay-out to 8cm2).
Figure 36. Rthj-amb vs PCB copper area in open box free air condition (one channel
on)
30
35
40
45
50
55
0246810
RTHj_amb(°C/W)
PCB Cu heatsink area (cm^2)
Package and PCB thermal data VND5050J-E / VND5050K-E
28/37 Doc ID 12266 Rev 6
Figure 37. PowerSSO-24™ thermal impedance junction ambient single pulse (one
channel on)
Equation 2: pulse calculation formula
where δ = tP/T
Figure 38. Thermal fitting model of a double channel HSD in PowerSSO-24™(b)
b. The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded
protections (power limitation or thermal cycling during thermal shutdown) are not triggered.
ZTHδRTH δZTHtp 1δ–()+⋅=
VND5050J-E / VND5050K-E Package and PCB thermal data
Doc ID 12266 Rev 6 29/37
Table 17. PowerSSO-24™ thermal parameters
Area/island (cm2)Footprint28
R1=R7 (°C/W) 0.4
R2=R8 (°C/W) 2
R3 (°C/W) 6
R4 (°C/W) 7.7
R5 (°C/W) 9 9 8
R6 (°C/W) 28 17 10
C1=C7 (W.s/°C) 0.001
C2=C8 (W.s/°C) 0.0022
C3 (W.s/°C) 0.025
C4 (W.s/°C) 0.75
C5 (W.s/°C) 1 4 9
C6 (W.s/°C) 2.2 5 17
Package and packing information VND5050J-E / VND5050K-E
30/37 Doc ID 12266 Rev 6
5 Package and packing information
5.1 ECOPACK® packages
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
5.2 PowerSSO-12™ package information
Figure 39. PowerSSO-12™ package dimensions
VND5050J-E / VND5050K-E Package and packing information
Doc ID 12266 Rev 6 31/37
Table 18. PowerSSO-12™ mechanical data
Symbol
Millimeters
Min. Typ. Max.
A 1.25 1.62
A1 0 0.1
A2 1.10 1.65
B 0.23 0.41
C 0.19 0.25
D4.8 5.0
E3.8 4.0
e0.8
H5.8 6.2
h 0.25 0.5
L 0.4 1.27
k0° 8°
X1.9 2.5
Y3.6 4.2
ddd 0.1
Package and packing information VND5050J-E / VND5050K-E
32/37 Doc ID 12266 Rev 6
5.3 PowerSSO-24™ package information
Figure 40. PowerSSO-24™ package dimensions
Table 19. PowerSSO-24™ mechanical data
Symbol
Millimeters
Min. Typ. Max.
A2.45
A2 2.15 2.35
a1 0 0.1
b 0.33 0.51
c 0.23 0.32
D 10.10 10.50
E7.4 7.6
e0.8
e3 8.8
F2.3
G0.1
H 10.1 10.5
VND5050J-E / VND5050K-E Package and packing information
Doc ID 12266 Rev 6 33/37
h0.4
k 0deg 8deg
L 0.55 0.85
O1.2
Q0.8
S2.9
T3.65
U1.0
N 10deg
X4.1 4.7
Y6.5 7.1
Table 19. PowerSSO-24™ mechanical data (continued)
Symbol
Millimeters
Min. Typ. Max.
Package and packing information VND5050J-E / VND5050K-E
34/37 Doc ID 12266 Rev 6
5.4 PowerSSO-12™ packing information
Figure 41. PowerSSO-12™ tube shipment (no suffix)
Figure 42. PowerSSO-12™ tape and reel shipment (suffix “TR”)
All dimensions are in mm.
Base Q.ty 100
Bulk Q.ty 2000
Tube length (± 0.5) 532
A1.85
B6.75
C (± 0.1) 0.6
A
C
B
Base Q.ty 2500
Bulk Q.ty 2500
A (max) 330
B (min) 1.5
C (± 0.2) 13
F 20.2
G (+ 2 / -0) 12.4
N (min) 60
T (max) 18.4
REEL DIMENSIONS
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
All dimensions are in mm.
Tape width W 12
Tape Hole Spacing P0 (± 0.1) 4
Component Spacing P 8
Hole Diameter D (± 0.05) 1.5
Hole Diameter D1 (min) 1.5
Hole Position F (± 0.1) 5.5
Compartment Depth K (max) 4.5
Hole Spacing P1 (± 0.1) 2
Top
cover
tape
End
Start
No componentsNo components Components
500mm min
500mm min
Empty components pockets
saled with cover tape.
User direction of feed
VND5050J-E / VND5050K-E Package and packing information
Doc ID 12266 Rev 6 35/37
5.5 PowerSSO-24™ packing information
Figure 43. PowerSS0-24™ tube shipment (no suffix)
Figure 44. PowerSSO-24™ tape and reel shipment (suffix “TR”)
All dimensions are in mm.
Base Qty 49
Bulk Qty 1225
Tube length (±0.5) 532
A3.5
B13.8
C (±0.1) 0.6
A
C
B
Base Qty 1000
Bulk Qty 1000
A (max) 330
B (min) 1.5
C (± 0.2) 13
F20.2
G (+2 / -0) 24.4
N (min) 100
T (max) 30.4
REEL DIMENSIONS
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
All dimensions are in mm.
Tape width W 24
Tape Hole Spacing P0 (± 0.1) 4
Component Spacing P 12
Hole Diameter D (± 0.05) 1.55
Hole Diameter D1 (min) 1.5
Hole Position F (± 0.1) 11.5
Compartment Depth K (max) 2.85
Hole Spacing P1 (± 0.1) 2
Top
cover
tape
End
Start
No componentsNo components Components
500mm min 500mm min
Empty components pockets
sealed with cover tape.
User direction of feed
Revision history VND5050J-E / VND5050K-E
36/37 Doc ID 12266 Rev 6
6 Revision history
Table 20. Document revision history
Date Revision Changes
30-Mar-2006 1Initial release.
11-Jan-2007 2 Minor formatting changes.
New disclaimer attached.
31-May-2007 3
Reformatted and restructured.
Contents and lists of tables and figures added.
Section 3.5: Maximum demagnetization energy (VCC = 13.5V)
added.
Table 4: Absolute maximum ratings: EMAX entries updated.
Table 13: Electrical transient requirements (part 1/3):Test level
values III and IV for test pulse 5b and notes updated
Figure 34: Thermal fitting model of a double channel HSD in
PowerSSO-12™, Figure 38: Thermal fitting model of a double
channel HSD in PowerSSO-24™: added notes.
Features table updated: ILIMH changed from 19 to 18A.
03-Dec-2007 4
Updated Section 4.1: PowerSSO-12™ thermal data:
– Changed Figure 32: Rthj-amb vs PCB copper area in open
box free air condition (one channel on).
– Changed Figure 33: PowerSSO-12™ thermal impedance
junction ambient single pulse (one channel on).
– Updated Table 16: PowerSSO-12™ thermal parameters:
R3 value changed from 7 to 4 °C/W.
R4 values changed from 10 /10 /10 to 8 /8 /7 °C/W.
17-Jun-2009 5
Table 19: PowerSSO-24™ mechanical data:
– Deleted A (min) value
– Changed A (max) value from 2.47 to 2.45
– Changed A2 (max) value from 2.40 to 2.35
– Changed a1 (max) value from 0.075 to 0.1
– Added F and k rows
22-Jul-2009 6
Updated Figure 40: PowerSSO-24™ package dimensions.
Updated Table 19: PowerSSO-24™ mechanical data:
– Deleted G1 row
– Added O, Q, S, T and U rows.
VND5050J-E / VND5050K-E
Doc ID 12266 Rev 6 37/37
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