VND5050J-E VND5050K-E Double channel high side driver for automotive applications Features Max supply voltage VCC 41 V Operating voltage range VCC 4.5 to 36 V Max on-State resistance (per ch.) RON 50 m Current limitation (typ) ILIMH 18 A Off-state supply current IS 2 A(1) PowerSSO-12 PowerSSO-24 - Reverse battery protection (see Figure 28) - Electrostatic discharge protection 1. Typical value with all loads connected. Applications Main - Inrush current active management by power limitation - Very low standby current - 3.0 V CMOS compatible input - Optimized electromagnetic emission - Very low electromagnetic susceptibility - In compliance with the 2002/95/EC European directive Description Diagnostic functions - Open drain status output - On-state open load detection - Off-state open load detection - Thermal shutdown indication Protections - Undervoltage shutdown - Overvoltage clamp - Output stuck to VCC detection - Load current limitation - Self limiting of fast thermal transients - Protection against loss of ground and loss of VCC - Thermal shutdown Table 1. Device summary Package July 2009 All types of resistive, inductive and capacitive loads The VND5050K-E and VND5050J-E are monolithic devices made using STMicroelectronics VIPower M0-5 technology. they are intended for driving resistive or inductive loads with one side connected to ground. Active VCC pin voltage clamp protects the devices against low energy spikes (see ISO7637 transient compatibility table). The devices detect open load condition both in on and off-state, when STAT_DIS is left open or driven low. Output shorted to VCC is detected in the off-state. When STAT_DIS is driven high, STATUS pin is in high impedance state. Output current limitation protects the devices in overload condition. In case of long overload duration, the devices limit the dissipated power to a safe level up to thermal shutdown intervention. Thermal shutdown with automatic restart allows the devices to recover normal operation as soon as fault conditions disappear. Order code Tube Tape and reel PowerSSO-12 VND5050J-E VND5050JTR-E PowerSSO-24 VND5050K-E VND5050KTR-E Doc ID 12266 Rev 6 1/37 www.st.com 1 Contents VND5050J-E / VND5050K-E Contents 1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.1 4 5 6 2/37 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 20 3.1.1 Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 20 3.1.2 Solution 2: a diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . 21 3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.3 Microcontroller I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.4 Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.5 Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . 23 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.1 PowerSSO-12TM thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.2 PowerSSO-24TM thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.1 ECOPACK(R) packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.2 PowerSSO-12TM package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.3 PowerSSO-24TM package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.4 PowerSSO-12TM packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.5 PowerSSO-24TM packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Doc ID 12266 Rev 6 VND5050J-E / VND5050K-E List of tables List of tables Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Switching (VCC = 13V; Tj = 25C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Status pin (VSD=0V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Openload detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Electrical transient requirements (part 1/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Electrical transient requirements (part 2/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Electrical transient requirements (part 3/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PowerSSO-12TM thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 PowerSSO-24TM thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 PowerSSO-12TM mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 PowerSSO-24TM mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Doc ID 12266 Rev 6 3/37 List of figures VND5050J-E / VND5050K-E List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. 4/37 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Status timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Off-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Status low output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 On-state resistance vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Status leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 On-state resistance vs VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Status clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Openload on-state detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Openload off-state voltage detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 ILIM vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 STAT_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 High level STAT_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Low level STAT_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Maximum turn-off current versus inductance (for each channel) . . . . . . . . . . . . . . . . . . . . 23 PowerSSO-12TM PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Rthj-amb vs PCB copper area in open box free air condition (one channel on) . . . . . . . . . 24 PowerSSO-12TM thermal impedance junction ambient single pulse (one channel on). . . . 25 Thermal fitting model of a double channel HSD in PowerSSO-12TM . . . . . . . . . . . . . . . . . 25 PowerSSO-24TM PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Rthj-amb vs PCB copper area in open box free air condition (one channel on) . . . . . . . . . 27 PowerSSO-24TM thermal impedance junction ambient single pulse (one channel on). . . . 28 Thermal fitting model of a double channel HSD in PowerSSO-24TM . . . . . . . . . . . . . . . . . 28 PowerSSO-12TM package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 PowerSSO-24TM package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 PowerSSO-12TM tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 PowerSSO-12TM tape and reel shipment (suffix "TR") . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 PowerSS0-24TM tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 PowerSSO-24TM tape and reel shipment (suffix "TR") . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Doc ID 12266 Rev 6 VND5050J-E / VND5050K-E 1 Block diagram and pin description Block diagram and pin description Figure 1. Block diagram VCC VCC CLAMP GND UNDERVOLTAGE INPUT1 CLAMP 1 STATUS1 DRIVER 1 STAT_DIS OUTPUT1 LOGIC INPUT2 OVERTEMP. 1 CURRENT LIMITER 1 STATUS2 OPENLOAD ON 1 OPENLOAD OFF 1 PWRLIM 1 Table 2. OUTPUTn GND INPUTn CONTROL & PROTECTION STATUS2 EQUIVALENT TO CHANNEL1 VCC OUTPUT2 Pin function Name VCC INPUT2 Function Battery connection. Power output. Ground connection. Must be reverse battery protected by an external diode/resistor network. Voltage controlled input pin with hysteresis, CMOS compatible. Controls output switch state. STATUSn Open drain digital diagnostic pin. STAT_DIS Active high CMOS compatible pin, to disable the STATUS pin. Doc ID 12266 Rev 6 5/37 Block diagram and pin description Figure 2. VND5050J-E / VND5050K-E Configuration diagram (top view) TAB = Vcc GND STAT_DIS INPUT 1 STATUS 1 STATUS 2 INPUT 2 1 2 3 4 5 6 12 11 10 9 8 7 Vcc OUTPUT 1 OUTPUT 1 OUTPUT 2 OUTPUT 2 Vcc VCC GND. N.C. STAT_DIS INPUT1 STATUS1 N.C. STATUS2 N.C. INPUT2 N.C. VCC OUTPUT1 OUTPUT1 OUTPUT1 OUTPUT1 OUTPUT1 OUTPUT1 OUTPUT2 OUTPUT2 OUTPUT2 OUTPUT2 OUTPUT2 OUTPUT2 TAB = VCC PowerSSO-12 Table 3. PowerSSO-24 Suggested connections for unused and not connected pins Connection/pin STATUS N.C. OUTPUT INPUT STAT_DIS Floating X X X X X To ground N.R.(1) X N.R. Through 10K resistor Through 10K resistor 1. Not recommended. 6/37 Doc ID 12266 Rev 6 VND5050J-E / VND5050K-E 2 Electrical specifications Electrical specifications Figure 3. Current and voltage conventions IS VCC VCC VFn ISD IOUTn STAT_DIS OUTPUTn VSD VOUTn IINn ISTATn INPUTn STATUSn VINn VSTATn GND IGND Note: VFn = VOUTn - VCCn during reverse battery condition. 2.1 Absolute maximum ratings Stressing the device above the rating listed in the "Absolute maximum ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to the conditions in table below for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality document. Table 4. Absolute maximum ratings Symbol Value Unit DC supply voltage 41 V - VCC Reverse DC supply voltage 0.3 V - IGND DC reverse ground pin current 200 mA Internally limited A 15 A VCC IOUT - IOUT Parameter DC output current Reverse dc output current IIN DC input current +10 / -1 mA ISTAT DC status current +10 / -1 mA +10 / -1 mA 104 mJ ISTAT_DIS DC status disable current EMAX Maximum switching energy (L=3mH; RL=0; Vbat=13.5V; Tjstart=150C; IOUT = IlimL(Typ.)) Doc ID 12266 Rev 6 7/37 Electrical specifications Table 4. VND5050J-E / VND5050K-E Absolute maximum ratings (continued) Symbol Value Unit 4000 4000 4000 5000 5000 V V V V V 750 V Junction operating temperature -40 to 150 C Storage temperature - 55 to 150 C VESD Electrostatic discharge (Human Body Model: R=1.5K; C=100pF) - Input - Status - STAT_DIS - Output - VCC VESD Charge device model (CDM-AEC-Q100-011) Tj Tstg 2.2 Parameter Thermal data Table 5. Thermal data Value Symbol 2.3 Parameter Unit Rthj-case Thermal resistance junction case (max) (with one channel on) Rthj-amb Thermal resistance junction ambient (max) PowerSSO-12 PowerSSO-24 2.8 2.8 C/W See Figure 32 See Figure 36 C/W Electrical characteristics 8 V<VCC<36 V; -40 C<Tj<150 C, unless otherwise specified. Table 6. . Symbol Parameter VCC Operating supply voltage VUSD VUSDhyst RON Vclamp IS 8/37 Power section Test conditions Min. Typ. Max. Unit 4.5 13 36 V Undervoltage shutdown 3.5 4.5 V Undervoltage shutdown hysteresis 0.5 On-state resistance(2) IOUT=2A; Tj=25C IOUT=2A; Tj=150C IOUT=2A; VCC=5V; Tj=25C Clamp voltage IS=20mA Supply current Off-state; VCC=13V; Tj=25C; VIN=VOUT=VSENSE=VCSD=0V On-state; VCC=13V; VIN=5V; IOUT=0A Doc ID 12266 Rev 6 41 V 50 100 65 m m m 46 52 V 2(1) 3 5(1) 6 A mA VND5050J-E / VND5050K-E Table 6. Electrical specifications Power section (continued) Symbol Parameter Test conditions IL(off2) VF Typ. Max. 0 0 0.01 3 5 VIN=VOUT=0V; VCC=13V; Tj=25C VIN=VOUT=0V; VCC=13V; Tj=125C Off-state output current(2) IL(off1) Min. Off-state output current(2) VIN=0V; VOUT=4V Output - VCC diode voltage (2) -IOUT=4A; Tj=150C -75 Unit A 0 0.7 V Max. Unit 1. PowerMOS leakage included. 2. For each channel. Table 7. Switching (VCC = 13V; Tj = 25C) Symbol Parameter Test conditions Min. Typ. td(on) Turn-on delay time RL= 6.5 (see Figure 5) 20 s td(off) Turn-off delay time RL= 6.5 (see Figure 5) 40 s dVOUT/dt(on) Turn-on voltage slope RL= 6.5 See Figure 22 V/s dVOUT/dt(off) Turn-off voltage slope RL= 6.5 See Figure 24 V/s WON Switching energy losses during twon RL= 6.5 (see Figure 5) 0.21 mJ WOFF Switching energy losses during twoff RL= 6.5 (see Figure 5) 0.28 mJ Table 8. Symbol Status pin (VSD=0V) Parameter Test conditions Min. Typ. Max. Unit VSTAT Status low output voltage ISTAT= 1.6 mA, VSD=0V 0.5 V ILSTAT Status leakage current Normal operation or VSD=5V, VSTAT= 5V 10 A CSTAT Status pin input capacitance Normal operation or VSD=5V, VSTAT= 5V 100 pF VSCL Status clamp voltage ISTAT= 1mA ISTAT= -1mA 7 V V Doc ID 12266 Rev 6 5.5 -0.7 9/37 Electrical specifications Table 9. Symbol VND5050J-E / VND5050K-E Protections(1) Parameter Test conditions IlimH DC short circuit current VCC=13V 5V<VCC<36V IlimL Short circuit current during thermal cycling VCC=13V TR<Tj<TTSD TTSD Shutdown temperature TR Reset temperature TRS Thermal reset of STATUS THYST tSDL VDEMAG VON Min. Typ. Max. Unit 12 18 24 24 A A 7 A 150 175 200 TRS + 1 TRS + 5 C 135 C Thermal hysteresis (TTSD-TR) 7 Status delay in overload conditions Tj>TTSD (see Figure 4) Turn-off output voltage clamp IOUT=2A; VIN=0; L=6mH Output voltage drop limitation IOUT= 0.1A; Tj= -40C...+150C (see Figure 6) C VCC-41 C VCC-46 20 s VCC-52 V 25 mV 1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles. Table 10. Symbol Parameter Test conditions IOL Openload on-state detection threshold VIN = 5V,8V<VCC<18V tDOL(on) Openload on-state detection delay IOUT = 0A, VCC=13V (see Figure 4) tPOL Delay between INPUT falling edge and STATUS = 0A (see Figure 4) I rising edge in Openload OUT condition VOL Openload off-state voltage detection threshold VIN = 0V, 8V<VCC<16V Output short circuit to VCC detection delay at turn-off (see Figure 4) tDSTKON Table 11. Symbol 10/37 Openload detection Min. Typ. Max. Unit 10 See Figure 19 70 mA 200 s 200 500 1000 s 2 See Figure 20 4 V tPOL s Max. Unit 0.9 V 180 Logic input Parameter Test conditions VIL Input low level IIL Low level input current VIN =0.9 V Doc ID 12266 Rev 6 Min. 1 Typ. A VND5050J-E / VND5050K-E Table 11. Electrical specifications Logic input (continued) Symbol Parameter Test conditions VIH Input high level IIH High level input current VI(hyst) Input hysteresis voltage Max. 10 0.25 VSDL STAT_DIS low level voltage ISDL Low level STAT_DIS current VSDH STAT_DIS high level voltage ISDH High level STAT_DIS current VSD(hyst) STAT_DIS hysteresis voltage 5.5 VSD = 0.9 V 7 V V 0.9 V -0.7 1 A 2.1 V 10 0.25 A V 5.5 ISD= 1mA ISD= -1mA A V VSD = 2.1 V STAT_DIS clamp voltage Unit V VIN = 2.1 V IIN = 1mA IIN = -1mA Input clamp voltage Figure 4. Typ. 2.1 VICL VSDCL Min. 7 -0.7 V V Status timings OPEN LOAD STATUS TIMING (with external pull-up) OPEN LOAD STATUS TIMING (without external pull-up) IOUT < IOL VIN VOUT < VOL IOUT < IOL VIN VOUT > VOL VSTAT VSTAT tDOL(on) tDOL(on) tPOL OVER TEMP STATUS TIMING OUTPUT STUCK TO VCC Tj > TTSD IOUT > IOL VIN VOUT > VOL VSTAT VIN VSTAT tDOL(on) tDSTKON Doc ID 12266 Rev 6 tSDL tSDL 11/37 Electrical specifications Table 12. VND5050J-E / VND5050K-E Truth table Input Output Sense (VCSD=0V)(1) Normal operation L H L H H H Current limitation L H L X H H Over temperature L H L L H L Undervoltage L H L L X X Output voltage > VOL L H H H L(2) H Output current < IOL L H L H H (3) L Conditions 1. If the VCSD is high, the SENSE output is at a high impedance, its potential depends on leakage currents and external circuit. 2. The STATUS pin is low with a delay equal to tDSTKON after INPUT falling edge. 3. The STATUS pin becomes high with a delay equal to tPOL after INPUT falling edge. Figure 5. Switching characteristics VOUT 90% 80% dVOUT/dt(off) dVOUT/dt(on) tr 10% tf t INPUT td(on) td(off) t 12/37 Doc ID 12266 Rev 6 VND5050J-E / VND5050K-E Figure 6. Electrical specifications Output voltage drop limitation Vcc-Vout Tj=150oC Tj=25oC Tj=-40oC Von Iout Von/Ron(T) Table 13. ISO 7637-2: 2004(E) Electrical transient requirements (part 1/3) Test levels(1) test pulse III IV Number of pulses or test times 1 -75V -100V 5000 pulses 0.5 s 5s 2 ms, 10 2a +37V +50V 5000 pulses 0.2 s 5s 50 s, 2 3a -100V -150V 1h 90 ms 100 ms 0.1 s, 50 3b +75V +100V 1h 90 ms 100 ms 0.1 s, 50 4 -6V -7V 1 pulse 100 ms, 0.01 5b(2) +65V +87V 1 pulse 400 ms, 2 Table 14. Burst cycle/pulse repetition time Delays and Impedance Electrical transient requirements (part 2/3) Test level results(1) ISO 7637-2: 2004(E) test pulse III IV 1 C C 2a C C 3a C C 3b C C 4 C C 5b(2) C C 1. The above test levels must be considered referred to VCC = 13.5V except for pulse 5b. 2. Valid in case of external load dump clamp: 40V maximum referred to ground. Doc ID 12266 Rev 6 13/37 Electrical specifications Table 15. 14/37 VND5050J-E / VND5050K-E Electrical transient requirements (part 3/3) Class Contents C All functions of the device are performed as designed after exposure to disturbance. E One or more functions of the device are not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device. Doc ID 12266 Rev 6 VND5050J-E / VND5050K-E Figure 7. Electrical specifications Waveforms NORMAL OPERATION INPUT STAT_DIS LOAD CURRENT STATUS UNDERVOLTAGE VUSDhyst VCC VUSD INPUT STAT_DIS LOAD CURRENT undefined STATUS OPEN LOAD with external pull-up INPUT STAT_DIS LOAD VOLTAGE VOL VOUT>VOL STATUS OPEN LOAD without external pull-up INPUT STAT_DIS LOAD VOLTAGE IOUT<IOL LOAD CURRENT tPOL STATUS RESISTIVE SHORT TO Vcc, NORMAL LOAD INPUT STAT_DIS IOUT>IOL LOAD VOLTAGE VOUT>VOL VOL STATUS tDSTKON OVERLOAD OPERATION Tj TTSD TR TRS INPUT STAT_DIS ILIMH ILIML LOAD CURRENT STATUS thermal cycling current power limitation limitation SHORTED LOAD Doc ID 12266 Rev 6 NORMAL LOAD 15/37 Electrical specifications VND5050J-E / VND5050K-E 2.4 Electrical characteristics curves Figure 8. Off-state output current Figure 9. Iloff1 (uA) High level input current lih (uA) 1 5 4.5 0.875 Off state Vcc=13V Vin=Vout=0V 0.75 Vin=2.1V 4 3.5 0.625 3 0.5 2.5 2 0.375 1.5 0.25 1 0.125 0.5 0 0 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 Tc (C) 50 75 100 125 150 175 100 125 150 175 150 175 Tc (C) Figure 10. Input clamp voltage Figure 11. Input high level Vih (V) Vicl (V) 4 8 3.5 7.75 lin=1mA 7.5 3 7.25 2.5 7 2 6.75 1.5 6.5 1 6.25 0.5 6 0 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 Figure 12. Input low level 75 Figure 13. Input hysteresis voltage Vil (V) Vihyst (V) 4 2 3.5 1.75 3 1.5 2.5 1.25 2 1 1.5 0.75 1 0.5 0.5 0.25 0 0 -50 -25 0 25 50 75 100 125 150 175 -50 Tc (C) 16/37 50 Tc (C) Tc (C) -25 0 25 50 75 Tc (C) Doc ID 12266 Rev 6 100 125 VND5050J-E / VND5050K-E Electrical specifications Figure 14. Status low output voltage Figure 15. On-state resistance vs Tcase Vstat (V) Ron (mOhm) 0.9 100 90 0.8 Istat=1.6mA Iout=2A Vcc=13V 80 0.7 70 0.6 60 0.5 50 0.4 40 0.3 30 0.2 20 0.1 10 0 0 -50 -25 0 25 50 75 100 125 150 -50 175 -25 0 25 50 75 100 125 150 175 Tc (C) Tc (C) Figure 16. Status leakage current Figure 17. On-state resistance vs VCC Ilstat (uA) Ron (mOhm) 0.055 100 90 0.05 Tc= 150C 80 Vstat=5V 70 0.045 Tc= 125C 60 0.04 0.035 50 Tc= 25C 40 Tc= -40C 30 20 0.03 10 0 0.025 -50 -25 0 25 50 75 100 125 150 0 175 5 10 15 20 25 30 35 40 Vcc (V) Tc (C) Figure 18. Status clamp voltage Figure 19. Openload on-state detection threshold Vscl (V) Iol (mA) 9 100 8.5 90 Istat=1mA 8 Vin=5V 80 7.5 70 7 60 6.5 50 6 40 5.5 30 5 20 4.5 10 4 0 -50 -25 0 25 50 75 100 125 150 175 -50 Tc (C) -25 0 25 50 75 100 125 150 175 Tc (C) Doc ID 12266 Rev 6 17/37 Electrical specifications VND5050J-E / VND5050K-E Figure 20. Openload off-state voltage detection threshold Figure 21. ILIM vs Tcase Ilimh (A) Vol (V) 25 5 22.5 4.5 Vcc=13V Vin=0V 4 20 3.5 17.5 3 15 2.5 12.5 2 10 1.5 7.5 5 1 -50 -25 0 25 50 75 100 125 150 -50 175 -25 0 25 50 75 100 125 150 175 Tc (C) Tc (C) Figure 22. Turn-on voltage slope Figure 23. Undervoltage shutdown dVout/dt(on) (V/ms) Vusd (V) 1000 14 900 Vcc=13V RI=6.5Ohm 800 12 700 10 600 8 500 400 6 300 4 200 2 100 0 0 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 Tc (C) 50 75 100 125 150 175 150 175 Tc (C) Figure 24. Turn-off voltage slope Figure 25. STAT_DIS clamp voltage dVout/dt(off) (V/ms) Vsdcl(V) 1000 14 900 Vcc=13V RI=6.5Ohm 800 12 Isd=1mA 700 10 600 8 500 400 6 300 4 200 2 100 0 0 -50 -25 0 25 50 75 100 125 150 175 -50 Tc (C) 18/37 -25 0 25 50 75 Tc (C) Doc ID 12266 Rev 6 100 125 VND5050J-E / VND5050K-E Electrical specifications Figure 26. High level STAT_DIS voltage Figure 27. Low level STAT_DIS voltage Vsdh(V) Vsdl(V) 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 -50 -25 0 25 50 75 100 125 150 175 -50 Tc (C) -25 0 25 50 75 100 125 150 175 Tc (C) Doc ID 12266 Rev 6 19/37 Application information 3 VND5050J-E / VND5050K-E Application information Figure 28. Application schematic +5V +5V VCC Rprot STAT_DIS Dld Rprot INPUT C OUTPUT Rprot STATUS GND VGND RGND DGND Note: Channel 2 has the same internal circuit as channel 1. 3.1 GND protection network against reverse battery 3.1.1 Solution 1: resistor in the ground line (RGND only) This can be used with any type of load. The following is an indication on how to dimension the RGND resistor. 1. RGND 600mV / (IS(on)max). 2. RGND (-VCC) / (-IGND) where -IGND is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device datasheet. Power Dissipation in RGND (when VCC<0: during reverse battery situations) is: PD= (-VCC)2/RGND This resistor can be shared amongst several different HSDs. Please note that the value of this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the maximum on-state currents of the different devices. Please note that if the microprocessor ground is not shared by the device ground then the RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output values. This shift will vary depending on how many devices are ON in the case of several high side drivers sharing the same RGND. 20/37 Doc ID 12266 Rev 6 VND5050J-E / VND5050K-E Application information If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then ST suggests to utilize Solution 2 (see below). 3.1.2 Solution 2: a diode (DGND) in the ground line A resistor (RGND=1k) should be inserted in parallel to DGND if the device drives an inductive load. This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of the ground network will produce a shift (600mV) in the input threshold and in the status output values if the microprocessor ground is not common to the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network. 3.2 Load dump protection Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the VCC max DC rating. The same applies if the device is subject to transients on the VCC line that are greater than the ones shown in the ISO 7637-2: 2004(E) table. 3.3 Microcontroller I/Os protection If a ground protection network is used and negative transient are present on the VCC line, the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to prevent the C I/Os pins to latch-up. The value of these resistors is a compromise between the leakage current of C and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of C I/Os. -VCCpeak/Ilatchup Rprot (VOHC-VIH-VGND) / IIHmax Calculation example: For VCCpeak= - 100V and Ilatchup 20mA; VOHC 4.5V 5k Rprot 180k Recommended values: Rprot =10k. 3.4 Open-load detection in off-state Off-state open load detection requires an external pull-up resistor (RPU) connected between OUTPUT pin and a positive supply voltage (VPU) like the +5V line used to supply the microprocessor. The external resistor has to be selected according to the following requirements: 1. no false open load indication when load is connected: in this case we have to avoid VOUT to be higher than VOlmin; this results in the following condition VOUT=(VPU/(RL+RPU))RL<VOlmin. 2. no misdetection when load is disconnected: in this case the VOUT has to be higher than VOLmax; this results in the following condition RPU<(VPU-VOLmax)/IL(off2). Doc ID 12266 Rev 6 21/37 Application information VND5050J-E / VND5050K-E Because Is(OFF) may significantly increase if Vout is pulled high (up to several mA), the pullup resistor RPU should be connected to a supply that is switched OFF when the module is in standby. The values of VOLmin, VOLmax and IL(off2) are available in the Electrical Characteristics section. Figure 29. Open-load detection in off-state V batt. VPU VCC RPU INPUT DRIVER + LOGIC IL(off2) OUT + STATUS R VOL GROUND 22/37 Doc ID 12266 Rev 6 RL VND5050J-E / VND5050K-E 3.5 Application information Maximum demagnetization energy (VCC = 13.5V) Figure 30. Maximum turn-off current versus inductance (for each channel) 100 A B C I (A) 10 1 0,1 1 10 100 L (mH) A: Tjstart = 150C single pulse B: Tjstart = 100C repetitive pulse C: Tjstart = 125C repetitive pulse VIN, IL Demagnetization Demagnetization Demagnetization t Note: Values are generated with RL =0 .In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves A and B. Doc ID 12266 Rev 6 23/37 Package and PCB thermal data VND5050J-E / VND5050K-E 4 Package and PCB thermal data 4.1 PowerSSO-12TM thermal data Figure 31. PowerSSO-12TM PC board Note: Layout condition of Rth and Zth measurements (PCB: Double layer, Thermal Vias, FR4 area= 77mm x 86mm,PCB thickness=1.6mm, Cu thickness=70m (front and back side), Copper areas: from minimum pad lay-out to 8cm2). Figure 32. Rthj-amb vs PCB copper area in open box free air condition (one channel on) RTHj _amb( C/ W) 70 65 60 55 50 45 40 35 30 0 2 4 6 PCB Cu heat sink area ( cm^ 2) 24/37 Doc ID 12266 Rev 6 8 10 VND5050J-E / VND5050K-E Package and PCB thermal data Figure 33. PowerSSO-12TM thermal impedance junction ambient single pulse (one channel on) ZTH ( C/ W) 100 Footprint 2 cm2 8 cm2 10 1 0,1 0,0001 0,001 0,01 0,1 1 Time ( s) 10 100 1000 Equation 1: pulse calculation formula Z TH = R TH +Z THtp (1 - ) where = tP/T Figure 34. Thermal fitting model of a double channel HSD in PowerSSO-12TM(a) a. The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered. Doc ID 12266 Rev 6 25/37 Package and PCB thermal data Table 16. 26/37 VND5050J-E / VND5050K-E PowerSSO-12TM thermal parameters Area/island (cm2) Footprint R1= R7 (C/W) 0.7 R2= R8 (C/W) 2.8 R3 (C/W) 4 R4 (C/W) 2 8 8 8 7 R5 (C/W) 22 15 10 R6 (C/W) 26 20 15 C1= C7 (W.s/C) 0.001 C2= C8 (W.s/C) 0.0025 C3 (W.s/C) 0.05 C4 (W.s/C) 0.2 0.1 0.1 C5 (W.s/C) 0.27 0.8 1 C6 (W.s/C) 3 6 9 Doc ID 12266 Rev 6 VND5050J-E / VND5050K-E 4.2 Package and PCB thermal data PowerSSO-24TM thermal data Figure 35. PowerSSO-24TM PC board Note: Layout condition of Rth and Zth measurements (PCB: Double layer, Thermal Vias, FR4 area= 77mm x 86mm, PCB thickness=1.6mm, Cu thickness=70m (front and back side), Copper areas: from minimum pad lay-out to 8cm2). Figure 36. Rthj-amb vs PCB copper area in open box free air condition (one channel on) RTHj_amb(C/W) 55 50 45 40 35 30 0 2 4 6 8 10 PCB Cu heatsink area (cm^2) Doc ID 12266 Rev 6 27/37 Package and PCB thermal data VND5050J-E / VND5050K-E Figure 37. PowerSSO-24TM thermal impedance junction ambient single pulse (one channel on) Equation 2: pulse calculation formula Z TH = R TH +Z THtp (1 - ) where = tP/T Figure 38. Thermal fitting model of a double channel HSD in PowerSSO-24TM(b) b. The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered. 28/37 Doc ID 12266 Rev 6 VND5050J-E / VND5050K-E Table 17. Package and PCB thermal data PowerSSO-24TM thermal parameters Area/island (cm2) Footprint R1=R7 (C/W) 0.4 R2=R8 (C/W) 2 R3 (C/W) 6 R4 (C/W) 7.7 R5 (C/W) 2 8 9 9 8 R6 (C/W) 28 17 10 C1=C7 (W.s/C) 0.001 C2=C8 (W.s/C) 0.0022 C3 (W.s/C) 0.025 C4 (W.s/C) 0.75 C5 (W.s/C) 1 4 9 C6 (W.s/C) 2.2 5 17 Doc ID 12266 Rev 6 29/37 Package and packing information VND5050J-E / VND5050K-E 5 Package and packing information 5.1 ECOPACK(R) packages In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. 5.2 PowerSSO-12TM package information Figure 39. PowerSSO-12TM package dimensions 30/37 Doc ID 12266 Rev 6 VND5050J-E / VND5050K-E Table 18. Package and packing information PowerSSO-12TM mechanical data Symbol Millimeters Min. Typ. Max. A 1.25 1.62 A1 0 0.1 A2 1.10 1.65 B 0.23 0.41 C 0.19 0.25 D 4.8 5.0 E 3.8 4.0 e 0.8 H 5.8 6.2 h 0.25 0.5 L 0.4 1.27 k 0 8 X 1.9 2.5 Y 3.6 4.2 ddd 0.1 Doc ID 12266 Rev 6 31/37 Package and packing information 5.3 VND5050J-E / VND5050K-E PowerSSO-24TM package information Figure 40. PowerSSO-24TM package dimensions Table 19. PowerSSO-24TM mechanical data Symbol Millimeters Min. Typ. A 2.45 A2 2.15 2.35 a1 0 0.1 b 0.33 0.51 c 0.23 0.32 D 10.10 10.50 E 7.4 7.6 e 0.8 e3 8.8 F 2.3 G H 32/37 Max. 0.1 10.1 Doc ID 12266 Rev 6 10.5 VND5050J-E / VND5050K-E Table 19. Package and packing information PowerSSO-24TM mechanical data (continued) Symbol Millimeters Min. Typ. h Max. 0.4 k 0deg 8deg L 0.55 0.85 O 1.2 Q 0.8 S 2.9 T 3.65 U 1.0 N 10deg X 4.1 4.7 Y 6.5 7.1 Doc ID 12266 Rev 6 33/37 Package and packing information 5.4 VND5050J-E / VND5050K-E PowerSSO-12TM packing information Figure 41. PowerSSO-12TM tube shipment (no suffix) B Base Q.ty Bulk Q.ty Tube length ( 0.5) A B C ( 0.1) C A 100 2000 532 1.85 6.75 0.6 All dimensions are in mm. Figure 42. PowerSSO-12TM tape and reel shipment (suffix "TR") REEL DIMENSIONS Base Q.ty Bulk Q.ty A (max) B (min) C ( 0.2) F G (+ 2 / -0) N (min) T (max) 2500 2500 330 1.5 13 20.2 12.4 60 18.4 TAPE DIMENSIONS According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing W P0 ( 0.1) P D ( 0.05) D1 (min) F ( 0.1) K (max) P1 ( 0.1) 12 4 8 1.5 1.5 5.5 4.5 2 All dimensions are in mm. End Start Top cover tape No components Components Empty components pockets saled with cover tape. User direction of feed 34/37 Doc ID 12266 Rev 6 No components 500mm min 500mm min VND5050J-E / VND5050K-E 5.5 Package and packing information PowerSSO-24TM packing information Figure 43. PowerSS0-24TM tube shipment (no suffix) C Base Qty Bulk Qty Tube length (0.5) A B C (0.1) B 49 1225 532 3.5 13.8 0.6 All dimensions are in mm. A Figure 44. PowerSSO-24TM tape and reel shipment (suffix "TR") REEL DIMENSIONS Base Qty Bulk Qty A (max) B (min) C ( 0.2) F G (+2 / -0) N (min) T (max) 1000 1000 330 1.5 13 20.2 24.4 100 30.4 TAPE DIMENSIONS According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing W P0 ( 0.1) P D ( 0.05) D1 (min) F ( 0.1) K (max) P1 ( 0.1) 24 4 12 1.55 1.5 11.5 2.85 2 End All dimensions are in mm. Start Top cover tape No components Components 500mm min No components 500mm min Empty components pockets sealed with cover tape. User direction of feed Doc ID 12266 Rev 6 35/37 Revision history 6 VND5050J-E / VND5050K-E Revision history Table 20. Document revision history Date Revision 30-Mar-2006 1 Initial release. 11-Jan-2007 2 Minor formatting changes. New disclaimer attached. 3 Reformatted and restructured. Contents and lists of tables and figures added. Section 3.5: Maximum demagnetization energy (VCC = 13.5V) added. Table 4: Absolute maximum ratings: EMAX entries updated. Table 13: Electrical transient requirements (part 1/3):Test level values III and IV for test pulse 5b and notes updated Figure 34: Thermal fitting model of a double channel HSD in PowerSSO-12TM, Figure 38: Thermal fitting model of a double channel HSD in PowerSSO-24TM: added notes. Features table updated: ILIMH changed from 19 to 18A. 4 Updated Section 4.1: PowerSSO-12TM thermal data: - Changed Figure 32: Rthj-amb vs PCB copper area in open box free air condition (one channel on). - Changed Figure 33: PowerSSO-12TM thermal impedance junction ambient single pulse (one channel on). - Updated Table 16: PowerSSO-12TM thermal parameters: R3 value changed from 7 to 4 C/W. R4 values changed from 10 /10 /10 to 8 /8 /7 C/W. 5 Table 19: PowerSSO-24TM mechanical data: - Deleted A (min) value - Changed A (max) value from 2.47 to 2.45 - Changed A2 (max) value from 2.40 to 2.35 - Changed a1 (max) value from 0.075 to 0.1 - Added F and k rows 6 Updated Figure 40: PowerSSO-24TM package dimensions. Updated Table 19: PowerSSO-24TM mechanical data: - Deleted G1 row - Added O, Q, S, T and U rows. 31-May-2007 03-Dec-2007 17-Jun-2009 22-Jul-2009 36/37 Changes Doc ID 12266 Rev 6 VND5050J-E / VND5050K-E Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. (c) 2009 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com Doc ID 12266 Rev 6 37/37