Single-Supply, Low Cost
Instrumentation Amplifier
AD8223
Rev. 0
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved.
FEATURES
Gain set with 1 resistor
Gain = 5 to 1000
Inputs
Voltage range to 150 mV below negative rail
25 nA maximum input bias current
30 nV/√Hz, RTI noise @ 1 kHz
Power supplies
Dual supply: ±2 V to ±12 V
Single supply: 3 V to 24 V
500 μA maximum supply current
APPLICATIONS
Low power medical instrumentation
Transducer interface
Thermocouple amplifiers
Industrial process controls
Difference amplifiers
Low power data acquisition
CONNECTION DIAGRAM
–RG1
–IN 2
+IN 3
–VS4
+RG
8
+VS
7
OUT
6
REF
5
–
+
AD8223
06925-001
Figure 1. 8-Lead SOIC (R) and 8-Lead MSOP (RM) Packages
Table 1. Instrumentation Amplifiers by Category
General-
Purpose Zero Drift
Mil
Grade
Low
Power
High Voltage
PGA
AD82201 AD82311 AD620 AD6271 AD8250
AD8221 AD85531 AD621 AD6231 AD8251
AD8222 AD85551 AD524 AD8223 AD8253
AD82241 AD85561 AD526
AD8228 AD85571 AD624
1 Rail-to-rail output.
GENERAL DESCRIPTION
The AD8223 is an integrated single-supply instrumentation
amplifier that delivers rail-to-rail output swing on a single
supply (3 V to 24 V). The AD8223 conforms to the 8-lead
industry standard pinout configuration.
The AD8223 is simple to use: one resistor sets the gain. With no
external resistor, the AD8223 is configured for G = 5. With an
external resistor, the AD8223 can be programmed for gains up
to 1000.
The AD8223 has a wide input common-mode range and can
amplify signals that have a 150 mV common-mode voltage
below ground. Although the design of the AD8223 is optimized
to operate from a single supply, the AD8223 still provides
excellent performance when operated from a dual voltage
supply (±2 V to ±12 V).
Low power consumption (1.5 mW at 3 V), wide supply voltage
range, and rail-to-rail output swing make the AD8223 ideal for
battery-powered applications. The rail-to-rail output stage
maximizes the dynamic range when operating from low supply
voltages. The AD8223 replaces discrete instrumentation
amplifier designs and offers superior linearity, temperature
stability, and reliability in a minimum of space.
AD8223
Rev. 0 | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Connection Diagram ....................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Single Supply ................................................................................. 3
Dual Supply ................................................................................... 5
Absolute Maximum Ratings ............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution .................................................................................. 7
Pin Configuration and Function Descriptions ............................. 8
Typical Performance Characteristics ............................................. 9
Theory of Operation ...................................................................... 14
Amplifier Architecture .............................................................. 14
Gain Selection ............................................................................. 14
Input Voltage Range ................................................................... 14
Reference Terminal .................................................................... 15
Input Protection ......................................................................... 15
RF Interference (RFI) ................................................................. 15
Ground Returns for Input Bias Currents ................................ 16
Applications Information .............................................................. 17
Basic Connection ....................................................................... 17
Differential Output .................................................................... 17
Output Buffering ........................................................................ 17
Cables ........................................................................................... 17
A Single-Supply Data Acquisition System .............................. 18
Amplifying Signals with Low Common-Mode Voltage ........ 18
Outline Dimensions ....................................................................... 19
Ordering Guide .......................................................................... 20
REVISION HISTORY
10/08—Revision 0: Initial Version
AD8223
Rev. 0 | Page 3 of 20
SPECIFICATIONS
SINGLE SUPPLY
TA = 25°C, −VS = 0 V, +VS = +5 V, and RL = 10 kΩ to 2.5 V, unless otherwise noted.
Table 2
Parameter
AD8223A AD8223B
Conditions Min Typ Max Min Typ Max Unit
COMMON-MODE REJECTION RATIO
DC to 60 Hz with 1 kΩ Source
Imbalance
VCM = 0 V to 3 V
G = 5 80 86 dB
G = 10 86 90 dB
G = 100 90 96 dB
G = 1000 90 96 dB
NOISE VIN+ = VIN− = VREF = 0 V
Voltage Noise, 1 kHz
G = 5 50 50 nV/√Hz
G = 1000 30 30 nV/√Hz
RTI, 0.1 Hz to 10 Hz
G = 5 1.0 1.0 μV p-p
G = 1000 0.6 0.6 μV p-p
Current Noise, 1 kHz 70 70 fA/√Hz
0.1 Hz to 10 Hz 1.2 1.2 pA p-p
VOLTAGE OFFSET Total RTI error =
VOSI + VOSO/G
Input Offset, VOSI 250 100 μV
Over Temperature TA = −40°C to +85°C 400 160 μV
Average TC TA = −40°C to +85°C 2 1 μV/°C
Output Offset, VOSO 1500 1000 μV
Over Temperature TA = −40°C to +85°C 2000 1500 μV
Average TC TA = −40°C to +85°C 15 10 μV/°C
Offset Referred to Input vs.
Supply (PSR)
+VS = 4 V to 24 V,
−VS = 0 V
G = 5 80 86 dB
G = 10 86 90 dB
G = 100 90 96 dB
G = 1000 90 96 dB
INPUT CURRENT
Input Bias Current 5 12 25 5 12 25 nA
Over Temperature TA = −40°C to +85°C 5 28 5 28 nA
Average Temperature
Coefficient
TA = −40°C to +85°C 50 50 pA/°C
Input Offset Current 0.25 2 0.25 2 nA
Over Temperature TA = −40°C to +85°C 2.5 2.5 nA
Average Temperature
Coefficient
TA = −40°C to +85°C 5 5 pA/°C
DYNAMIC RESPONSE
Small Signal −3 dB Bandwidth
G = 5 125 125 kHz
G = 10 125 125 kHz
G = 100 50 50 kHz
G = 1000 5 5 kHz
Slew Rate 0.2 0.2 V/μs
AD8223
Rev. 0 | Page 4 of 20
Parameter
AD8223A AD8223B
Conditions Min Typ Max Min Typ Max Unit
Settling Time to 0.01% Step size = 3.5 V
G = 5 18 18 μs
G = 10 18 18 μs
G = 100 18 18 μs
G = 1000 85 85 μs
GAIN G = 5 + (80 kΩ/RG)
Gain Range 5 1000 5 1000 V/V
Gain Error1 V
OUT = 0.05 V to 4.5 V
G = 5 0.07 0.02 %
G = 10 0.10 0.3 0.10 0.2 %
G = 100 0.10 0.3 0.10 0.3 %
G = 1000 0.10 0.3 0.10 0.3 %
Nonlinearity VOUT = 0.05 V to 4.5 V
G = 5 12 12 ppm
G = 1000 200 200 ppm
Gain vs. Temperature TA = −40°C to +85°C
G = 5 10 2 ppm/°C
G > 51 50 50 ppm/°C
INPUT
Input Impedance
Differential 2||2 2||2 GΩ||pF
Common-Mode 2||2 2||2 GΩ||pF
Common-Mode Input Voltage
Range2
VIN+ = VIN− (−VS) −
0.15
(+VS) −
1.5
(−VS) −
0.15
(+VS) −
1.5
V
OUTPUT
Output Swing RL = 10 kΩ to ground +0.01 (+VS) −
0.5
+0.01 (+VS) −
0.5
V
R
L = 100 kΩ to ground +0.01 (+VS) −
0.15
+0.01 (+VS) −
0.15
V
REFERENCE INPUT
RIN 60 ±20% 60 ±20% kΩ
IIN VIN+ = VIN− = VREF = 0 V +10 +20 +10 +20 μA
Voltage Range −VS +VS −VS +VS V
Gain to Output 1 ±
0.0002
1 ±
0.0002
V
POWER SUPPLY
Operating Range +3 +24 +3 +24 V
Quiescent Current 350 500 350 500 μA
Over Temperature TA = −40°C to +85°C 600 600 μA
TEMPERATURE RANGE
For Specified Performance -40 +85 −40 +85 °C
1 Does not include effects of external resistor, RG.
2 Total input range depends on common-mode voltage, differential voltage, and gain. See Figure 18 through Figure 21, and the Input Voltage Range section in the
Theory of Operation section for more information.
AD8223
Rev. 0 | Page 5 of 20
DUAL SUPPLY
TA = 25°C, −VS = −12 V, +VS = +12 V, and RL = 10 k to ground, unless otherwise noted.1
Table 3.
Parameter
AD8223A AD8223B
Conditions Min Typ Max Min Typ Max Unit
COMMON-MODE REJECTION RATIO
DC to 60 Hz with 1 kΩ Source
Imbalance
VCM = −10 V to 10 V
G = 5 80 86 dB
G = 10 86 90 dB
G = 100 90 96 dB
G = 1000 90 96 dB
NOISE VIN+ = VIN− = VREF = 0 V
Voltage Noise, 1 kHz
G = 5 50 50 nV/√Hz
G = 1000 30 30 nV/√Hz
RTI, 0.1 Hz to 10 Hz
G = 5 1.0 1.0 μV p-p
G = 1000 0.6 0.6 μV p-p
Current Noise, 1 kHz 70 70 fA/√Hz
0.1 Hz to 10 Hz 1.2 1.2 pA p-p
VOLTAGE OFFSET Total RTI error =
VOSI + VOSO/G
Input Offset, VOSI 250 100 μV
Over Temperature TA = −40°C to +85°C 400 160 μV
Average TC TA = −40°C to +85°C 2 1 μV/°C
Output Offset, VOSO 1500 1000 μV
Over Temperature TA = −40°C to +85°C 2000 1500 μV
Average TC TA = −40°C to +85°C 15 10 μV/°C
Offset Referred to Input vs.
Supply (PSR)
+VS = 5 V to 12 V,
−VS = −5 V to −12 V
G = 5 80 86 dB
G = 10 86 90 dB
G = 100 90 96 dB
G = 1000 90 96 dB
INPUT CURRENT
Input Bias Current 5 12 25 5 12 25 nA
Over Temperature TA = −40°C to +85°C 5 28 5 28 nA
Average Temperature
Coefficient
TA = −40°C to +85°C 50 50 pA/°C
Input Offset Current 0.25 2 0.25 2 nA
Over Temperature TA = −40°C to +85°C 2.5 2.5 nA
Average Temperature
Coefficient
TA = −40°C to +85°C 5 5 pA/°C
DYNAMIC RESPONSE
Small Signal −3 dB Bandwidth
G = 5 200 200 kHz
G = 10 200 200 kHz
G = 100 70 70 kHz
G = 1000 7 7 kHz
Slew Rate 0.3 0.3 V/μs
Settling Time to 0.01% Step size = 10 V
G = 5 30 30 μs
G = 10 30 30 μs
G = 100 30 30 μs
G = 1000 150 150 μs
AD8223
Rev. 0 | Page 6 of 20
Parameter
AD8223A AD8223B
Conditions Min Typ Max Min Typ Max Unit
GAIN G = 5 + (80 kΩ/RG)
Gain Range 5 1000 5 1000 V/V
Gain Error2 V
OUT = −10 V to +10 V
G = 5 0.07 0.02 %
G = 10 0.10 0.3 0.10 0.2 %
G = 100 0.10 0.3 0.10 0.3 %
G = 1000 0.10 0.3 0.10 0.3 %
Nonlinearity VOUT = −10 V to +10 V
G = 5 5 5 ppm
G = 1000 30 30 ppm
Gain vs. Temperature TA = −40°C to +85°C
G = 5 10 2 ppm/°C
G > 51 50 50 ppm/°C
INPUT
Input Impedance
Differential 2||2 2||2 GΩ||pF
Common-Mode 2||2 2||2 GΩ||pF
Common-Mode Input Voltage
Range3
VIN+ = VIN− (−VS) −
0.15
(+VS) −
1.5
(−VS) −
0.15
(+VS) −
1.5
V
OUTPUT
Output Swing RL = 10 kΩ to ground (−VS) +
0.3
(+VS) −
0.8
(−VS) +
0.3
(+VS) −
0.8
V
R
L = 100 kΩ to ground (−VS) +
0.1
(+VS) −
0.3
(−VS) +
0.1
(+VS) −
0.3
V
REFERENCE INPUT
RIN 60 ±20% 60 ±20% kΩ
IIN VIN+ = VIN− = VREF = 0 V +10 +20 +10 +20 μA
Voltage Range −VS +VS −VS +VS V
Gain to Output 1 ±
0.0002
1 ±
0.0002
V
POWER SUPPLY
Operating Range ±2 ±12 ±2 ±12 V
Quiescent Current 650 650 μA
Over Temperature TA = −40°C to +85°C 850 850 μA
TEMPERATURE RANGE
For Specified Performance −40 +85 −40 +85 °C
1 Because maximum supply voltage is 24 V between the negative and positive supply, these specifications at ±12V are at the part’s limit. Operation at a nominal supply
voltage slightly less than ±12 V is recommended to allow for power supply tolerances.
2 Does not include effects of external resistor, RG.
3 Total input range depends on common-mode voltage, differential voltage, and gain. See Figure 18 through Figure 21 and the Input Voltage Range section in the
Theory of Operation section for more information.
AD8223
Rev. 0 | Page 7 of 20
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter Rating
Supply Voltage ±12 V
Internal Power Dissipation 650 mW
Differential Input Voltage ±VS
Output Short-Circuit Duration Indefinite
Storage Temperature Range (R, RM) −65°C to +125°C
Operating Temperature Range −40°C to +85°C
Lead Temperature (Soldering, 10 sec) 300°C
ESD (Human Body Model) 1.5 kV
ESD (Charge Device Model) 500 V
ESD (Machine Model) 100 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Specification is for the device in free air.
Table 5. Thermal Resistance
Package Type θJA Unit
8-Lead SOIC (R) 155 °C/W
8-Lead MSOP (RM) 200 °C/W
ESD CAUTION
AD8223
Rev. 0 | Page 8 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
–RG1
–IN 2
+IN 3
–VS4
+RG
8
+VS
7
OUT
6
REF
5
06925-002
AD8223
TOP VIEW
(Not to Scale)
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Descriptions
1 −RG Gain Resistor Terminal.
2 −IN Negative Input.
3 +IN Positive Input.
4 −VS Negative Supply.
5 REF Reference. Connect to a low impedance source. Output is referenced to this node.
6 OUT Output.
7 +VS Positive Supply.
8 +RG Gain Resistor Terminal.
AD8223
Rev. 0 | Page 9 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VS = ±5 V, RL = 10 k, unless otherwise noted.
700
0
–12.0
06925-061
INPUT BIAS CURRENT (nA)
NUMBER OF UNITS
600
500
400
300
200
100
–13.8 –13.5 –13.2 –12.9 –12.6 –12.3
N = 4720
MEAN = –12.9448
SD = 0.317868
Figure 3. Typical Distribution of Input Bias Current
0
1.2
06925-062
INPUT OFFSET CURRENT (nA)
NUMBER OF UNITS
1000
800
600
400
200
–0.9 –0.6 –0.3 0 0.3 0.6 0.9
N = 4720
MEAN = –0.00571517
SD = 0.172282
Figure 4. Typical Distribution of Input Offset Current
0
–0.015 0.015
06925-063
GAIN ERROR, G = 5 (%)
NUMBER OF UNITS
1400
1200
1000
800
600
400
200
–0.010 –0.005 0 0.005 0.010
N = 5036
MEAN = –0.00336179
SD = 0.00155048
Figure 5. Typical Distribution for Gain Error (G = 5)
1000
10
0.1 100k
06925-050
FREQUENCY (Hz)
VOLTAGE NOISE DENSITY (nV/ Hz)
1 10 100 1k 10k
100
G = 1000
BW LIMIT G = 100
BW LIMIT
G = 5 G = 10
Figure 6. Voltage Noise Density vs. Frequency
15
0
25
20
10
5
TEMPERATURE (°C)
I
BIAS
(nA)
–60 –40 –20 0 20 40 60 80 100 120 140
06925-064
Figure 7. IBIAS vs. Temperature
1000
100
10
0.01 1k
FREQUENCY (Hz)
CURRENT NOISE DENSITY (fA/ Hz)
06925-065
0.1 1 10 100
Figure 8. Current Noise Density vs. Frequency
AD8223
Rev. 0 | Page 10 of 20
18
0
–12 10
06925-013
CMV (V)
I
BIAS
(nA)
16
14
12
10
8
6
4
2
–10 –8 –6 –4 –2 0 2 4 6 8
±V
S
= ±12V
±V
S
= ±5V ±V
S
= ±2.5V
Figure 9. IBIAS vs. CMV
1s/DIV
500fA/DIV
06925-066
Figure 10. 0.1 Hz to 10 Hz Current Noise
06925-054
1s/DIV0.5µV/DIV
G = 5
G = 1000
Figure 11. 0.1 Hz to 10 Hz RTI and RTO Voltage Noise
120
30
1100k
06925-055
FREQUENCY (Hz)
CMRR (dB)
10 100 1k 10k
110
100
90
80
70
60
50
40
G = 5
G = 1000
G = 10G = 100
Figure 12. CMRR vs. Frequency, ±VS = ±12
120
30
1100k
06925-056
FREQUENCY (Hz)
CMRR (dB)
10 100 1k 10k
110
100
90
80
70
60
50
40
G = 5
G = 1000
G = 10
G = 100
Figure 13. CMRR vs. Frequency, +VS = +5 V
70
–30
100 1M
FREQUENCY (Hz)
GAIN (dB)
1k 10k 100k
60
50
40
30
20
10
0
–10
–20
G = 1000
G = 100
G = 10
G = 5
06925-018
Figure 14. Gain vs. Frequency, ±VS = ±12 V
AD8223
Rev. 0 | Page 11 of 20
70
–30
100 1M
FREQUENCY (Hz)
GAIN (dB)
1k 10k 100k
60
50
40
30
20
10
0
–10
–20
G = 1000
G = 100
G = 10
G = 5
06925-067
Figure 15. Gain vs. Frequency, +VS = +5 V
25
0
0.1 100
06925-068
FREQUENCY (kHz)
OUTPUT VOLTAGE (V p-p)
110
20
15
10
5
±12V
±5V
±2.5V
Figure 16. Large Signal Frequency Response
0.04
0.20
214
06925-069
SUPPLY VOLTAGE (±V
S
)
SLEW RATE (V/μs)
0.38
0.36
0.34
0.32
0.30
0.28
0.26
0.24
0.22
4681012
Figure 17. Slew Rate vs. Supply Voltage
4
–6
–6 6
06925-070
MAXIMUM OUTPUT VOLTAGE (V)
COMMON-MODE INPUT (V)
3
2
1
0
–1
–2
–3
–4
–5
–4 –2 0 2 4
±V
S
= ±5V
±V
S
= ±2.5V
+V
S
= +5V
Figure 18. Common-Mode Input vs. Maximum Output Voltage,
G = 5, Small Supplies
15
–15
–15 15
06925-071
MAXIMUM OUTPUT VOLTAGE (V)
COMMON-MODE INPUT (V)
10
5
0
–5
–10
–10 –5 0 5 10
Figure 19. Common-Mode Input vs. Maximum Output Voltage,
G = 5, ±VS = ±12 V
4
–6
–6 6
06925-072
MAXIMUM OUTPUT VOLTAGE (V)
COMMON-MODE INPUT (V)
3
2
1
0
–1
–2
–3
–4
–5
–4 –2 0 2 4
±V
S
= ±5V
±V
S
= ±2.5V
+V
S
= +5V
Figure 20. Common-Mode Input vs. Maximum Output Voltage,
G = 100, Small Supplies
AD8223
Rev. 0 | Page 12 of 20
15
–15
–15 15
06925-073
MAXIMUM OUTPUT VOLTAGE (V)
COMMON-MODE INPUT (V)
10
5
0
–5
–10
–10 –5 0 5 10
Figure 21. Common-Mode Input vs. Maximum Output Voltage,
G = 100, ±VS = ±12 V
140
0
1 100k
FREQUENCY (Hz)
PSRR (dB)
10 100 1k 10k
120
100
80
60
40
20
G = 1000
G = 10
G = 5
G = 100
06925-023
Figure 22. Positive PSRR vs. Frequency, ±VS = ±12 V
140
0
1 100k
FREQUENCY (Hz)
PSRR (dB)
10 100 1k 10k
120
100
80
60
40
20
G = 1000
G = 5
G = 100
G = 10
06925-024
Figure 23. Positive PSRR vs. Frequency, +VS = +5 V
120
0
1 100k
FREQUENCY (Hz)
PSRR (dB)
10 100 1k 10k
G = 1000
G = 10
06925-025
100
80
60
40
20
G = 100
G = 5
Figure 24. Negative PSRR vs. Frequency, ±VS = ±12 V
06925-051
100µs/DIV
0.1%/DIV
5V/DIV
Figure 25. Large Signal Response, G = 5
06925-052
100µs/DIV
0.1%/DIV
5V/DIV
Figure 26. Large Signal Pulse Response, G = 100, CL = 100 pF
AD8223
Rev. 0 | Page 13 of 20
06925-053
100µs/DIV
0.1%/DIV
5V/DIV
Figure 27. Large Signal Pulse Response, G = 1000, CL = 100 pF
06925-028
2
G = 100
G = 5
G = 10
10µs/DIV20mV/DIV
Figure 28. Small Signal Pulse Response, G = 5, 10, 100; RL = 10 kΩ
06925-034
2
100µs/DIV20mV/DIV
Figure 29. Small Signal Pulse Response, G = 1000, RL = 25 kΩ, CL = 100 pF
0.01 0.1 1 10
06925-074
OUTPUT CURRENT (mA)
OUTPUT VOLTAGE SWING (V)
REFERRED TO SUPPLY VOLTAGES
–V
S
+1
+2
–2
–1
+
V
S
SOURCING
SINKING
Figure 30. Output Voltage Swing vs. Output Current
AD8223
Rev. 0 | Page 14 of 20
THEORY OF OPERATION
AMPLIFIER ARCHITECTURE
The AD8223 is an instrumentation amplifier based on a
classic 3-op amp approach, modified to ensure operation
even at common-mode voltages at the negative supply rail.
The architecture allows lower voltage offsets, better CMRR,
and higher gain accuracy than competing instrumentation
amplifiers in its class.
+
–
8kΩ10kΩ50kΩ
POSITIVE SUPPLY
7
INVERTIN
G
2
14
8kΩ10kΩ50kΩ
8
4
NEGATIVE SUPPLY
NON-
INVERTIN
G
3
7
GAIN OUT
6
REF
5
+
–
+
–
06925-038
Figure 31. Simplified Schematic
Figure 31 shows a simplified schematic of the AD8223. The
AD8223 has three stages. In the first stage, the input signal is
applied to PNP transistors. These PNP transistors act as voltage
buffers and allow input voltages below ground. The second
stage consists of a pair of 8 k resistors, the RG resistor, and a
pair of amplifiers. This stage allows the amplification of the
AD8223 to be set with a single external resistor. The third stage
is a differential amplifier composed of an op amp, two 10 k
resistors, and two 50 k resistors. This stage removes the
common-mode signal and applies an additional gain of 5.
The transfer function of the AD8223 is
VOUT = G(VIN+ − VIN−) + VREF
where:
GR
Gk08
5
GAIN SELECTION
Placing a resistor across the RG terminals sets the gain of the
AD8223, which can be calculated by referring to Table 7 or by
using the following gain equation:
5
k80
G
RG
Table 7. Gains Achieved Using 1% Resistors
1% Standard Table
Value of RG (Ω) Desired Gain Calculated Gain
26.7 k 8 7.99
15.8 k 10 10.1
5.36 k 20 19.9
2.26 k 40 40.4
1.78 k 50 49.9
845 100 99.7
412 200 199
162 500 499
80.6 1000 998
The AD8223 defaults to G = 5 when no gain resistor is used. Add
the tolerance and gain drift of the RG resistor to the specifications
of the AD8223 to determine the total gain accuracy of the system.
When the gain resistor is not used, gain depends only on
internal resistor matching, so gain error and gain drift are
minimal.
INPUT VOLTAGE RANGE
The 3-op amp architecture of the AD8223 applies gain and then
removes the common-mode voltage. Therefore, internal nodes
in the AD8223 experience a combination of both the gained
signal and the common-mode signal. This combined signal can
be limited by the voltage supplies even when the individual input
and output signals are not. To determine whether the signal can be
limited, refer to Figure 18 through Figure 21. Alternatively, use
the parameters in the Specifications section to verify that the input
and output are not limited and then use the following formula to
make sure the internal nodes are not limited.
To check if it is limited by the internal nodes,
V1.0
10
6.0V01.0
S
DIFF
CMS V
GainV
VV
If more common-mode range is required, a solution is to apply less
gain in the instrumentation amplifier and more in a later stage.
AD8223
Rev. 0 | Page 15 of 20
REFERENCE TERMINAL
The output voltage of the AD8223 is developed with respect to
the potential on the reference terminal. This is useful when the
output signal needs to be offset to a precise midsupply level. For
example, a voltage source can be tied to the REF pin to level-
shift the output so that the AD8223 can drive a single-supply
ADC. The REF pin is protected with ESD diodes and should
not exceed either +VS or −VS by more than 0.3 V.
For best performance, keep the source impedance to the REF
terminal below 5 Ω. As shown in Figure 31, the reference
terminal, REF, is at one end of a 50 k resistor. Additional
impedance at the REF terminal adds to this resistor and results
in poorer CMRR performance.
INCORRECT
AD8223
VREF
CORRECT
AD8223
OP2177
+
–
VREF
06925-039
Figure 32. Driving the Reference Pin
INPUT PROTECTION
Internal supply referenced clamping diodes allow the input,
reference, output, and gain terminals of the AD8223 to safely
withstand overvoltages of 0.3 V above or below the supplies.
This is true for all gains, and for power-on and power-off. This
last case is particularly important because the signal source and
amplifier can be powered separately.
If the overvoltage is expected to exceed this value, limit the
current through these diodes to about 10 mA using external
current limiting resistors. This is shown in Figure 33. The size
of this resistor is defined by the supply voltage and the required
overvoltage protection.
10mA
1 = 10mA MAX
OUT
AD8223
+
–V
OVER
– V
S
+ 0.7V
+
V
S
–V
S
R
G
R
LIM
R
LIM
R
LIM
=
V
OVER
V
OVER
06925-040
Figure 33. Input Protection
RF INTERFERENCE (RFI)
RF rectification is often a problem when amplifiers are used in
applications where there are strong RF signals. The disturbance
can appear as a small dc offset voltage. High frequency signals
can be filtered with a low-pass, R-C network placed at the input
of the instrumentation amplifier, as shown in Figure 34. The
filter limits the input signal bandwidth according to the follow-
ing relationship:
)(22
1
CD
Diff CCR
FilterFreq
C
CM RC
FilterFreq
2
1
where CD ≥ 10CC.
R
R
AD8223
+15
V
+IN
–IN
0.1µF 10µF
10µF
0.1µF
REF
V
OUT
–15V
R1
499Ω
C
D
47nF
C
C
1nF
C
C
1nF
4.02kΩ
4.02kΩ
+
–
+
+
06925-041
Figure 34. RFI Suppression
Figure 34 shows an example in which the differential filter fre-
quency is approximately 400 Hz, and the common-mode filter
frequency is approximately 40 kHz. The typical dc offset shift
over frequency is less than 1.5 µV, and the RF signal rejection
of the circuit is better than 71 dB.
The resistors were selected to be large enough to isolate the
circuit input from the capacitors but not large enough to
significantly increase the circuit noise. Choose values of R and
CC to minimize RFI. Mismatch between the R × CC at positive
input and the R × CC at negative input degrades the CMRR of
the AD8223. Because of their higher accuracy and stability,
COG/NPO type ceramic capacitors are recommended for the
CC capacitors. The dielectric for the CD capacitor is not as
critical.
AD8223
Rev. 0 | Page 16 of 20
GROUND RETURNS FOR INPUT BIAS CURRENTS
Input bias currents are those dc currents that must flow to bias
the input transistors of an amplifier. These are usually transistor
base currents. When amplifying floating input sources such as
transformers or ac-coupled sources, there must be a direct dc
path into each input so that the bias current can flow. Figure 35
shows how a bias current path can be provided for the cases of
transformer coupling, capacitive ac-coupling, and a thermo-
couple application.
In dc-coupled resistive bridge applications, providing this path
is generally not necessary because the bias current simply flows
from the bridge supply through the bridge and into the amplifier.
However, if the impedances that the two inputs see are large and
differ by a large amount (>10 k), the offset current of the input
stage causes dc errors proportional to the input offset voltage of
the amplifier.
THERMOCOUPLE
+V
S
REF
–V
S
AD8223
CAPACITIVELY COUPLED
+V
S
REF
C
C
–V
S
AD8223
TRANSFORMER
+V
S
REF
–V
S
AD8223
INCORREC
T
CAPACITIVELY COUPLED
+V
S
REF
C
R
R
C
–V
S
AD8223
1
f
HIGH-PASS
= 2πRC
THERMOCOUPLE
+V
S
REF
–V
S
10MΩ
AD8223
TRANSFORMER
+V
S
REF
–V
S
AD8223
CORRECT
0
6925-042
Figure 35. Creating an IBIAS Path
AD8223
Rev. 0 | Page 17 of 20
APPLICATIONS INFORMATION
+2V TO +12V
REF (INPUT)
–2V TO –12V
REF
OUTPUT
+3V TO +24V
+
–
+
–
+
V
S
10µF0.1µF 10µF0.1µF
10µF0.1µF
++
V
OUT
+
R
G
R
G
R
G
V
IN
–V
S
REF (INPUT)
REF
OUTPUT
+
V
S
V
OUT
R
G
R
G
R
G
V
IN
A. DUAL SUPPLY B. SINGLE SUPPLY
06925-043
Figure 36. Basic Connections
BASIC CONNECTION
Figure 36 shows the basic connection circuit for the AD8223.
The +VS and −VS terminals are connected to the power supply.
The supply can be either bipolar (VS = ±2 V to ±12 V) or single
supply (−VS = 0 V, +VS = +3 V to +24 V). Power supplies should
be capacitively decoupled close to the power pins of the device.
For best results, use surface-mount 0.1 µF ceramic chip capacitors
and 10 µF electrolytic tantalum capacitors.
The input voltage, which can be either single-ended (tie either
−IN or +IN to ground) or differential, is amplified by the
programmed gain. The output signal appears as the voltage
difference between the output pin and the externally applied
voltage on the REF input.
DIFFERENTIAL OUTPUT
Figure 37 shows how to create a differential output in-amp. An
OP1177 op amp creates the inverted output. Because the op
amp drives the AD8223 reference pin, the AD8223 can still
ensure that the differential voltage is correct. Errors from the
op amp or mismatched resistors are common to both outputs
and are thus common mode. These common-mode errors
should be rejected by the next device in the signal chain.
+IN
–IN
REF
AD8223
V
REF
20kΩ
+–
OP1177
+OUT
–OUT
20kΩ
06925-044
Figure 37. Differential Output Using Op Amp
OUTPUT BUFFERING
The AD8223 is designed to drive loads of 10 k or greater. If
the load is less than this value, buffer the AD8223 output with a
precision single-supply op amp such as the OP113. This op amp
can swing from 0 V to 4 V on its output while driving a load as
small as 600 .
5
V
AD8223
REF OP113
5V
V
OUT
+
–
0.1µF
0.1µF
+
–
IN
R
G
06925-045
Figure 38. Output Buffering
CABLES
Receiving from a Cable
In many applications, shielded cables are used to minimize
noise; for best CMR over frequency, the shield should be
properly driven. Figure 39 shows an active guard drive that
is configured to improve ac common-mode rejection by
bootstrapping the capacitances of input cable shields, thus
minimizing the capacitance mismatch between the inputs.
R
G
2
–INPUT
+INPUT
100Ω
AD8223
AD8031
REFERENCE
V
OUT
R
G
2
+V
S
–V
S
2
7
6
5
4
1
8
3
06925-046
Figure 39. Common-Mode Shield Driver
AD8223
Rev. 0 | Page 18 of 20
Driving a Cable
All cables have a certain capacitance per unit length, which
varies widely with cable type. The capacitive load from the
cable may cause peaking in the output response of the AD8223.
To reduce the peaking, use a resistor between the AD8223 and
the cable. Because cable capacitance and desired output response
vary widely, this resistor is best determined empirically. A good
starting point is 75 Ω.
The AD8232 operates at a low enough frequency that transmission
line effects are rarely an issue; therefore, the resistor need not
match the characteristic impedance of the cable.
AD8223
(DIFF OUT)
AD8223
(SINGLE OUT)
06925-047
Figure 40. Driving a Cable
A SINGLE-SUPPLY DATA ACQUISITION SYSTEM
Interfacing bipolar signals to single-supply analog-to-digital
converters (ADCs) presents a challenge. The bipolar signal
must be mapped into the input range of the ADC. Figure 41
shows how this translation can be achieved.
±10mV
5V
AD8223
REF
5V
AD7776
5
V
+
–
A
IN
REFOUT
REFIN
0.1µF
0.1µF
R
G
1.02kΩ
0
6925-048
Figure 41. A Single-Supply Data Acquisition System
The bridge circuit is excited by a +5 V supply. The full-scale output
voltage from the bridge (±10 mV), therefore, has a common-
mode level of 2.5 V. The AD8223 removes the common-mode
component and amplifies the input signal by a factor of 100
(RG = 1.02 k). This results in an output signal of ±1 V. To
prevent this signal from running into the AD8223 ground rail, the
voltage on the REF pin must be raised to at least 1 V. In this
example, the 2 V reference voltage from the AD7776 ADC is
used to bias the AD8223 output voltage to 2 V ± 1 V, which
corresponds to the input range of the ADC.
AMPLIFYING SIGNALS WITH LOW COMMON-
MODE VOLTAGE
Because the common-mode input range of the AD8223 extends
0.15 V below ground, it is possible to measure small differential
signals that have low, or no, common-mode components. Figure 42
shows a thermocouple application in which one side of the J-type
thermocouple is grounded.
2V
5
V
AD8223
REF
0.1µF
V
OUT
R
G
1.02kΩ
+
–
J-TYPE
THERMOCOUPLE
06925-049
Figure 42. Amplifying Bipolar Signals with Low Common-Mode Voltage
Over a temperature range of −200°C to +200°C, the J-type
thermocouple delivers a voltage ranging from −7.890 mV
to +10.777 mV. A programmed gain on the AD8223 of 100
(RG = 845) and a voltage on the AD8223 REF pin of 2 V results
in the AD8223 output voltage ranging from 1.110 V to 3.077 V
relative to ground.
AD8223
Rev. 0 | Page 19 of 20
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-187-AA
0.80
0.60
0.40
8°
0°
4
8
1
5
PIN 1
0.65 BSC
SEATING
PLANE
0.38
0.22
1.10 MAX
3.20
3.00
2.80
COPLANARITY
0.10
0.23
0.08
3.20
3.00
2.80
5.15
4.90
4.65
0.15
0.00
0.95
0.85
0.75
Figure 43. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-A A
012407-A
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099) 45°
8°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
85
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2441)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
Figure 44. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
AD8223
Rev. 0 | Page 20 of 20
ORDERING GUIDE
Model Temperature Range Package Description Package Option Branding
AD8223AR −40°C to +85°C 8-Lead SOIC_N R-8
AD8223AR-RL −40°C to +85°C 8-Lead SOIC_N,13" Tape and Reel R-8
AD8223AR-R7 −40°C to +85°C 8-Lead SOIC_N, 7" Tape and Reel R-8
AD8223ARM −40°C to +85°C 8-Lead MSOP RM-8 Y0U
AD8223ARM-RL −40°C to +85°C 8-Lead MSOP, 13" Tape and Reel RM-8 Y0U
AD8223ARM-R7 −40°C to +85°C 8-Lead MSOP, 7" Tape and Reel RM-8 Y0U
AD8223ARMZ1 −40°C to +85°C 8-Lead MSOP RM-8 Y0Q
AD8223ARMZ-RL1 −40°C to +85°C 8-Lead MSOP, 13" Tape and Reel RM-8 Y0Q
AD8223ARMZ-R71 −40°C to +85°C 8-Lead MSOP, 7" Tape and Reel RM-8 Y0Q
AD8223ARZ1 −40°C to +85°C 8-Lead SOIC_N R-8
AD8223ARZ-RL1 −40°C to +85°C 8-Lead SOIC_N, 13" Tape and Reel R-8
AD8223ARZ-R71 −40°C to +85°C 8-Lead SOIC_N, 7" Tape and Reel R-8
AD8223BR −40°C to +85°C 8-Lead SOIC_N R-8
AD8223BR-RL −40°C to +85°C 8-Lead SOIC_N, 13" Tape and Reel R-8
AD8223BR-R7 −40°C to +85°C 8-Lead SOIC_N, 7" Tape and Reel R-8
AD8223BRM −40°C to +85°C 8-Lead MSOP RM-8 Y0V
AD8223BRM-RL −40°C to +85°C 8-Lead MSOP, 13" Tape and Reel RM-8 Y0V
AD8223BRM-R7 −40°C to +85°C 8-Lead MSOP, 7" Tape and Reel RM-8 Y0V
AD8223BRMZ1 −40°C to +85°C 8-Lead MSOP RM-8 Y0R
AD8223BRMZ-RL1 −40°C to +85°C 8-Lead MSOP, 13" Tape and Reel RM-8 Y0R
AD8223BRMZ-R71 −40°C to +85°C 8-Lead MSOP, 7" Tape and Reel RM-8 Y0R
AD8223BRZ1 −40°C to +85°C 8-Lead SOIC_N R-8
AD8223BRZ-RL1 −40°C to +85°C 8-Lead SOIC_N, 13" Tape and Reel R-8
AD8223BRZ-R71 −40°C to +85°C 8-Lead SOIC_N, 7" Tape and Reel R-8
1 Z = RoHS Compliant Part.
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06925-0-10/08(0)