Single-Supply, Low Cost Instrumentation Amplifier AD8223 Gain set with 1 resistor Gain = 5 to 1000 Inputs Voltage range to 150 mV below negative rail 25 nA maximum input bias current 30 nV/Hz, RTI noise @ 1 kHz Power supplies Dual supply: 2 V to 12 V Single supply: 3 V to 24 V 500 A maximum supply current APPLICATIONS Low power medical instrumentation Transducer interface Thermocouple amplifiers Industrial process controls Difference amplifiers Low power data acquisition CONNECTION DIAGRAM -RG 1 8 +RG -IN 2 - 7 +VS +IN 3 + 6 OUT -VS 4 5 REF AD8223 06925-001 FEATURES Figure 1. 8-Lead SOIC (R) and 8-Lead MSOP (RM) Packages Table 1. Instrumentation Amplifiers by Category GeneralPurpose AD82201 AD8221 AD8222 AD82241 AD8228 1 Zero Drift AD82311 AD85531 AD85551 AD85561 AD85571 Mil Grade AD620 AD621 AD524 AD526 AD624 Low Power AD6271 AD6231 AD8223 High Voltage PGA AD8250 AD8251 AD8253 Rail-to-rail output. GENERAL DESCRIPTION The AD8223 is an integrated single-supply instrumentation amplifier that delivers rail-to-rail output swing on a single supply (3 V to 24 V). The AD8223 conforms to the 8-lead industry standard pinout configuration. The AD8223 is simple to use: one resistor sets the gain. With no external resistor, the AD8223 is configured for G = 5. With an external resistor, the AD8223 can be programmed for gains up to 1000. The AD8223 has a wide input common-mode range and can amplify signals that have a 150 mV common-mode voltage below ground. Although the design of the AD8223 is optimized to operate from a single supply, the AD8223 still provides excellent performance when operated from a dual voltage supply (2 V to 12 V). Low power consumption (1.5 mW at 3 V), wide supply voltage range, and rail-to-rail output swing make the AD8223 ideal for battery-powered applications. The rail-to-rail output stage maximizes the dynamic range when operating from low supply voltages. The AD8223 replaces discrete instrumentation amplifier designs and offers superior linearity, temperature stability, and reliability in a minimum of space. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2008 Analog Devices, Inc. All rights reserved. AD8223 TABLE OF CONTENTS Features .............................................................................................. 1 Gain Selection ............................................................................. 14 Applications ....................................................................................... 1 Input Voltage Range ................................................................... 14 Connection Diagram ....................................................................... 1 Reference Terminal .................................................................... 15 General Description ......................................................................... 1 Input Protection ......................................................................... 15 Revision History ............................................................................... 2 RF Interference (RFI)................................................................. 15 Specifications..................................................................................... 3 Ground Returns for Input Bias Currents ................................ 16 Single Supply ................................................................................. 3 Applications Information .............................................................. 17 Dual Supply ................................................................................... 5 Basic Connection ....................................................................... 17 Absolute Maximum Ratings............................................................ 7 Differential Output .................................................................... 17 Thermal Resistance ...................................................................... 7 Output Buffering ........................................................................ 17 ESD Caution .................................................................................. 7 Cables ........................................................................................... 17 Pin Configuration and Function Descriptions ............................. 8 A Single-Supply Data Acquisition System .............................. 18 Typical Performance Characteristics ............................................. 9 Amplifying Signals with Low Common-Mode Voltage ........ 18 Theory of Operation ...................................................................... 14 Outline Dimensions ....................................................................... 19 Amplifier Architecture .............................................................. 14 Ordering Guide .......................................................................... 20 REVISION HISTORY 10/08--Revision 0: Initial Version Rev. 0 | Page 2 of 20 AD8223 SPECIFICATIONS SINGLE SUPPLY TA = 25C, -VS = 0 V, +VS = +5 V, and RL = 10 k to 2.5 V, unless otherwise noted. Table 2 Parameter COMMON-MODE REJECTION RATIO DC to 60 Hz with 1 k Source Imbalance G=5 G = 10 G = 100 G = 1000 NOISE Voltage Noise, 1 kHz G=5 G = 1000 RTI, 0.1 Hz to 10 Hz G=5 G = 1000 Current Noise, 1 kHz 0.1 Hz to 10 Hz VOLTAGE OFFSET Input Offset, VOSI Over Temperature Average TC Output Offset, VOSO Over Temperature Average TC Offset Referred to Input vs. Supply (PSR) G=5 G = 10 G = 100 G = 1000 INPUT CURRENT Input Bias Current Over Temperature Average Temperature Coefficient Input Offset Current Over Temperature Average Temperature Coefficient DYNAMIC RESPONSE Small Signal -3 dB Bandwidth G=5 G = 10 G = 100 G = 1000 Slew Rate Conditions Min AD8223A Typ Max Min AD8223B Typ Max Unit VCM = 0 V to 3 V 80 86 90 90 86 90 96 96 dB dB dB dB VIN+ = VIN- = VREF = 0 V 50 30 50 30 nV/Hz nV/Hz 1.0 0.6 70 1.2 1.0 0.6 70 1.2 V p-p V p-p fA/Hz pA p-p Total RTI error = VOSI + VOSO/G 250 400 2 1500 2000 15 TA = -40C to +85C TA = -40C to +85C TA = -40C to +85C TA = -40C to +85C +VS = 4 V to 24 V, -VS = 0 V 80 86 90 90 TA = -40C to +85C TA = -40C to +85C 5 5 86 90 96 96 12 25 28 50 0.25 TA = -40C to +85C TA = -40C to +85C 100 160 1 1000 1500 10 5 5 dB dB dB dB 12 25 28 nA nA pA/C 2 2.5 50 5 5 nA nA pA/C 125 125 50 5 0.2 125 125 50 5 0.2 kHz kHz kHz kHz V/s Rev. 0 | Page 3 of 20 2 2.5 V V V/C V V V/C 0.25 AD8223 Parameter Settling Time to 0.01% G=5 G = 10 G = 100 G = 1000 GAIN Gain Range Gain Error1 G=5 G = 10 G = 100 G = 1000 Nonlinearity G=5 G = 1000 Gain vs. Temperature G=5 G > 51 INPUT Input Impedance Differential Common-Mode Common-Mode Input Voltage Range2 OUTPUT Output Swing REFERENCE INPUT RIN IIN Voltage Range Gain to Output POWER SUPPLY Operating Range Quiescent Current Over Temperature TEMPERATURE RANGE For Specified Performance 1 2 Conditions Step size = 3.5 V Min AD8223A Typ Max Min 18 18 18 85 AD8223B Typ Max 18 18 18 85 Unit s s s s G = 5 + (80 k/RG) 5 1000 5 1000 V/V 0.02 0.2 0.3 0.3 % % % % VOUT = 0.05 V to 4.5 V 0.10 0.10 0.10 0.07 0.3 0.3 0.3 0.10 0.10 0.10 VOUT = 0.05 V to 4.5 V 12 200 12 200 ppm ppm TA = -40C to +85C 10 2 50 50 2||2 2||2 2||2 2||2 ppm/C ppm/C G||pF G||pF V VIN+ = VIN- (-VS) - 0.15 (+VS) - 1.5 (-VS) - 0.15 (+VS) - 1.5 RL = 10 k to ground +0.01 +0.01 +0.01 (+VS) - 0.5 (+VS) - 0.15 V RL = 100 k to ground (+VS) - 0.5 (+VS) - 0.15 20% +20 +VS k A V V +24 500 600 V A A +85 C 60 +10 VIN+ = VIN- = VREF = 0 V -VS 20% +20 +VS +0.01 60 +10 -VS 1 0.0002 +3 350 TA = -40C to +85C -40 1 0.0002 +24 500 600 +3 +85 -40 350 V Does not include effects of external resistor, RG. Total input range depends on common-mode voltage, differential voltage, and gain. See Figure 18 through Figure 21, and the Input Voltage Range section in the Theory of Operation section for more information. Rev. 0 | Page 4 of 20 AD8223 DUAL SUPPLY TA = 25C, -VS = -12 V, +VS = +12 V, and RL = 10 k to ground, unless otherwise noted.1 Table 3. Parameter COMMON-MODE REJECTION RATIO DC to 60 Hz with 1 k Source Imbalance G=5 G = 10 G = 100 G = 1000 NOISE Voltage Noise, 1 kHz G=5 G = 1000 RTI, 0.1 Hz to 10 Hz G=5 G = 1000 Current Noise, 1 kHz 0.1 Hz to 10 Hz VOLTAGE OFFSET Input Offset, VOSI Over Temperature Average TC Output Offset, VOSO Over Temperature Average TC Offset Referred to Input vs. Supply (PSR) G=5 G = 10 G = 100 G = 1000 INPUT CURRENT Input Bias Current Over Temperature Average Temperature Coefficient Input Offset Current Over Temperature Average Temperature Coefficient DYNAMIC RESPONSE Small Signal -3 dB Bandwidth G=5 G = 10 G = 100 G = 1000 Slew Rate Settling Time to 0.01% G=5 G = 10 G = 100 G = 1000 Conditions Min AD8223A Typ Max Min AD8223B Typ Max Unit VCM = -10 V to 10 V 80 86 90 90 86 90 96 96 dB dB dB dB VIN+ = VIN- = VREF = 0 V 50 30 50 30 nV/Hz nV/Hz 1.0 0.6 70 1.2 1.0 0.6 70 1.2 V p-p V p-p fA/Hz pA p-p Total RTI error = VOSI + VOSO/G 250 400 2 1500 2000 15 TA = -40C to +85C TA = -40C to +85C TA = -40C to +85C TA = -40C to +85C +VS = 5 V to 12 V, -VS = -5 V to -12 V 80 86 90 90 TA = -40C to +85C TA = -40C to +85C 5 5 86 90 96 96 12 25 28 50 0.25 TA = -40C to +85C TA = -40C to +85C 100 160 1 1000 1500 10 5 5 dB dB dB dB 12 25 28 nA nA pA/C 2 2.5 50 2 2.5 V V V/C V V V/C 0.25 5 5 nA nA pA/C 200 200 70 7 0.3 200 200 70 7 0.3 kHz kHz kHz kHz V/s 30 30 30 150 30 30 30 150 s s s s Step size = 10 V Rev. 0 | Page 5 of 20 AD8223 Parameter GAIN Gain Range Gain Error2 G=5 G = 10 G = 100 G = 1000 Nonlinearity G=5 G = 1000 Gain vs. Temperature G=5 G > 51 INPUT Input Impedance Differential Common-Mode Common-Mode Input Voltage Range3 OUTPUT Output Swing Conditions G = 5 + (80 k/RG) POWER SUPPLY Operating Range Quiescent Current Over Temperature TEMPERATURE RANGE For Specified Performance AD8223A Typ 5 Max Min 1000 5 AD8223B Typ Max Unit 1000 V/V 0.02 0.2 0.3 0.3 % % % % VOUT = -10 V to +10 V 0.10 0.10 0.10 0.07 0.3 0.3 0.3 0.10 0.10 0.10 VOUT = -10 V to +10 V 5 30 5 30 ppm ppm TA = -40C to +85C 10 2 50 50 2||2 2||2 2||2 2||2 ppm/C ppm/C G||pF G||pF V VIN+ = VIN- (-VS) - 0.15 (+VS) - 1.5 (-VS) - 0.15 (+VS) - 1.5 RL = 10 k to ground (-VS) + 0.3 (-VS) + 0.1 (+VS) - 0.8 (+VS) - 0.3 (-VS) + 0.3 (-VS) + 0.1 (+VS) - 0.8 (+VS) - 0.3 V 20% +20 +VS k A V V RL = 100 k to ground REFERENCE INPUT RIN IIN Voltage Range Gain to Output Min 60 +10 VIN+ = VIN- = VREF = 0 V -VS 20% +20 +VS 60 +10 -VS 1 0.0002 1 0.0002 V 2 12 650 850 2 12 650 850 V A A -40 +85 -40 +85 C TA = -40C to +85C 1 Because maximum supply voltage is 24 V between the negative and positive supply, these specifications at 12V are at the part's limit. Operation at a nominal supply voltage slightly less than 12 V is recommended to allow for power supply tolerances. Does not include effects of external resistor, RG. 3 Total input range depends on common-mode voltage, differential voltage, and gain. See Figure 18 through Figure 21 and the Input Voltage Range section in the Theory of Operation section for more information. 2 Rev. 0 | Page 6 of 20 AD8223 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 4. Parameter Supply Voltage Internal Power Dissipation Differential Input Voltage Output Short-Circuit Duration Storage Temperature Range (R, RM) Operating Temperature Range Lead Temperature (Soldering, 10 sec) ESD (Human Body Model) ESD (Charge Device Model) ESD (Machine Model) JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Rating 12 V 650 mW VS Indefinite -65C to +125C -40C to +85C 300C 1.5 kV 500 V 100 V Specification is for the device in free air. Table 5. Thermal Resistance Package Type 8-Lead SOIC (R) 8-Lead MSOP (RM) ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 7 of 20 JA 155 200 Unit C/W C/W AD8223 -RG 1 8 +RG -IN 2 AD8223 7 3 TOP VIEW (Not to Scale) +VS +IN 6 OUT -VS 4 5 REF 06925-002 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 2. Pin Configuration Table 6. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 Mnemonic -RG -IN +IN -VS REF OUT +VS +RG Descriptions Gain Resistor Terminal. Negative Input. Positive Input. Negative Supply. Reference. Connect to a low impedance source. Output is referenced to this node. Output. Positive Supply. Gain Resistor Terminal. Rev. 0 | Page 8 of 20 AD8223 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25C, VS = 5 V, RL = 10 k, unless otherwise noted. 1000 NUMBER OF UNITS 600 500 400 300 200 06925-061 100 0 -13.8 -13.5 -13.2 -12.9 -12.6 -12.3 100 G=5 G = 1000 BW LIMIT G = 100 BW LIMIT 10 0.1 -12.0 1 10 INPUT BIAS CURRENT (nA) 100 1k 100k 10k FREQUENCY (Hz) Figure 6. Voltage Noise Density vs. Frequency Figure 3. Typical Distribution of Input Bias Current 25 N = 4720 MEAN = -0.00571517 SD = 0.172282 1000 G = 10 06925-050 700 VOLTAGE NOISE DENSITY (nV/ Hz) N = 4720 MEAN = -12.9448 SD = 0.317868 IBIAS (nA) 600 400 15 10 5 06925-062 200 0 -0.9 -0.6 -0.3 0 0.3 0.6 0.9 0 -60 1.2 06925-064 NUMBER OF UNITS 20 800 -40 -20 INPUT OFFSET CURRENT (nA) 600 400 200 0 0.005 80 100 120 140 0.010 100 10 0.01 0.015 GAIN ERROR, G = 5 (%) 06925-065 CURRENT NOISE DENSITY (fA/ Hz) 800 06925-063 NUMBER OF UNITS 1000 -0.005 60 1000 1200 -0.010 40 Figure 7. IBIAS vs. Temperature N = 5036 MEAN = -0.00336179 SD = 0.00155048 0 -0.015 20 TEMPERATURE (C) Figure 4. Typical Distribution of Input Offset Current 1400 0 0.1 1 10 100 FREQUENCY (Hz) Figure 5. Typical Distribution for Gain Error (G = 5) Figure 8. Current Noise Density vs. Frequency Rev. 0 | Page 9 of 20 1k AD8223 18 120 16 110 G = 1000 VS = 5V 14 VS = 2.5V 100 VS = 12V G = 100 8 80 70 60 4 50 2 40 06925-013 6 0 -12 -10 -8 -6 -4 -2 0 2 4 6 30 10 8 G = 10 06925-055 CMRR (dB) 10 1 10 100 1k 10k 100k FREQUENCY (Hz) CMV (V) Figure 12. CMRR vs. Frequency, VS = 12 Figure 9. IBIAS vs. CMV 120 G = 1000 110 100 G=5 CMRR (dB) 90 G = 10 G = 100 80 70 60 50 40 30 06925-056 1s/DIV 06925-066 500fA/DIV 1 10 100 1k 10k 100k FREQUENCY (Hz) Figure 13. CMRR vs. Frequency, +VS = +5 V Figure 10. 0.1 Hz to 10 Hz Current Noise 70 60 G = 1000 G = 1000 50 GAIN (dB) 40 G=5 G = 100 30 20 10 G = 10 G=5 0 0.5V/DIV 1s/DIV 06925-018 -10 -20 06925-054 IBIAS (nA) G=5 90 12 -30 100 1k 10k 100k FREQUENCY (Hz) Figure 14. Gain vs. Frequency, VS = 12 V Figure 11. 0.1 Hz to 10 Hz RTI and RTO Voltage Noise Rev. 0 | Page 10 of 20 1M AD8223 70 4 G = 1000 60 3 G = 100 40 30 G = 10 20 G=5 10 0 VS = 2.5V 0 +VS = +5V -1 -2 -3 -4 06925-067 -10 1 -20 -30 100 1k 10k -5 -6 -6 1M 100k 06925-070 GAIN (dB) VS = 5V 2 COMMON-MODE INPUT (V) 50 -4 FREQUENCY (Hz) -2 0 2 4 6 MAXIMUM OUTPUT VOLTAGE (V) Figure 15. Gain vs. Frequency, +VS = +5 V Figure 18. Common-Mode Input vs. Maximum Output Voltage, G = 5, Small Supplies 25 15 12V 10 COMMON-MODE INPUT (V) 15 5V 10 2.5V 5 5 0 -5 06925-068 -10 0 0.1 1 -15 -15 100 10 06925-071 OUTPUT VOLTAGE (V p-p) 20 -10 FREQUENCY (kHz) 0 5 10 15 Figure 19. Common-Mode Input vs. Maximum Output Voltage, G = 5, VS = 12 V 4 0.38 3 0.36 2 COMMON-MODE INPUT (V) 0.04 0.34 0.32 0.30 0.28 0.26 0.24 VS = 5V 1 VS = 2.5V 0 +VS = +5V -1 -2 -3 0.22 2 4 6 8 10 12 06925-072 -4 06925-069 SLEW RATE (V/s) Figure 16. Large Signal Frequency Response 0.20 -5 MAXIMUM OUTPUT VOLTAGE (V) -5 -6 -6 14 SUPPLY VOLTAGE (VS) -4 -2 0 2 4 6 MAXIMUM OUTPUT VOLTAGE (V) Figure 17. Slew Rate vs. Supply Voltage Figure 20. Common-Mode Input vs. Maximum Output Voltage, G = 100, Small Supplies Rev. 0 | Page 11 of 20 AD8223 15 120 10 100 5 80 0 G = 100 60 G = 10 40 -10 20 -15 -15 06925-073 -5 -10 -5 0 5 10 0 15 G=5 06925-025 PSRR (dB) COMMON-MODE INPUT (V) G = 1000 1 10 100 1k 10k 100k FREQUENCY (Hz) MAXIMUM OUTPUT VOLTAGE (V) Figure 21. Common-Mode Input vs. Maximum Output Voltage, G = 100, VS = 12 V Figure 24. Negative PSRR vs. Frequency, VS = 12 V 140 120 5V/DIV G = 1000 100 PSRR (dB) G = 100 80 G = 10 60 G=5 0 06925-023 20 1 10 100 1k 10k 100s/DIV 06925-051 0.1%/DIV 40 100k FREQUENCY (Hz) Figure 22. Positive PSRR vs. Frequency, VS = 12 V Figure 25. Large Signal Response, G = 5 140 120 5V/DIV G = 1000 100 G = 10 G=5 0.1%/DIV 40 20 0 1 10 100 1k 10k 100s/DIV 06925-052 60 06925-024 PSRR (dB) G = 100 80 100k FREQUENCY (Hz) Figure 26. Large Signal Pulse Response, G = 100, CL = 100 pF Figure 23. Positive PSRR vs. Frequency, +VS = +5 V Rev. 0 | Page 12 of 20 AD8223 5V/DIV 0.1%/DIV Figure 27. Large Signal Pulse Response, G = 1000, CL = 100 pF 20mV/DIV 100s/DIV 06925-034 100s/DIV 06925-053 2 Figure 29. Small Signal Pulse Response, G = 1000, RL = 25 k, CL = 100 pF G=5 G = 10 G = 100 SOURCING -1 -2 +2 SINKING +1 06925-074 OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES +VS 2 20mV/DIV 10s/DIV 06925-028 -VS 0.01 0.1 1 OUTPUT CURRENT (mA) Figure 30. Output Voltage Swing vs. Output Current Figure 28. Small Signal Pulse Response, G = 5, 10, 100; RL = 10 k Rev. 0 | Page 13 of 20 10 AD8223 THEORY OF OPERATION AMPLIFIER ARCHITECTURE GAIN SELECTION The AD8223 is an instrumentation amplifier based on a classic 3-op amp approach, modified to ensure operation even at common-mode voltages at the negative supply rail. The architecture allows lower voltage offsets, better CMRR, and higher gain accuracy than competing instrumentation amplifiers in its class. Placing a resistor across the RG terminals sets the gain of the AD8223, which can be calculated by referring to Table 7 or by using the following gain equation: RG POSITIVE SUPPLY 7 1% Standard Table Value of RG () 26.7 k 15.8 k 5.36 k 2.26 k 1.78 k 845 412 162 80.6 - 4 1 8k 10k 50k - GAIN + 8k 8 10k 50k 7 OUT 6 REF 5 - NONINVERTING 3 4 NEGATIVE SUPPLY 06925-038 + Figure 31. Simplified Schematic Figure 31 shows a simplified schematic of the AD8223. The AD8223 has three stages. In the first stage, the input signal is applied to PNP transistors. These PNP transistors act as voltage buffers and allow input voltages below ground. The second stage consists of a pair of 8 k resistors, the RG resistor, and a pair of amplifiers. This stage allows the amplification of the AD8223 to be set with a single external resistor. The third stage is a differential amplifier composed of an op amp, two 10 k resistors, and two 50 k resistors. This stage removes the common-mode signal and applies an additional gain of 5. The transfer function of the AD8223 is VOUT = G(VIN+ - VIN-) + VREF where: G5 80 k RG G5 Table 7. Gains Achieved Using 1% Resistors + INVERTING 2 80 k Desired Gain 8 10 20 40 50 100 200 500 1000 Calculated Gain 7.99 10.1 19.9 40.4 49.9 99.7 199 499 998 The AD8223 defaults to G = 5 when no gain resistor is used. Add the tolerance and gain drift of the RG resistor to the specifications of the AD8223 to determine the total gain accuracy of the system. When the gain resistor is not used, gain depends only on internal resistor matching, so gain error and gain drift are minimal. INPUT VOLTAGE RANGE The 3-op amp architecture of the AD8223 applies gain and then removes the common-mode voltage. Therefore, internal nodes in the AD8223 experience a combination of both the gained signal and the common-mode signal. This combined signal can be limited by the voltage supplies even when the individual input and output signals are not. To determine whether the signal can be limited, refer to Figure 18 through Figure 21. Alternatively, use the parameters in the Specifications section to verify that the input and output are not limited and then use the following formula to make sure the internal nodes are not limited. To check if it is limited by the internal nodes, VS 0.01 V 0.6 VCM VDIFF Gain 10 VS 0.1 V If more common-mode range is required, a solution is to apply less gain in the instrumentation amplifier and more in a later stage. Rev. 0 | Page 14 of 20 AD8223 REFERENCE TERMINAL RF INTERFERENCE (RFI) The output voltage of the AD8223 is developed with respect to the potential on the reference terminal. This is useful when the output signal needs to be offset to a precise midsupply level. For example, a voltage source can be tied to the REF pin to levelshift the output so that the AD8223 can drive a single-supply ADC. The REF pin is protected with ESD diodes and should not exceed either +VS or -VS by more than 0.3 V. RF rectification is often a problem when amplifiers are used in applications where there are strong RF signals. The disturbance can appear as a small dc offset voltage. High frequency signals can be filtered with a low-pass, R-C network placed at the input of the instrumentation amplifier, as shown in Figure 34. The filter limits the input signal bandwidth according to the following relationship: For best performance, keep the source impedance to the REF terminal below 5 . As shown in Figure 31, the reference terminal, REF, is at one end of a 50 k resistor. Additional impedance at the REF terminal adds to this resistor and results in poorer CMRR performance. INCORRECT FilterFreqDiff 1 2 R(2CD CC ) FilterFreqCM 1 2 RCC where CD 10CC. CORRECT +15V AD8223 VREF R + CD R1 47nF 499 OP2177 -IN 4.02k VOUT AD8223 R 06925-039 REF - CC 1nF Figure 32. Driving the Reference Pin 10F 0.1F INPUT PROTECTION Internal supply referenced clamping diodes allow the input, reference, output, and gain terminals of the AD8223 to safely withstand overvoltages of 0.3 V above or below the supplies. This is true for all gains, and for power-on and power-off. This last case is particularly important because the signal source and amplifier can be powered separately. If the overvoltage is expected to exceed this value, limit the current through these diodes to about 10 mA using external current limiting resistors. This is shown in Figure 33. The size of this resistor is defined by the supply voltage and the required overvoltage protection. +VS 1 = 10mA MAX + RG AD8223 OUT RLIM RLIM = -VS Figure 34. RFI Suppression Figure 34 shows an example in which the differential filter frequency is approximately 400 Hz, and the common-mode filter frequency is approximately 40 kHz. The typical dc offset shift over frequency is less than 1.5 V, and the RF signal rejection of the circuit is better than 71 dB. The resistors were selected to be large enough to isolate the circuit input from the capacitors but not large enough to significantly increase the circuit noise. Choose values of R and CC to minimize RFI. Mismatch between the R x CC at positive input and the R x CC at negative input degrades the CMRR of the AD8223. Because of their higher accuracy and stability, COG/NPO type ceramic capacitors are recommended for the CC capacitors. The dielectric for the CD capacitor is not as critical. VOVER - VS + 0.7V 10mA 06925-040 - -15V + 06925-041 - VOVER +IN 4.02k + VOVER + CC 1nF VREF RLIM 10F 0.1F AD8223 Figure 33. Input Protection Rev. 0 | Page 15 of 20 AD8223 INCORRECT GROUND RETURNS FOR INPUT BIAS CURRENTS CORRECT +VS Input bias currents are those dc currents that must flow to bias the input transistors of an amplifier. These are usually transistor base currents. When amplifying floating input sources such as transformers or ac-coupled sources, there must be a direct dc path into each input so that the bias current can flow. Figure 35 shows how a bias current path can be provided for the cases of transformer coupling, capacitive ac-coupling, and a thermocouple application. +VS AD8223 AD8223 REF REF -VS -VS TRANSFORMER In dc-coupled resistive bridge applications, providing this path is generally not necessary because the bias current simply flows from the bridge supply through the bridge and into the amplifier. However, if the impedances that the two inputs see are large and differ by a large amount (>10 k), the offset current of the input stage causes dc errors proportional to the input offset voltage of the amplifier. TRANSFORMER +VS +VS AD8223 AD8223 REF REF 10M -VS -VS THERMOCOUPLE THERMOCOUPLE +VS +VS C C 1 fHIGH-PASS = 2RC AD8223 C REF R AD8223 C REF -VS -VS CAPACITIVELY COUPLED CAPACITIVELY COUPLED Figure 35. Creating an IBIAS Path Rev. 0 | Page 16 of 20 06925-042 R AD8223 APPLICATIONS INFORMATION +VS +VS +2V TO +12V 0.1F + 10F 0.1F + RG + 10F + RG OUTPUT RG - VIN VOUT RG RG OUTPUT RG - REF REF (INPUT) 0.1F -VS VOUT REF REF (INPUT) 10F + -2V TO -12V A. DUAL SUPPLY 06925-043 VIN +3V TO +24V B. SINGLE SUPPLY Figure 36. Basic Connections BASIC CONNECTION OUTPUT BUFFERING Figure 36 shows the basic connection circuit for the AD8223. The +VS and -VS terminals are connected to the power supply. The supply can be either bipolar (VS = 2 V to 12 V) or single supply (-VS = 0 V, +VS = +3 V to +24 V). Power supplies should be capacitively decoupled close to the power pins of the device. For best results, use surface-mount 0.1 F ceramic chip capacitors and 10 F electrolytic tantalum capacitors. The AD8223 is designed to drive loads of 10 k or greater. If the load is less than this value, buffer the AD8223 output with a precision single-supply op amp such as the OP113. This op amp can swing from 0 V to 4 V on its output while driving a load as small as 600 . 5V 0.1F The input voltage, which can be either single-ended (tie either -IN or +IN to ground) or differential, is amplified by the programmed gain. The output signal appears as the voltage difference between the output pin and the externally applied voltage on the REF input. 5V 0.1F + RG AD8223 - DIFFERENTIAL OUTPUT + Figure 38. Output Buffering +IN AD8223 CABLES Receiving from a Cable In many applications, shielded cables are used to minimize noise; for best CMR over frequency, the shield should be properly driven. Figure 39 shows an active guard drive that is configured to improve ac common-mode rejection by bootstrapping the capacitances of input cable shields, thus minimizing the capacitance mismatch between the inputs. +OUT +VS -INPUT -IN 20k 20k VREF 100 AD8031 - + OP1177 +INPUT RG 2 RG 2 7 1 AD8223 8 3 6 4 Figure 39. Common-Mode Shield Driver Figure 37. Differential Output Using Op Amp Rev. 0 | Page 17 of 20 VOUT 5 -VS 06925-044 -OUT 2 REFERENCE 06925-046 Figure 37 shows how to create a differential output in-amp. An OP1177 op amp creates the inverted output. Because the op amp drives the AD8223 reference pin, the AD8223 can still ensure that the differential voltage is correct. Errors from the op amp or mismatched resistors are common to both outputs and are thus common mode. These common-mode errors should be rejected by the next device in the signal chain. REF VOUT OP113 - REF 06925-045 VIN AD8223 Driving a Cable All cables have a certain capacitance per unit length, which varies widely with cable type. The capacitive load from the cable may cause peaking in the output response of the AD8223. To reduce the peaking, use a resistor between the AD8223 and the cable. Because cable capacitance and desired output response vary widely, this resistor is best determined empirically. A good starting point is 75 . The AD8232 operates at a low enough frequency that transmission line effects are rarely an issue; therefore, the resistor need not match the characteristic impedance of the cable. The bridge circuit is excited by a +5 V supply. The full-scale output voltage from the bridge (10 mV), therefore, has a commonmode level of 2.5 V. The AD8223 removes the common-mode component and amplifies the input signal by a factor of 100 (RG = 1.02 k). This results in an output signal of 1 V. To prevent this signal from running into the AD8223 ground rail, the voltage on the REF pin must be raised to at least 1 V. In this example, the 2 V reference voltage from the AD7776 ADC is used to bias the AD8223 output voltage to 2 V 1 V, which corresponds to the input range of the ADC. AMPLIFYING SIGNALS WITH LOW COMMONMODE VOLTAGE Because the common-mode input range of the AD8223 extends 0.15 V below ground, it is possible to measure small differential signals that have low, or no, common-mode components. Figure 42 shows a thermocouple application in which one side of the J-type thermocouple is grounded. AD8223 (DIFF OUT) 5V 0.1F AD8223 (SINGLE OUT) + 06925-047 J-TYPE THERMOCOUPLE 06925-049 5V 5V 0.1F 0.1F AD7776 + AD8223 AIN REF REFOUT REFIN 06925-048 - 2V Over a temperature range of -200C to +200C, the J-type thermocouple delivers a voltage ranging from -7.890 mV to +10.777 mV. A programmed gain on the AD8223 of 100 (RG = 845) and a voltage on the AD8223 REF pin of 2 V results in the AD8223 output voltage ranging from 1.110 V to 3.077 V relative to ground. Interfacing bipolar signals to single-supply analog-to-digital converters (ADCs) presents a challenge. The bipolar signal must be mapped into the input range of the ADC. Figure 41 shows how this translation can be achieved. 10mV VOUT REF Figure 42. Amplifying Bipolar Signals with Low Common-Mode Voltage A SINGLE-SUPPLY DATA ACQUISITION SYSTEM RG 1.02k AD8223 - Figure 40. Driving a Cable 5V RG 1.02k Figure 41. A Single-Supply Data Acquisition System Rev. 0 | Page 18 of 20 AD8223 OUTLINE DIMENSIONS 3.20 3.00 2.80 8 3.20 3.00 2.80 5.15 4.90 4.65 5 1 4 PIN 1 0.65 BSC 0.95 0.85 0.75 1.10 MAX 0.15 0.00 0.38 0.22 COPLANARITY 0.10 0.80 0.60 0.40 8 0 0.23 0.08 SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 43. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters 5.00 (0.1968) 4.80 (0.1890) 8 1 5 4 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY 0.10 SEATING PLANE 6.20 (0.2441) 5.80 (0.2284) 1.75 (0.0688) 1.35 (0.0532) 0.51 (0.0201) 0.31 (0.0122) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-012-A A CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 44. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) Rev. 0 | Page 19 of 20 012407-A 4.00 (0.1574) 3.80 (0.1497) AD8223 ORDERING GUIDE Model AD8223AR AD8223AR-RL AD8223AR-R7 AD8223ARM AD8223ARM-RL AD8223ARM-R7 AD8223ARMZ1 AD8223ARMZ-RL1 AD8223ARMZ-R71 AD8223ARZ1 AD8223ARZ-RL1 AD8223ARZ-R71 AD8223BR AD8223BR-RL AD8223BR-R7 AD8223BRM AD8223BRM-RL AD8223BRM-R7 AD8223BRMZ1 AD8223BRMZ-RL1 AD8223BRMZ-R71 AD8223BRZ1 AD8223BRZ-RL1 AD8223BRZ-R71 1 Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C Package Description 8-Lead SOIC_N 8-Lead SOIC_N,13" Tape and Reel 8-Lead SOIC_N, 7" Tape and Reel 8-Lead MSOP 8-Lead MSOP, 13" Tape and Reel 8-Lead MSOP, 7" Tape and Reel 8-Lead MSOP 8-Lead MSOP, 13" Tape and Reel 8-Lead MSOP, 7" Tape and Reel 8-Lead SOIC_N 8-Lead SOIC_N, 13" Tape and Reel 8-Lead SOIC_N, 7" Tape and Reel 8-Lead SOIC_N 8-Lead SOIC_N, 13" Tape and Reel 8-Lead SOIC_N, 7" Tape and Reel 8-Lead MSOP 8-Lead MSOP, 13" Tape and Reel 8-Lead MSOP, 7" Tape and Reel 8-Lead MSOP 8-Lead MSOP, 13" Tape and Reel 8-Lead MSOP, 7" Tape and Reel 8-Lead SOIC_N 8-Lead SOIC_N, 13" Tape and Reel 8-Lead SOIC_N, 7" Tape and Reel Z = RoHS Compliant Part. (c)2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06925-0-10/08(0) Rev. 0 | Page 20 of 20 Package Option R-8 R-8 R-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 R-8 R-8 R-8 R-8 R-8 R-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 R-8 R-8 R-8 Branding Y0U Y0U Y0U Y0Q Y0Q Y0Q Y0V Y0V Y0V Y0R Y0R Y0R