KIT ATION EVALU E L B A AVAIL 19-3514; Rev 2; 1/07 14-Bit, 200Msps, High-Dynamic-Performance, Dual DAC with CMOS Inputs 200Msps Output Update Rate Noise Spectral Density = -160dBFS/Hz at fOUT = 16MHz Excellent SFDR and IMD Performance SFDR = 78dBc at fOUT = 16MHz (to Nyquist) SFDR = 74dBc at fOUT = 80MHz (to Nyquist) IMD = -86dBc at fOUT = 10MHz IMD = -74dBc at fOUT = 80MHz ACLR = 75dB at fOUT = 61MHz 2mA to 20mA Full-Scale Output Current CMOS-Compatible Digital and Clock Inputs On-Chip 1.2V Bandgap Reference Low 260mW Power Dissipation 68-Lead QFN-EP Package Evaluation Kit Available (MAX5874EVKIT) Ordering Information PART MAX5874EGK-D MAX5874EGK+D PKG CODE -40C to +85C 68 QFN-EP* -40C to +85C 68 QFN-EP* G6800-4 G6800-4 *EP = Exposed pad. + = Lead-free package. D = Dry pack. Pin Configuration Base Stations: Single/Multicarrier UMTS, CDMA, GSM 63 62 61 60 59 58 B5 B6 B4 B3 B2 B1 B0 N.C. DVDD1.8 67 66 65 64 A13 68 A12 A11 A10 A8 Direct Digital Synthesis (DDS) A9 TOP VIEW A7 Communications: Fixed Broadband Wireless Access, Point-to-Point Microwave PINPACKAGE TEMP RANGE N.C. Applications Features 57 56 55 54 53 52 Cable Modem Termination System (CMTS) A6 1 51 B7 A5 2 50 B8 Automated Test Equipment (ATE) A4 3 49 B9 A3 4 48 B10 Instrumentation A2 5 47 B11 A1 6 46 B12 A0 7 45 B13 N.C. 8 44 SELIQ N.C. 9 43 GND GND 10 42 XOR DVDD3.3 11 41 DORI GND 12 40 PD GND 13 39 TORB AVDD3.3 14 38 CLKP GND 15 37 CLKN REFIO 16 36 GND FSADJ 17 35 AVCLK 12 250 LVDS MAX5877 14 250 LVDS MAX5878 16 250 LVDS 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 AVDD1.8 MAX5876 GND CMOS AVDD3.3 200 AVDD3.3 16 GND MAX5875 OUTIP CMOS OUTIN 200 GND 14 GND MAX5874 OUTQP CMOS OUTQN 200 GND 12 AVDD3.3 MAX5873 MAX5874 AVDD3.3 LOGIC INPUTS GND UPDATE RATE (Msps) AVDD1.8 PART RESOLUTION (Bits) DACREF Selector Guide QFN ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. 1 MAX5874 General Description The MAX5874 is an advanced 14-bit, 200Msps, dual digital-to-analog converter (DAC). This DAC meets the demanding performance requirements of signal synthesis applications found in wireless base stations and other communications applications. Operating from 3.3V and 1.8V supplies, this dual DAC offers exceptional dynamic performance such as 78dBc spurious-free dynamic range (SFDR) at fOUT = 16MHz and supports update rates of 200Msps, with a power dissipation of only 260mW. The MAX5874 utilizes a current-steering architecture that supports a 2mA to 20mA full-scale output current range, and allows a 0.1V P-P to 1V P-P differential output voltage swing. The device features an integrated 1.2V bandgap reference and control amplifier to ensure high-accuracy and low-noise performance. A separate reference input (REFIO) allows for the use of an external reference source for optimum flexibility and improved gain accuracy. The digital and clock inputs of the MAX5874 accept 3.3V CMOS voltage levels. The device features a flexible input data bus that allows for dual-port input or a single-interleaved data port. The MAX5874 is available in a 68-pin QFN package with an exposed paddle (EP) and is specified for the extended temperature range (-40C to +85C). Refer to the MAX5873 and MAX5875 data sheets for pin-compatible 12-bit and 16-bit versions of the MAX5874, respectively. Refer to the MAX5877 for an LVDS-compatible version of the MAX5874. MAX5874 14-Bit, 200Msps, High-Dynamic-Performance, Dual DAC with CMOS Inputs ABSOLUTE MAXIMUM RATINGS TORB, DORI, PD to GND, DACREF ....-0.3V to (DVDD3.3 + 0.3V) Continuous Power Dissipation (TA = +70C) 68-Pin QFN-EP (derate 41.7mW/C above +70C) (Note 1) ............3333.3mW Thermal Resistance JA (Note 1)...................................+24C/W Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-60C to +150C Lead Temperature (soldering, 10s) .................................+300C AVDD1.8, DVDD1.8 to GND, DACREF ................. -0.3V to +2.16V AVDD3.3, DVDD3.3, AVCLK to GND, DACREF ....... -0.3V to +3.9V DACREF, REFIO, FSADJ to GND, DACREF.......................................... -0.3V to (AVDD3.3 + 0.3V) OUTIP, OUTIN, OUTQP, OUTQN to GND, DACREF ....................-1V to (AVDD3.3 + 0.3V) CLKP, CLKN to GND, DACREF..............-0.3V to (AVCLK + 0.3V) A13/B13-A0/B0, XOR, SELIQ to GND, DACREF...............................................-0.3V to (DVDD3.3 + 0.3V) Note 1: Thermal resistors based on a multilayer board with 4 x 4 via array in exposed paddle area. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (AVDD3.3 = DVDD3.3 = AVCLK = 3.3V, AVDD1.8 = DVDD1.8 = 1.8V, GND = 0, external reference VREFIO = 1.25V, output load 50 doubleterminated, transformer-coupled output, IOUTFS = 20mA, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE Resolution Integral Nonlinearity INL Measured differentially Differential Nonlinearity DNL Measured differentially Offset Error OS GEFS Gain-Drift Tempco Full-Scale Output Current IOUTFS Output Compliance Bits 1 LSB 0.7 -0.025 0.001 LSB +0.025 %FS 10 ppm/C External reference 1 %FS Internal reference 100 External reference 50 Offset-Drift Tempco Full-Scale Gain Error 14 (Note 3) Single-ended ppm/C 2 20 -0.5 +1.1 mA V Output Resistance ROUT 1 M Output Capacitance COUT 5 pF DYNAMIC PERFORMANCE Clock Frequency Output Update Rate Noise Spectral Density 2 fCLK fDAC 1 200 fDAC = fCLK / 2, single-port mode 1 100 fDAC = fCLK, dual-port mode 1 200 fDAC = 150MHz fOUT = 16MHz, -12dBFS -160 fDAC = 200MHz fOUT = 80MHz, -12dBFS -158 _______________________________________________________________________________________ MHz Msps dBFS/Hz 14-Bit, 200Msps, High-Dynamic-Performance, Dual DAC with CMOS Inputs (AVDD3.3 = DVDD3.3 = AVCLK = 3.3V, AVDD1.8 = DVDD1.8 = 1.8V, GND = 0, external reference VREFIO = 1.25V, output load 50 doubleterminated, transformer-coupled output, IOUTFS = 20mA, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 2) PARAMETER SYMBOL CONDITIONS fDAC = 100MHz Spurious-Free Dynamic Range to Nyquist SFDR fDAC = 200MHz Spurious-Free Dynamic Range, 25MHz Bandwidth Two-Tone IMD SFDR MIN TYP fOUT = 1MHz, 0dBFS 88 fOUT = 1MHz, -6dBFS 82 fOUT = 1MHz, -12dBFS 82 fOUT = 10MHz, -12dBFS 80 fOUT = 30MHz, -12dBFS 79 fOUT = 10MHz, -12dBFS 80 fOUT = 16MHz, -12dBFS, TA +25oC 71 fOUT = 16MHz, -12dBFS 68 UNITS dBc 78 78 fOUT = 50MHz, -12dBFS 77 fOUT = 80MHz, -12dBFS 74 fDAC = 150MHz fOUT = 16MHz, -12dBFS 84 fDAC = 100MHz fOUT1 = 9MHz, -7dBFS; fOUT2 = 10MHz, -7dBFS -86 fDAC = 200MHz fOUT1 = 79MHz, -7dBFS; fOUT2 = 80MHz, -7dBFS -74 TTIMD MAX dBc dBc Four-Tone IMD, 1MHz Frequency Spacing, GSM Model FTIMD fDAC = 150MHz fOUT = 16MHz, -12dBFS -82 dBc Adjacent Channel Leakage Power Ratio 3.84MHz Bandwidth, W-CDMA Model ACLR fDAC = 184.32MHz fOUT = 61.44MHz 75 dB 240 MHz Output Bandwidth BW-1dB (Note 4) INTER-DAC CHARACTERISTICS Gain Gain Matching Gain-Matching Tempco Phase-Matching Tempco fOUT = DC fOUT = 60MHz Phase/C Channel-to-Channel Crosstalk dB +0.01 Gain/C Phase Phase Matching 0.2 fOUT = DC - 80MHz 20 ppm/C 0.25 Degrees Degrees/ C dB 0.002 fCLK = 200MHz, fOUT = 50MHz, 0dBFS -70 REFERENCE Internal Reference Voltage Range VREFIO 1.14 1.2 1.26 V Reference Input Compliance Range VREFIOCR 0.125 1.250 V Reference Input Resistance RREFIO 10 k Reference Voltage Drift TCOREF 25 ppm/C _______________________________________________________________________________________ 3 MAX5874 ELECTRICAL CHARACTERISTICS (continued) MAX5874 14-Bit, 200Msps, High-Dynamic-Performance, Dual DAC with CMOS Inputs ELECTRICAL CHARACTERISTICS (continued) (AVDD3.3 = DVDD3.3 = AVCLK = 3.3V, AVDD1.8 = DVDD1.8 = 1.8V, GND = 0, external reference VREFIO = 1.25V, output load 50 doubleterminated, transformer-coupled output, IOUTFS = 20mA, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ANALOG OUTPUT TIMING (See Figure 4) Output Fall Time tFALL 90% to 10% (Note 5) 0.7 ns Output Rise Time tRISE 10% to 90% (Note 5) 0.7 ns Output-Voltage Settling Time Output Propagation Delay tSETTLE tPD Glitch Impulse Output Noise nOUT Output settles to 0.025% FS (Note 5) 14 ns Excluding data latency (Note 5) 1.1 ns Measured differentially 1 pV*s IOUTFS = 2mA 30 IOUTFS = 20mA 30 pA/Hz TIMING CHARACTERISTICS Data to Clock Setup Time tSETUP Referenced to rising edge of clock (Note 6) -0.6 -1.2 Data to Clock Hold Time tHOLD Referenced to rising edge of clock (Note 6) 2.1 1.5 ns Latency to I output 9 Latency to Q output 8 Clock cycles Single-Port (Interleaved Mode) Data Latency Dual-Port (Parallel Mode) Data Latency ns 5.5 Clock cycles Minimum Clock Pulse-Width High tCH CLKP, CLKN 2.4 ns Minimum Clock Pulse-Width Low tCL CLKP, CLKN 2.4 ns CMOS LOGIC INPUTS (A13/B13-A0/B0, XOR, SELIQ, PD, TORB, DORI) Input Logic High VIH Input Logic Low VIL Input Leakage Current IIN PD, TORB, DORI Internal Pulldown Resistance Input Capacitance 0.7 x DVDD3.3 V 1 VPD = VTORB = VDORI = 3.3V CIN 0.3 x DVDD3.3 V 20 A 1.5 M 2.5 pF CLOCK INPUTS (CLKP, CLKN) Differential Input Voltage Swing Differential Input Slew Rate SRCLK External Common-Mode Voltage Range VCOM Sine wave > 1.5 Square wave > 0.5 (Note 7) > 100 V/s AVCLK / 2 0.3 V VP-P Input Resistance RCLK 5 k Input Capacitance CCLK 2.5 pF POWER SUPPLIES Analog Supply Voltage Range Digital Supply Voltage Range Clock Supply Voltage Range 4 AVDD3.3 3.135 3.3 3.465 AVDD1.8 1.710 1.8 1.890 DVDD3.3 3.135 3.3 3.465 DVDD1.8 1.710 1.8 1.890 AVCLK 3.135 3.3 3.465 _______________________________________________________________________________________ V V V 14-Bit, 200Msps, High-Dynamic-Performance, Dual DAC with CMOS Inputs (AVDD3.3 = DVDD3.3 = AVCLK = 3.3V, AVDD1.8 = DVDD1.8 = 1.8V, GND = 0, external reference VREFIO = 1.25V, output load 50 doubleterminated, transformer-coupled output, IOUTFS = 20mA, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 2) PARAMETER Analog Supply Current SYMBOL CONDITIONS IAVDD3.3 + IAVCLK fDAC = 200Msps, fOUT = 1MHz IAVDD1.8 IDVDD3.3 Digital Supply Current IDVDD1.8 Power Dissipation PDISS Power-Supply Rejection Ratio PSRR MIN Power-down TYP MAX 53 58 UNITS mA 0.001 fDAC = 200Msps, fOUT = 1MHz 24 Power-down 32 mA 0.001 fDAC = 200Msps, fOUT = 1MHz 1.5 Power-down 3 mA 0.001 fDAC = 200Msps, fOUT = 1MHz 21 Power-down 25 mA 0.001 fDAC = 200Msps, fOUT = 1MHz 260 Power-down 14 AVDD3.3 = AVCLK = DVDD3.3 = +3.3V 5% (Notes 7, 8) -0.1 300 mW W +0.1 %FS/V Note 2: Specifications at TA +25C are guaranteed by production testing. Specifications at TA < +25C are guaranteed by design and characterization data. Note 3: Nominal full-scale current IOUTFS = 32 x IREF. Note 4: This parameter does not include update-rate-dependent effects of sin(x)/x filtering inherent in the MAX5874. Note 5: Parameter measured single-ended into a 50 termination resistor. Note 6: Not production tested. Guaranteed by design and characterization data. Note 7: A differential clock input slew rate of > 100V/s is required to achieve the specified dynamic performance. Note 8: Parameter defined as the change in midscale output caused by a 5% variation in the nominal supply voltage. Typical Operating Characteristics (AVDD3.3 = DVDD3.3 = AVCLK = 3.3V, AVDD1.8 = DVDD1.8 = 1.8V, external reference, VREFIO = 1.25V, RL = 50 double-terminated, IOUTFS = 20mA, TA = +25C, unless otherwise noted.) SINGLE-TONE SFDR vs. OUTPUT FREQUENCY (fCLK = 100Msps) 80 80 -12dBFS 60 40 20 20 15 fOUT (MHz) 20 25 -6dBFS 60 40 20 0 0 10 80 SFDR (dBc) 40 5 0dBFS -12dBFS -6dBFS SFDR (dBc) SFDR (dBc) 0dBFS -6dBFS 60 0 100 MAX5874 toc02 0dBFS -12dBFS 100 MAX5874 toc01 100 SINGLE-TONE SFDR vs. OUTPUT FREQUENCY (fCLK = 150Msps) MAX5874 toc03 SINGLE-TONE SFDR vs. OUTPUT FREQUENCY (fCLK = 50Msps) 0 0 10 20 30 fOUT (MHz) 40 50 0 15 30 45 60 75 fOUT (MHz) _______________________________________________________________________________________ 5 MAX5874 ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (continued) (AVDD3.3 = DVDD3.3 = AVCLK = 3.3V, AVDD1.8 = DVDD1.8 = 1.8V, external reference, VREFIO = 1.25V, RL = 50 double-terminated, IOUTFS = 20mA, TA = +25C, unless otherwise noted.) 60 40 20 -60 -70 -12dBFS -80 BW = 12MHz fOUT1 = 29.8706MHz fOUT2 = 30.9937MHz fOUT1 -20 OUTPUT POWER (dBFS) -50 TWO-TONE IMD (dBc) -12dBFS -6dBFS 0 MAX5874 toc05 0dBFS 80 SFDR (dBc) -40 MAX5874 toc04 100 TWO-TONE IMD (fCLK = 100Msps) TWO-TONE IMD vs. OUTPUT FREQUENCY (1MHz CARRIER SPACING, fCLK = 100Msps) MAX5874 toc06 SINGLE-TONE SFDR vs. OUTPUT FREQUENCY (fCLK = 200Msps) fOUT2 -40 -60 2 x fOUT1 - fOUT2 2 x fOUT2 - fOUT1 -80 -90 -6dBFS 0 -100 0 20 40 60 100 80 10 15 20 25 30 40 35 24 28 30 32 SFDR vs. FULL-SCALE OUTPUT CURRENT (fCLK = 200MHz) SFDR vs. TEMPERATURE (fCLK = 200MHz) 20mA 80 95 MAX5874 toc08 MAX5874 toc07 AOUT = -6dBFS AOUT = -6dBFS TA = +85C 90 TA = -40C 85 -12dBFS 10mA 60 SFDR (dBc) -70 SFDR (dBc) -60 5mA 40 -80 MAX5874 toc09 TWO-TONE IMD vs. OUTPUT FREQUENCY (1MHz CARRIER SPACING, fCLK = 200Msps) 100 36 34 fOUT (MHz) 80 75 TA = +25C 70 20 -90 65 -6dBFS 60 0 -100 20 30 40 50 60 70 0 80 20 40 60 80 20 40 60 80 fOUT (MHz) fOUT (MHz) INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE POWER DISSIPATION vs. CLOCK FREQUENCY (fOUT = 10MHz) MAX5874 toc10 1.00 0.75 0.75 0.50 0.50 DNL (LSB) 0.25 0 -0.25 0.25 0 -0.50 -1.00 8192 12,288 DIGITAL INPUT CODE 16,384 260 240 220 180 -0.50 4096 AOUT = 0dBFS 200 -0.25 -0.75 280 100 MAX5874 toc12 fOUT (MHz) 1.00 0 0 100 POWER DISSIPATION (mW) 10 MAX5874 toc11 0 6 26 fOUT (MHz) -50 TWO-TONE IMD (dBc) -100 5 fOUT (MHz) -40 INL (LSB) MAX5874 14-Bit, 200Msps, High-Dynamic-Performance, Dual DAC with CMOS Inputs 0 4096 8192 12,288 DIGITAL INPUT CODE 16,384 30 50 70 90 110 130 150 170 190 fCLK (MHz) _______________________________________________________________________________________ 14-Bit, 200Msps, High-Dynamic-Performance, Dual DAC with CMOS Inputs FOUR-TONE POWER RATIO PLOT (fCLK = 150MHz, fCENTER = 31.6040MHz ) 220 210 INTERNAL REFERENCE fOUT1 -20 -30 fOUT4 -40 -60 -80 200 -40 MAX5874 toc15 -20 OUTPUT POWER (dBFS) EXTERNAL REFERENCE fOUT1 = 29.9997MHz fOUT2 fOUT3 f OUT2 = 31.0251MHz fOUT3 = 31.0640MHz fOUT4 = 32.9829MHz BW = 12MHz ANALOG OUTPUT POWER (dBm) 0 MAX5874 toc13 230 AOUT = 0dBFS fCLK = 184.32MHz fCENTER = 30.72MHz ACLR = 76dB -50 -60 -70 -80 -90 -100 -110 -100 3.235 3.335 -120 26 3.435 28 30 32 34 36 38 3.05MHz/div fOUT (MHz) SUPPLY VOLTAGE (V) ACLR FOR WCDMA MODULATION, SINGLE CARRIER -30 -40 fCENTER = 61.44MHz fCLK = 184.32MHz ACLR = 75dB WCDMA BASEBAND ACLR 85 MAX5874 toc16 -20 -60 81 ACLR (dB) 82 -80 ALTERNATE 83 -50 -70 ADJACENT 84.5 84 MAX5874 toc17 190 3.135 ANALOG OUTPUT POWER (dBm) POWER DISSIPATION (mW) 240 ACLR FOR WCDMA MODULATION, TWO CARRIERS MAX5874 toc14 POWER DISSIPATION vs. SUPPLY VOLTAGE (fCLK = 100MHz, fOUT = 10MHz) 81.4 80 79 -90 78 -100 77 -110 76 79.5 79.4 78.6 79.7 79.0 78.6 75 -120 DC 92.16MHz 9.2MHz/div 1 2 3 4 NUMBER OF CARRIERS _______________________________________________________________________________________ 7 MAX5874 Typical Operating Characteristics (continued) (AVDD3.3 = DVDD3.3 = AVCLK = 3.3V, AVDD1.8 = DVDD1.8 = 1.8V, external reference, VREFIO = 1.25V, RL = 50 double-terminated, IOUTFS = 20mA, TA = +25C, unless otherwise noted.) MAX5874 14-Bit, 200Msps, High-Dynamic-Performance, Dual DAC with CMOS Inputs Pin Description PIN 1-7 NAME FUNCTION A6, A5, A4, Data Bits A6-A0. In dual-port mode, data is directed to the Q-DAC. In single-port mode, data bits A3, A2, A1, A0 are not used. Connect bits A6-A0 to GND in single-port mode. 8, 9, 59, 60 N.C. No Connection. Leave floating or connect to GND. 10, 12, 13, 15, 20, 23, 26, 27, 30, 33, 36, 43 GND Converter Ground 11 DVDD3.3 Digital Supply Voltage. Accepts a 3.135V to 3.465V supply voltage range. Bypass with a 0.1F capacitor to GND. 14, 21, 22, 31, 32 AVDD3.3 Analog Supply Voltage. Accepts a 3.135V to 3.465V supply voltage range. Bypass each pin with a 0.1F capacitor to GND. 16 REFIO Reference I/O. Output of the internal 1.2V precision bandgap reference. Bypass with a 1F capacitor to GND. REFIO can be driven with an external reference source. See Table1. 17 FSADJ Full-Scale Adjust Input. This input sets the full-scale output current of the DAC. For a 20mA fullscale output current, connect a 2k resistor between FSADJ and DACREF. See Table1. 18 DACREF Current-Set Resistor Return Path. For a 20mA full-scale output current, connect a 2k resistor between FSADJ and DACREF. Internally connected to GND. Do not use as an external ground connection. 19, 34 AVDD1.8 Analog Supply Voltage. Accepts a 1.71V to 1.89V supply voltage range. Bypass each pin with a 0.1F capacitor to GND. 24 OUTQN Complementary Q-DAC Output. Negative terminal for current output. 25 OUTQP Q-DAC Output. Positive terminal for current output. 28 OUTIN Complementary I-DAC Output. Negative terminal for current output. 29 OUTIP I-DAC Output. Positive terminal for current output. 35 AVCLK Clock Supply Voltage. Accepts a 3.135V to 3.465V supply voltage range. Bypass with a 0.1F capacitor to GND. 37 CLKN Complementary Converter Clock Input. Negative input terminal for differential converter clock. Internally biased to AVCLK / 2. 38 CLKP Converter Clock Input. Positive input terminal for differential converter clock. Internally biased to AVCLK / 2. 39 TORB Two's-Complement/Binary Select Input. Set TORB to a CMOS-logic-high level to indicate a two'scomplement input format. Set TORB to a CMOS-logic-low level to indicate a binary input format. TORB has an internal pulldown resistor. 40 PD Power-Down Input. Set PD to a CMOS-logic-high level to force the DAC into power-down mode. Set PD to a CMOS-logic-low level for normal operation. PD has an internal pulldown resistor. 41 DORI Dual (Parallel)/Single (Interleaved) Port Select Input. Set DORI high to configure as a dual-port DAC. Set DORI low to configure as a single-port interleaved DAC. DORI has an internal pulldown resistor. 8 _______________________________________________________________________________________ 14-Bit, 200Msps, High-Dynamic-Performance, Dual DAC with CMOS Inputs PIN NAME FUNCTION 42 XOR DAC Exclusive-OR Select Input. Set XOR low to allow the data stream to pass unchanged to the DAC input. Set XOR high to invert the input data into the DAC. If unused, connect XOR to GND. 44 SELIQ DAC Select Input. Set SELIQ low to direct data into the Q-DAC inputs. Set SELIQ high to direct data into the I-DAC inputs. If unused, connect SELIQ to GND. SELIQ's logic state is only valid in single-port (interleaved) mode. 45-58 61 62-68 -- B13, B12, B11, B10, B9, B8, Data Bits B13-B0. In dual-port mode, data is directed to the I-DAC. In single-port mode, the state B7, B6, B5, B4, of SELIQ determines where the data bits are directed. B3, B2, B1, B0 DVDD1.8 Digital Supply Voltage. Accepts a 1.71V to 1.89V supply voltage range. Bypass with a 0.1F capacitor to GND. A13, A12, A11, Data Bits A13-A7. In dual-port mode, data is directed to the Q-DAC. In single-port mode, data A10, A9, A8, A7 bits are not used. Connect bits A13-A7 to GND in single-port mode. EP Exposed Pad. Must be connected to GND through a low-impedance path. Detailed Description Architecture The MAX5874 high-performance, 14-bit, dual currentsteering DAC (Figure 1) operates with DAC update rates up to 200Msps. The converter consists of input registers and a demultiplexer for single-port (interleaved) mode, followed by a current-steering array. During operation in interleaved mode, the input data registers demultiplex the single-port data bus. The current-steering array generates differential full-scale currents in the 2mA to 20mA range. An internal current-switching network, in combination with external 50 termination resistors, converts the differential output currents into dual differential output voltages with a 0.1V to 1V peak-to-peak output voltage range. An integrated 1.2V bandgap reference, control amplifier, and user-selectable external resistor determine the data converter's full-scale output range. Reference Architecture and Operation The MAX5874 supports operation with the internal 1.2V bandgap reference or an external reference voltage source. REFIO serves as the input for an external, lowimpedance reference source. REFIO also serves as a reference output when the DAC operates in internal reference mode. For stable operation with the internal reference, decouple REFIO to GND with a 1F capacitor. Due to its limited output-drive capability, buffer REFIO with an external amplifier when driving large external loads. The MAX5874's reference circuit (Figure 2) employs a control amplifier to regulate the full-scale current IOUTFS for the differential current outputs of the DAC. Calculate the full-scale output current as follows: IOUTFS = 32 x VREFIO 1 x 1 - 14 RSET 2 where I OUTFS is the full-scale output current of the DAC. R SET (located between FSADJ and DACREF) determines the amplifier's full-scale output current for the DAC. See Table 1 for a matrix of different IOUTFS and RSET selections. Table 1. IOUTFS and RSET Selection Matrix Based on a Typical 1.200V Reference Voltage RSET () FULL-SCALE CURRENT IOUTFS (mA) CALCULATED 1% EIA STD 2 19.2k 19.1k 5 7.68k 7.5k 10 3.84k 3.83k 15 2.56k 2.55k 20 1.92k 1.91k _______________________________________________________________________________________ 9 MAX5874 Pin Description (continued) MAX5874 14-Bit, 200Msps, High-Dynamic-Performance, Dual DAC with CMOS Inputs DVDD3.3 GND DVDD1.8 AVDD1.8 AVDD3.3 OUTIP TORB LATCH DORI XOR/ DECODE LATCH LATCH DAC OUTIN SELIQ CMOS RECEIVER DATA13- DATA0 LATCH XOR OUTQP LATCH XOR/ DECODE LATCH LATCH DAC OUTQN AVCLK CLKP CLKN DACREF CLK INTERFACE 1.2V REFERENCE GND REFIO FSADJ MAX5874 POWER-DOWN BLOCK PD GND Figure 1. MAX5874 High-Performance, 14-Bit, Dual Current-Steering DAC Analog Outputs (OUTIP, OUTIN, OUTQP, OUTQN) Each MAX5874 DAC outputs two complementary currents (OUTIP/N, OUTQP/N) that operate in a singleended or differential configuration. A load resistor converts these two output currents into complementary single-ended output voltages. A transformer or a differential amplifier configuration converts the differential voltage existing between OUTIP (OUTQP) and OUTIN (OUTQN) to a single-ended voltage. If not using a transformer, the recommended termination from the output is a 25 termination resistor to ground and a 50 resistor between the outputs. To generate a single-ended output, select OUTIP (or OUTQP) as the output and connect OUTIN (or OUTQN) to GND. SFDR degrades with single-ended operation. Figure 3 displays a simplified diagram of the internal output structure of the MAX5874. Clock Inputs (CLKP, CLKN) The MAX5874 features flexible differential clock inputs (CLKP, CLKN) operating from a separate supply 10 (AV CLK) to achieve the optimum jitter performance. Drive the differential clock inputs from a single-ended or a differential clock source. For single-ended operation, drive CLKP with a logic source and bypass CLKN to GND with a 0.1F capacitor. CLKP and CLKN are internally biased to AVCLK / 2. This facilitates the AC-coupling of clock sources directly to the device without external resistors to define the DC level. The dynamic input resistance from CLKP and CLKN to ground is > 5k. Data Timing Relationship Figure 4 displays the timing relationship between digital CMOS data, clock, and output signals. The MAX5874 features a 1.5ns hold, a -1.2ns setup, and a 1.1ns propagation delay time. A nine (eight)-clock-cycle latency exists between CLKP/CLKN and OUTIP/OUTIN (OUTQP/OUTQN) when operating in single-port (interleaved) mode. In dual-port (parallel) mode, the clock latency is 5.5 clock cycles for both channels. Table 2 shows the DAC output codes. ______________________________________________________________________________________ 14-Bit, 200Msps, High-Dynamic-Performance, Dual DAC with CMOS Inputs MAX5874 1.2V REFERENCE AVDD CURRENT SOURCES 10k CURRENT SWITCHES REFIO 1F OUTIP FSADJ CURRENT-SOURCE ARRAY DAC IREF RSET IOUT OUTIN IOUT DACREF IREF = VREFIO / RSET OUTIN OUTIP Figure 2. Reference Architecture, Internal Reference Configuration Figure 3. Simplified Analog Output Structure Table 2. DAC Output Code Table bit applied to XOR through exclusive-OR gates. Pulling XOR high inverts the input data. Pulling XOR low leaves the input data noninverted. By applying a previously encoded pseudo-random bit stream to the data input and applying decoding to XOR, the digital input data can be decorrelated from the DAC output, allowing for the troubleshooting of possible spurious or harmonic distortion degradation due to digital feedthrough on the printed circuit board (PCB). A13/B13-A0/B0, XOR, and SELIQ are latched on the rising edge of the clock. In single-port mode (DORI pulled low) a logic-high signal on SELIQ directs the B13-B0 data onto the I-DAC inputs. A logic-low signal at SELIQ directs data to the Q-DAC inputs. In dual-port (parallel) mode (DORI pulled high), data on pins A13-A0 are directed onto the Q-DAC inputs and B13-B0 are directed onto the I-DAC inputs. DIGITAL INPUT CODE OFFSET BINARY TWO'S COMPLEMENT 00 0000 0000 0000 10 0000 0000 0000 OUT_P OUT_N 0 IOUTFS 01 1111 1111 1111 00 0000 0000 0000 IOUTFS / 2 IOUTFS / 2 11 1111 1111 1111 01 1111 1111 1111 IOUTFS 0 CMOS-Compatible Digital Inputs Input Data Format Select (TORB, DORI) The TORB input selects between two's-complement or binary digital input data. Set TORB to a CMOS-logichigh level to indicate a two's-complement input format. Set TORB to a CMOS-logic-low level to indicate a binary input format. The DORI input selects between a dual-port (parallel) or single-port (interleaved) DAC. Set DORI high to configure the MAX5874 as a dual-port DAC. Set DORI low to configure the MAX5874 as a single-port DAC. In dual-port mode, connect SELIQ to ground. CMOS DAC Inputs (A13/B13-A0/B0, XOR, SELIQ) The MAX5874 latches input data on the rising edge of the clock in a user-selectable two's-complement or binary format. A logic-high voltage on TORB selects two's-complement and a logic-low selects offset binary format. The MAX5874 includes a single-ended, CMOS-compatible XOR input. Input data (all bits) are compared with the Power-Down Operation (PD) The MAX5874 also features an active-high powerdown mode that reduces the DAC's digital current consumption from 22mA to less than 2A and the analog current consumption from 77mA to less than 2A. Set PD high to power down the MAX5874. Set PD low for normal operation. When powered down, the power consumption of the MAX5874 is reduced to less than 14W. The MAX5874 requires 10ms to wake up from power-down and enter a fully operational state. The PD integrated pulldown resistor activates the MAX5874 if PD is left floating. ______________________________________________________________________________________ 11 MAX5874 14-Bit, 200Msps, High-Dynamic-Performance, Dual DAC with CMOS Inputs DATA13-DATA0, XOR N-1 N N+1 N+2 tH tS CLK tPD DAC OUTPUT N-2 N-4 N-5 N-6 N-3 (a) DUAL-PORT (PARALLEL) TIMING DIAGRAM CLK I0 DATAIN Q0 I1 Q1 I2 Q2 I3 Q3 SELIQ tS tH I-4 I-5 I OUT Q OUT I-3 I-2 I-6 Q-6 Q-5 Q-4 Q-3 tPD Q-2 (b) SINGLE-PORT (INTERLEAVED) TIMING DIAGRAM Figure 4. Timing Relationships Between Clock and Input Data for (a) Dual-Port (Parallel) Mode and (b) Single-Port (Interleaved) Mode Applications Information CLK Interface The MAX5874 features a flexible differential clock input (CLKP, CLKN) with a separate supply (AV CLK ) to achieve optimum jitter performance. Use an ultra-low jitter clock to achieve the required noise density. Clock jitter must be less than 0.5psRMS for meeting the specified noise density. For that reason, the CLKP/CLKN input source must be designed carefully. The differential clock (CLKN and CLKP) input can be driven from a single-ended or a differential clock source. Differential 12 clock drive is required to achieve the best dynamic performance from the DAC. For single-ended operation, drive CLKP with a low-noise source and bypass CLKN to GND with a 0.1F capacitor. Figure 5 shows a convenient and quick way to apply a differential signal created from a single-ended source (e.g., HP/AGILENT 8644B signal generator) and a wideband transformer. Alternatively, these inputs can be driven from a CMOS-compatible clock source; however, it is recommended to use sinewave or AC-coupled differential ECL/PECL drive for best dynamic performance. ______________________________________________________________________________________ 14-Bit, 200Msps, High-Dynamic-Performance, Dual DAC with CMOS Inputs 0.1F CLKP 25 SINGLE-ENDED CLOCK SOURCE The distortion performance of the DAC depends on the load impedance. The MAX5874 is optimized for 50 differential double termination. It can be used with a transformer output as shown in Figure 6 or just one 25 resistor from each output to ground and one 50 resistor between the outputs (Figure 7). This produces a fullscale output power of up to -2dBm, depending on the output current setting. Higher termination impedance can be used at the cost of degraded distortion performance and increased output noise voltage. TO DAC 1:1 25 0.1F CLKN GND Grounding, Bypassing, and PowerSupply Considerations Figure 5. Differential Clock-Signal Generation Differential-to-Single-Ended Conversion Using a Wideband RF Transformer Use a pair of transformers (Figure 6) or a differential amplifier configuration to convert the differential voltage existing between OUTIP/OUTQP and OUTIN/OUTQN to a single-ended voltage. Optimize the dynamic performance by using a differential transformer-coupled output to limit the output power to < 0dBm full scale. Pay close attention to the transformer core saturation characteristics when selecting a transformer for the MAX5874. Transformer core saturation can introduce strong 2ndorder harmonic distortion, especially at low output frequencies and high signal amplitudes. For best results, center tap the transformer to ground. When not using a transformer, terminate each DAC output to ground with a 25 resistor. Additionally, place a 50 resistor between the outputs (Figure 7). Grounding and power-supply decoupling can strongly influence the MAX5874 performance. Unwanted digital crosstalk couples through the input, reference, power supply, and ground connections, and affects dynamic performance. High-speed, high-frequency applications require closely followed proper grounding and powersupply decoupling. These techniques reduce EMI and internal crosstalk that can significantly affect the MAX5874 dynamic performance. Use a multilayer PCB with separate ground and powersupply planes. Run high-speed signals on lines directly above the ground plane. Keep digital signals as far away from sensitive analog inputs and outputs, reference input sense lines, and clock inputs as practical. Use a controlled-impedance symmetric design of clock input and the analog output lines to minimize 2nd-order harmonic distortion components, thus 50 T2, 1:1 OUTIP/OUTQP DATA13-DATA0 100 MAX5874 14 VOUT, SINGLE-ENDED T1, 1:1 OUTIN/OUTQN 50 GND WIDEBAND RF TRANSFORMER T2 PERFORMS THE DIFFERENTIAL-TO-SINGLE-ENDED CONVERSION Figure 6. Differential-to-Single-Ended Conversion Using a Wideband RF Transformer ______________________________________________________________________________________ 13 MAX5874 WIDEBAND RF TRANSFORMER PERFORMS SINGLE-ENDED-TODIFFERENTIAL CONVERSION For a single-ended unipolar output, select OUTIP (OUTQP) as the output and ground OUTIN (OUTQN) to GND. Driving the MAX5874 single-ended is not recommended since additional noise and distortion will be added. MAX5874 14-Bit, 200Msps, High-Dynamic-Performance, Dual DAC with CMOS Inputs 25 OUTIP/OUTQP DATA13-DATA0 50 MAX5874 14 OUTP OUTN OUTIN/OUTQN 25 GND Figure 7. Differential Output Configuration optimizing the DAC's dynamic performance. Keep digital signal paths short and run lengths matched to avoid propagation delay and data skew mismatches. The MAX5874 requires five separate power-supply inputs for analog (AV DD1.8 and AV DD3.3 ), digital (DVDD1.8 and DVDD3.3), and clock (AVCLK) circuitry. Decouple each AVDD, DVDD, and AVCLK input pin with a separate 0.1F capacitor as close to the device as possible with the shortest possible connection to the ground plane (Figure 8). Minimize the analog and digital load capacitances for optimized operation. Decouple all three power-supply voltages at the point they enter the PCB with tantalum or electrolytic capacitors. Ferrite beads with additional decoupling capacitors forming a pi-network could also improve performance. The analog and digital power-supply inputs AVDD3.3, AVCLK, and DVDD3.3 allow a 3.135V to 3.465V supply voltage range. The analog and digital power-supply inputs AVDD1.8 and DVDD1.8 allow a 1.71V to 1.89V supply voltage range. The MAX5874 is packaged in a 68-pin QFN-EP package, providing greater design flexibility and optimized DAC AC performance. The EP enables the use of necessary grounding techniques to ensure highest performance operation. Thermal efficiency is not the key factor, since the MAX5874 features low-power operation. The exposed pad ensures a solid ground connection between the DAC and the PCB's ground layer. 14 The data converter die attaches to an EP lead frame with the back of this frame exposed at the package bottom surface, facing the PCB side of the package. This allows for a solid attachment of the package to the PCB with standard infrared (IR) reflow soldering techniques. A specially created land pattern on the PCB, matching the size of the EP (6mm x 6mm), ensures the proper attachment and grounding of the DAC. Refer to the MAX5874 EV kit data sheet. Designing vias into the land area and implementing large ground planes in the PCB design allow for the highest performance operation of the DAC. Use an array of at least 4 x 4 vias ( 0.3mm diameter per via hole and 1.2mm pitch between via holes) for this 68-pin QFN-EP package. Connect the MAX5874 exposed paddle to GND. Vias connect the land pattern to internal or external copper planes. Use as many vias as possible to the ground plane to minimize inductance. BYPASSING--DAC LEVEL AVDD1.8 AVDD3.3 0.1F AVCLK 0.1F 0.1F OUTIP/OUTQP DATA13-DATA0 MAX5874 14 OUTIN/OUTQN 0.1F DVDD1.8 0.1F DVDD3.3 *BYPASS EACH POWER-SUPPLY PIN INDIVIDUALLY. Figure 8. Recommended Power-Supply Decoupling and Bypassing Circuitry ______________________________________________________________________________________ 14-Bit, 200Msps, High-Dynamic-Performance, Dual DAC with CMOS Inputs Integral Nonlinearity (INL) Integral nonlinearity is the deviation of the values on an actual transfer function from either a best straight-line fit (closest approximation to the actual transfer curve) or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. For a DAC, the deviations are measured at every individual step. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between an actual step height and the ideal value of 1 LSB. A DNL error specification of less than 1 LSB guarantees a monotonic transfer function. Offset Error The offset error is the difference between the ideal and the actual offset current. For a DAC, the offset point is the average value at the output for the two midscale digital input codes with respect to the full scale of the DAC. This error affects all codes by the same amount. Gain Error A gain error is the difference between the ideal and the actual full-scale output voltage on the transfer curve, after nullifying the offset error. This error alters the slope of the transfer function and corresponds to the same percentage error in each step. Dynamic Performance Parameter Definitions Signal-to-Noise Ratio (SNR) For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the fullscale analog output (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum can be derived from the DAC's resolution (N bits): SNR = 6.02 x N + 1.76 However, noise sources such as thermal noise, reference noise, clock jitter, etc., affect the ideal reading; therefore, SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first four harmonics, and the DC offset. Noise Spectral Density The DAC output noise floor is the sum of the quantization noise and the output amplifier noise (thermal and shot noise). Noise spectral density is the noise power in 1Hz bandwidth, specified in dBFS/Hz. Spurious-Free Dynamic Range (SFDR) SFDR is the ratio of RMS amplitude of the carrier frequency (maximum signal components) to the RMS value of their next-largest distortion component. SFDR is usually measured in dBc and with respect to the carrier frequency amplitude or in dBFS with respect to the DAC's full-scale range. Depending on its test condition, SFDR is observed within a predefined window or to Nyquist. Two-Tone Intermodulation Distortion (IMD) The two-tone IMD is the ratio expressed in dBc (or dBFS) of the worst 3rd-order (or higher) IMD product(s) to either output tone. Adjacent Channel Leakage Power Ratio (ACLR) Commonly used in combination with wideband codedivision multiple-access (W-CDMA), ACLR reflects the leakage power ratio in dB between the measured power within a channel relative to its adjacent channel. ACLR provides a quantifiable method of determining out-of-band spectral energy and its influence on an adjacent channel when a bandwidth-limited RF signal passes through a nonlinear device. Settling Time The settling time is the amount of time required from the start of a transition until the DAC output settles its new output value to within the converter's specified accuracy. Glitch Impulse A glitch is generated when a DAC switches between two codes. The largest glitch is usually generated around the midscale transition, when the input pattern transitions from 011...111 to 100...000. The glitch impulse is found by integrating the voltage of the glitch at the midscale transition over time. The glitch impulse is usually specified in pV*s. ______________________________________________________________________________________ 15 MAX5874 Static Performance Parameter Definitions Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 68L QFN.EPS MAX5874 14-Bit, 200Msps, High-Dynamic-Performance, Dual DAC with CMOS Inputs PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM 1 C 21-0122 2 PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM 1 C 21-0122 2 Revision History Pages changed at Rev 2: 1-16 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.