General Description
The MAX5874 is an advanced 14-bit, 200Msps, dual
digital-to-analog converter (DAC). This DAC meets the
demanding performance requirements of signal synthesis
applications found in wireless base stations and other
communications applications. Operating from 3.3V and
1.8V supplies, this dual DAC offers exceptional dynamic
performance such as 78dBc spurious-free dynamic range
(SFDR) at fOUT = 16MHz and supports update rates of
200Msps, with a power dissipation of only 260mW.
The MAX5874 utilizes a current-steering architecture
that supports a 2mA to 20mA full-scale output current
range, and allows a 0.1VP-P to 1VP-P differential
output voltage swing. The device features an integrated
1.2V bandgap reference and control amplifier to ensure
high-accuracy and low-noise performance. A separate
reference input (REFIO) allows for the use of an exter-
nal reference source for optimum flexibility and
improved gain accuracy.
The digital and clock inputs of the MAX5874 accept
3.3V CMOS voltage levels. The device features a flexi-
ble input data bus that allows for dual-port input or a
single-interleaved data port. The MAX5874 is available
in a 68-pin QFN package with an exposed paddle (EP)
and is specified for the extended temperature range
(-40°C to +85°C).
Refer to the MAX5873 and MAX5875 data sheets for
pin-compatible 12-bit and 16-bit versions of the
MAX5874, respectively. Refer to the MAX5877 for an
LVDS-compatible version of the MAX5874.
Applications
Base Stations: Single/Multicarrier UMTS, CDMA, GSM
Communications: Fixed Broadband Wireless Access,
Point-to-Point Microwave
Direct Digital Synthesis (DDS)
Cable Modem Termination System (CMTS)
Automated Test Equipment (ATE)
Instrumentation
Features
♦200Msps Output Update Rate
♦Noise Spectral Density = -160dBFS/Hz at
fOUT = 16MHz
♦Excellent SFDR and IMD Performance
SFDR = 78dBc at fOUT = 16MHz (to Nyquist)
SFDR = 74dBc at fOUT = 80MHz (to Nyquist)
IMD = -86dBc at fOUT = 10MHz
IMD = -74dBc at fOUT = 80MHz
♦ACLR = 75dB at fOUT = 61MHz
♦2mA to 20mA Full-Scale Output Current
♦CMOS-Compatible Digital and Clock Inputs
♦On-Chip 1.2V Bandgap Reference
♦Low 260mW Power Dissipation
♦68-Lead QFN-EP Package
♦Evaluation Kit Available (MAX5874EVKIT)
MAX5874
14-Bit, 200Msps, High-Dynamic-Performance,
Dual DAC with CMOS Inputs
________________________________________________________________ Maxim Integrated Products 1
5859606162 5455565763
38
39
40
41
42
43
44
45
46
47
DVDD3.3
AVDD1.8
A12
QFN
TOP VIEW
A13
DVDD1.8
N.C.
N.C.
B0
B1
B2
B3
B4
5253
B5
B6
DACREF
AVDD3.3
GND
GND
AVDD3.3
OUTQP
OUTQN
GND
GND
OUTIP
OUTIN
AVDD3.3
GND
AVDD3.3
B11
B12
B13
SELIQ
GND
XOR
DORI
PD
TORB
CLKP
35
36
37 CLKN
GND
AVCLK
GND
N.C.
N.C.
A0
A1
REFIO
GND
AVDD3.3
GND
GND
A2
A3
A4
A5
48 B10
A6
64
A11
656667
A8
A9
A10
68
A7
2322212019 2726252418 2928 323130
GND
AVDD1.8
3433
49
50 B8
B9
51 B7
11
10
9
8
7
6
5
4
3
2
16
15
14
13
12
1
FSADJ 17
MAX5874
Pin Configuration
Ordering Information
19-3514; Rev 2; 1/07
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
*EP = Exposed pad.
+ = Lead-free package. D = Dry pack.
EVALUATION KIT
AVAILABLE
PART TEMP RANGE PIN-
PACKAGE
PKG
CODE
MAX5874EGK-D -40°C to +85°C 68 QFN-EP* G6800-4
MAX5874EGK+D -40°C to +85°C 68 QFN-EP* G6800-4
Selector Guide
PART RESOLUTION
(Bits)
UPDATE
RATE (Msps)
LOGIC
INPUTS
MAX5873 12 200 CMOS
MAX5874 14 200 CMOS
MAX5875 16 200 CMOS
MAX5876 12 250 LVDS
MAX5877 14 250 LVDS
MAX5878 16 250 LVDS
MAX5874
14-Bit, 200Msps, High-Dynamic-Performance,
Dual DAC with CMOS Inputs
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVDD1.8, DVDD1.8 to GND, DACREF ................. -0.3V to +2.16V
AVDD3.3, DVDD3.3, AVCLK to GND, DACREF....... -0.3V to +3.9V
DACREF, REFIO, FSADJ to GND,
DACREF.......................................... -0.3V to (AVDD3.3 + 0.3V)
OUTIP, OUTIN, OUTQP,
OUTQN to GND, DACREF ....................-1V to (AVDD3.3 + 0.3V)
CLKP, CLKN to GND, DACREF..............-0.3V to (AVCLK + 0.3V)
A13/B13–A0/B0, XOR, SELIQ to GND,
DACREF...............................................-0.3V to (DVDD3.3 + 0.3V)
TORB, DORI, PD to GND, DACREF ....-0.3V to (DVDD3.3 + 0.3V)
Continuous Power Dissipation (TA = +70°C)
68-Pin QFN-EP
(derate 41.7mW/°C above +70°C) (Note 1)............3333.3mW
Thermal Resistance θJA (Note 1)...................................+24°C/W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
STATIC PERFORMANCE
Resolution 14 Bits
Integral Nonlinearity INL Measured differentially ±1 LSB
Differential Nonlinearity DNL Measured differentially ±0.7 LSB
Offset Error OS -0.025 ±0.001 +0.025 %FS
Offset-Drift Tempco ±10 ppm/°C
Full-Scale Gain Error GEFS External reference ±1%FS
Internal reference ±100
Gain-Drift Tempco External reference ±50 ppm/°C
Full-Scale Output Current IOUTFS (Note 3) 2 20 mA
Output Compliance Single-ended -0.5 +1.1 V
Output Resistance ROUT 1MΩ
Output Capacitance COUT 5pF
DYNAMIC PERFORMANCE
Clock Frequency fCLK 1 200 MHz
fDAC = fCLK / 2, single-port mode 1 100
Output Update Rate fDAC fDAC = fCLK, dual-port mode 1 200 Msps
fDAC = 150MHz fOUT = 16MHz, -12dBFS -160
Noise Spectral Density fDAC = 200MHz fOUT = 80MHz, -12dBFS -158 dBFS/Hz
ELECTRICAL CHARACTERISTICS
(AVDD3.3 = DVDD3.3 = AVCLK = 3.3V, AVDD1.8 = DVDD1.8 = 1.8V, GND = 0, external reference VREFIO = 1.25V, output load 50Ωdouble-
terminated, transformer-coupled output, IOUTFS = 20mA, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
(Note 2)
Note 1: Thermal resistors based on a multilayer board with 4 x 4 via array in exposed paddle area.
MAX5874
14-Bit, 200Msps, High-Dynamic-Performance,
Dual DAC with CMOS Inputs
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(AVDD3.3 = DVDD3.3 = AVCLK = 3.3V, AVDD1.8 = DVDD1.8 = 1.8V, GND = 0, external reference VREFIO = 1.25V, output load 50Ωdouble-
terminated, transformer-coupled output, IOUTFS = 20mA, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
(Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
fOUT = 1MHz, 0dBFS 88
fOUT = 1MHz, -6dBFS 82
fOUT = 1MHz, -12dBFS 82
fOUT = 10MHz, -12dBFS 80
fDAC = 100MHz
fOUT = 30MHz, -12dBFS 79
fOUT = 10MHz, -12dBFS 80
fOUT = 16MHz, -12dBFS,
TA ≥ +25oC71 78
fOUT = 16MHz, -12dBFS 68 78
fOUT = 50MHz, -12dBFS 77
Spurious-Free Dynamic Range to
Nyquist SFDR
fDAC = 200MHz
fOUT = 80MHz, -12dBFS 74
dBc
Spurious-Free Dynamic Range,
25MHz Bandwidth SFDR fDAC = 150MHz fOUT = 16MHz, -12dBFS 84 dBc
fDAC = 100MHz fOUT1 = 9MHz, -7dBFS;
fOUT2 = 10MHz, -7dBFS -86
Two-Tone IMD TTIMD
fDAC = 200MHz fOUT1 = 79MHz, -7dBFS;
fOUT2 = 80MHz, -7dBFS -74
dBc
Four-Tone IMD, 1MHz
Frequency Spacing, GSM Model FTIMD fDAC = 150MHz fOUT = 16MHz, -12dBFS -82 dBc
Adjacent Channel Leakage Power
Ratio 3.84MHz Bandwidth,
W-CDMA Model
ACLR fDAC =
184.32MHz fOUT = 61.44MHz 75 dB
Output Bandwidth BW-1dB (Note 4) 240 MHz
INTER-DAC CHARACTERISTICS
fOUT = DC - 80MHz ±0.2
Gain Matching ∆Gain fOUT = DC +0.01 dB
Gain-Matching Tempco ∆Gain/°C±20 ppm/°C
Phase Matching ∆Phase fOUT = 60MHz ±0.25 D egr ees
Phase-Matching Tempco ∆Phase/°C±0.002 D eg r ees/
°C
Channel-to-Channel Crosstalk fCLK = 200MHz, fOUT = 50MHz, 0dBFS -70 dB
REFERENCE
Internal Reference Voltage Range VREFIO 1.14 1.2 1.26 V
Reference Input Compliance
Range VREFIOCR 0.125 1.250 V
Reference Input Resistance RREFIO 10 kΩ
Reference Voltage Drift TCOREF ±25 ppm/°C
MAX5874
14-Bit, 200Msps, High-Dynamic-Performance,
Dual DAC with CMOS Inputs
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(AVDD3.3 = DVDD3.3 = AVCLK = 3.3V, AVDD1.8 = DVDD1.8 = 1.8V, GND = 0, external reference VREFIO = 1.25V, output load 50Ωdouble-
terminated, transformer-coupled output, IOUTFS = 20mA, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
(Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
ANALOG OUTPUT TIMING (See Figure 4)
Output Fall Time tFALL 90% to 10% (Note 5) 0.7 ns
Output Rise Time tRISE 10% to 90% (Note 5) 0.7 ns
Output-Voltage Settling Time tSETTLE Output settles to 0.025% FS (Note 5) 14 ns
Output Propagation Delay tPD Excluding data latency (Note 5) 1.1 ns
Glitch Impulse Measured differentially 1 pV•s
IOUTFS = 2mA 30
Output Noise nOUT IOUTFS = 20mA 30 pA/√Hz
TIMING CHARACTERISTICS
Data to Clock Setup Time tSETUP Referenced to rising edge of clock (Note 6) -0.6 -1.2 ns
Data to Clock Hold Time tHOLD Referenced to rising edge of clock (Note 6) 2.1 1.5 ns
Latency to I output 9
Single-Port (Interleaved Mode)
Data Latency Latency to Q output 8
Clock
cycles
Dual-Port (Parallel Mode) Data
Latency 5.5 Clock
cycles
Minimum Clock Pulse-Width High tCH CLKP, CLKN 2.4 ns
Minimum Clock Pulse-Width Low tCL CLKP, CLKN 2.4 ns
CMOS LOGIC INPUTS (A13/B13–A0/B0, XOR, SELIQ, PD, TORB, DORI)
Input Logic High VIH 0.7 x
DVDD3.3 V
Input Logic Low VIL 0.3 x
DVDD3.3 V
Input Leakage Current IIN 120µA
PD, TORB, DORI Internal
Pulldown Resistance VPD = VTORB = VDORI = 3.3V 1.5 MΩ
Input Capacitance CIN 2.5 pF
CLOCK INPUTS (CLKP, CLKN)
Sine wave > 1.5
Differential Input Voltage Swing Square wave > 0.5 VP-P
Differential Input Slew Rate SRCLK (Note 7) > 100 V/µs
External Common-Mode Voltage
Range VCOM AVCLK / 2
±0.3 V
Input Resistance RCLK 5kΩ
Input Capacitance CCLK 2.5 pF
POWER SUPPLIES
AVDD3.3 3.135 3.3 3.465
Analog Supply Voltage Range AVDD1.8 1.710 1.8 1.890 V
DVDD3.3 3.135 3.3 3.465
Digital Supply Voltage Range DVDD1.8 1.710 1.8 1.890 V
Clock Supply Voltage Range AVCLK 3.135 3.3 3.465 V
MAX5874
14-Bit, 200Msps, High-Dynamic-Performance,
Dual DAC with CMOS Inputs
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (continued)
(AVDD3.3 = DVDD3.3 = AVCLK = 3.3V, AVDD1.8 = DVDD1.8 = 1.8V, GND = 0, external reference VREFIO = 1.25V, output load 50Ωdouble-
terminated, transformer-coupled output, IOUTFS = 20mA, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
(Note 2)
Note 2: Specifications at TA≥+25°C are guaranteed by production testing. Specifications at TA< +25°C are guaranteed by design
and characterization data.
Note 3: Nominal full-scale current IOUTFS = 32 x IREF.
Note 4: This parameter does not include update-rate-dependent effects of sin(x)/x filtering inherent in the MAX5874.
Note 5: Parameter measured single-ended into a 50Ωtermination resistor.
Note 6: Not production tested. Guaranteed by design and characterization data.
Note 7: A differential clock input slew rate of > 100V/µs is required to achieve the specified dynamic performance.
Note 8: Parameter defined as the change in midscale output caused by a ±5% variation in the nominal supply voltage.
Typical Operating Characteristics
(AVDD3.3 = DVDD3.3 = AVCLK = 3.3V, AVDD1.8 = DVDD1.8 = 1.8V, external reference, VREFIO = 1.25V, RL = 50Ωdouble-terminated,
IOUTFS = 20mA, TA= +25°C, unless otherwise noted.)
SINGLE-TONE SFDR vs. OUTPUT
FREQUENCY (fCLK = 50Msps)
MAX5874 toc01
fOUT (MHz)
SFDR (dBc)
2015105
20
40
60
80
100
0
025
-12dBFS -6dBFS
0dBFS
SINGLE-TONE SFDR vs. OUTPUT
FREQUENCY (fCLK = 100Msps)
MAX5874 toc02
fOUT (MHz)
SFDR (dBc)
40302010
20
40
60
80
100
0
050
-12dBFS -6dBFS
0dBFS
SINGLE-TONE SFDR vs. OUTPUT
FREQUENCY (fCLK = 150Msps)
MAX5874 toc03
fOUT (MHz)
SFDR (dBc)
60453015
20
40
60
80
100
0
075
-12dBFS -6dBFS
0dBFS
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
fDAC = 200Msps, fOUT = 1MHz 53 58
IAVDD3.3
+ IAVCLK Power-down 0.001 mA
fDAC = 200Msps, fOUT = 1MHz 24 32
Analog Supply Current
IAVDD1.8 Power-down 0.001 mA
fDAC = 200Msps, fOUT = 1MHz 1.5 3
IDVDD3.3 Power-down 0.001 mA
fDAC = 200Msps, fOUT = 1MHz 21 25
Digital Supply Current
IDVDD1.8 Power-down 0.001 mA
fDAC = 200Msps, fOUT = 1MHz 260 300 mW
Power Dissipation PDISS Power-down 14 µW
Power-Supply Rejection Ratio PSRR AVDD3.3 = AVCLK = DVDD3.3 = +3.3V ±5%
(Notes 7, 8) -0.1 +0.1 %FS/V
MAX5874
14-Bit, 200Msps, High-Dynamic-Performance,
Dual DAC with CMOS Inputs
6 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(AVDD3.3 = DVDD3.3 = AVCLK = 3.3V, AVDD1.8 = DVDD1.8 = 1.8V, external reference, VREFIO = 1.25V, RL = 50Ωdouble-terminated,
IOUTFS = 20mA, TA= +25°C, unless otherwise noted.)
TWO-TONE IMD vs. OUTPUT FREQUENCY
(1MHz CARRIER SPACING, fCLK = 200Msps)
MAX5874 toc07
fOUT (MHz)
TWO-TONE IMD (dBc)
70605040302010
-90
-80
-70
-60
-50
-40
-100
080
-6dBFS
-12dBFS
SFDR vs. FULL-SCALE OUTPUT CURRENT
(fCLK = 200MHz)
MAX5874 toc08
fOUT (MHz)
SFDR (dBc)
80604020
20
40
60
80
100
0
0 100
AOUT = -6dBFS
10mA
5mA
20mA
SFDR vs. TEMPERATURE
(fCLK = 200MHz)
MAX5874 toc09
fOUT (MHz)
SFDR (dBc)
80604020
70
65
80
75
90
85
95
60
0 100
AOUT = -6dBFS
TA = +25°C
TA = -40°C
TA = +85°C
INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODE
MAX5874 toc10
DIGITAL INPUT CODE
INL (LSB)
12,28881924096
-0.75
-0.50
-0.25
0
0.25
0.50
0.75
1.00
-1.00
0 16,384
DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE
MAX5874 toc11
DIGITAL INPUT CODE
DNL (LSB)
12,28881924096
-0.50
-0.25
0
0.25
0.50
0.75
1.00
0 16,384
POWER DISSIPATION vs. CLOCK
FREQUENCY (fOUT = 10MHz)
MAX5874 toc12
fCLK (MHz)
POWER DISSIPATION (mW)
190170150130110907050
200
220
240
260
280
180
30
AOUT = 0dBFS
SINGLE-TONE SFDR vs. OUTPUT
FREQUENCY (fCLK = 200Msps)
MAX5874 toc04
fOUT (MHz)
SFDR (dBc)
80604020
20
40
60
80
100
0
0100
-12dBFS -6dBFS
0dBFS
TWO-TONE IMD vs. OUTPUT FREQUENCY
(1MHz CARRIER SPACING, fCLK = 100Msps)
MAX5874 toc05
fOUT (MHz)
TWO-TONE IMD (dBc)
353025201510
-90
-80
-70
-60
-50
-40
-100
540
-6dBFS
-12dBFS
TWO-TONE IMD
(fCLK = 100Msps)
MAX5874 toc06
fOUT (MHz)
OUTPUT POWER (dBFS)
3432302826
-80
-60
-40
-20
0
-100
24 36
BW = 12MHz
2 x fOUT1 - fOUT22 x fOUT2 - fOUT1
fOUT1 fOUT2
fOUT1 = 29.8706MHz
fOUT2 = 30.9937MHz
MAX5874
14-Bit, 200Msps, High-Dynamic-Performance,
Dual DAC with CMOS Inputs
_______________________________________________________________________________________ 7
Typical Operating Characteristics (continued)
(AVDD3.3 = DVDD3.3 = AVCLK = 3.3V, AVDD1.8 = DVDD1.8 = 1.8V, external reference, VREFIO = 1.25V, RL = 50Ωdouble-terminated,
IOUTFS = 20mA, TA= +25°C, unless otherwise noted.)
POWER DISSIPATION vs. SUPPLY VOLTAGE
(fCLK = 100MHz, fOUT = 10MHz)
MAX5874 toc13
SUPPLY VOLTAGE (V)
POWER DISSIPATION (mW)
3.4353.3353.235
200
210
220
230
240
190
3.135
AOUT = 0dBFS
EXTERNAL REFERENCE
INTERNAL REFERENCE
FOUR-TONE POWER RATIO PLOT
(fCLK = 150MHz, fCENTER = 31.6040MHz )
MAX5874 toc14
fOUT (MHz)
OUTPUT POWER (dBFS)
3634323028
-80
-60
-40
-20
0
-100
26 38
BW = 12MHz
fOUT1
fOUT2
fOUT4
fOUT3
fOUT1 = 29.9997MHz
fOUT2 = 31.0251MHz
fOUT3 = 31.0640MHz
fOUT4 = 32.9829MHz
ACLR FOR WCDMA MODULATION,
TWO CARRIERS
MAX5874 toc15
3.05MHz/div
ANALOG OUTPUT POWER (dBm)
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-120
fCLK = 184.32MHz
fCENTER = 30.72MHz
ACLR = 76dB
ACLR FOR WCDMA MODULATION,
SINGLE CARRIER
MAX5874 toc16
9.2MHz/div
ANALOG OUTPUT POWER (dBm)
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
DC 92.16MHz
fCENTER = 61.44MHz
fCLK = 184.32MHz
ACLR = 75dB
-20
WCDMA BASEBAND ACLR
MAX5874 toc17
NUMBER OF CARRIERS
ACLR (dB)
4321
76
77
82
84
85
75
ALTERNATE
ADJACENT
83
81
80
79
78
79.5
84.5
78.6
79.4 79.0
81.4
78.6
79.7
MAX5874
14-Bit, 200Msps, High-Dynamic-Performance,
Dual DAC with CMOS Inputs
8 _______________________________________________________________________________________
Pin Description
PIN NAME FUNCTION
1–7 A6, A5, A4,
A3, A2, A1, A0
Data Bits A6–A0. In dual-port mode, data is directed to the Q-DAC. In single-port mode, data bits
are not used. Connect bits A6–A0 to GND in single-port mode.
8, 9, 59, 60 N.C. No Connection. Leave floating or connect to GND.
10, 12, 13, 15,
20, 23, 26, 27,
30, 33, 36, 43
GND Converter Ground
11 DVDD3.3 Digital Supply Voltage. Accepts a 3.135V to 3.465V supply voltage range. Bypass with a 0.1µF
capacitor to GND.
14, 21, 22, 31,
32 AVDD3.3 Analog Supply Voltage. Accepts a 3.135V to 3.465V supply voltage range. Bypass each pin with
a 0.1µF capacitor to GND.
16 REFIO Reference I/O. Output of the internal 1.2V precision bandgap reference. Bypass with a 1µF
capacitor to GND. REFIO can be driven with an external reference source. See Table1.
17 FSADJ Full-Scale Adjust Input. This input sets the full-scale output current of the DAC. For a 20mA full-
scale output current, connect a 2kΩ resistor between FSADJ and DACREF. See Table1.
18 DACREF
Current-Set Resistor Return Path. For a 20mA full-scale output current, connect a 2kΩ resistor
between FSADJ and DACREF. Internally connected to GND. Do not use as an external ground
connection.
19, 34 AVDD1.8 Analog Supply Voltage. Accepts a 1.71V to 1.89V supply voltage range. Bypass each pin with a
0.1µF capacitor to GND.
24 OUTQN Complementary Q-DAC Output. Negative terminal for current output.
25 OUTQP Q-DAC Output. Positive terminal for current output.
28 OUTIN Complementary I-DAC Output. Negative terminal for current output.
29 OUTIP I-DAC Output. Positive terminal for current output.
35 AVCLK Clock Supply Voltage. Accepts a 3.135V to 3.465V supply voltage range. Bypass with a 0.1µF
capacitor to GND.
37 CLKN Complementary Converter Clock Input. Negative input terminal for differential converter clock.
Internally biased to AVCLK / 2.
38 CLKP Converter Clock Input. Positive input terminal for differential converter clock. Internally biased to
AVCLK / 2.
39 TORB
Two’s-Complement/Binary Select Input. Set TORB to a CMOS-logic-high level to indicate a two’s-
complement input format. Set TORB to a CMOS-logic-low level to indicate a binary input format.
TORB has an internal pulldown resistor.
40 PD Power-Down Input. Set PD to a CMOS-logic-high level to force the DAC into power-down mode.
Set PD to a CMOS-logic-low level for normal operation. PD has an internal pulldown resistor.
41 DORI
Dual (Parallel)/Single (Interleaved) Port Select Input. Set DORI high to configure as a dual-port
DAC. Set DORI low to configure as a single-port interleaved DAC. DORI has an internal pulldown
resistor.
MAX5874
14-Bit, 200Msps, High-Dynamic-Performance,
Dual DAC with CMOS Inputs
_______________________________________________________________________________________ 9
Detailed Description
Architecture
The MAX5874 high-performance, 14-bit, dual current-
steering DAC (Figure 1) operates with DAC update rates
up to 200Msps. The converter consists of input registers
and a demultiplexer for single-port (interleaved) mode,
followed by a current-steering array. During operation in
interleaved mode, the input data registers demultiplex
the single-port data bus. The current-steering array gen-
erates differential full-scale currents in the 2mA to 20mA
range. An internal current-switching network, in combina-
tion with external 50Ωtermination resistors, converts the
differential output currents into dual differential output
voltages with a 0.1V to 1V peak-to-peak output voltage
range. An integrated 1.2V bandgap reference, control
amplifier, and user-selectable external resistor determine
the data converter’s full-scale output range.
Reference Architecture and Operation
The MAX5874 supports operation with the internal 1.2V
bandgap reference or an external reference voltage
source. REFIO serves as the input for an external, low-
impedance reference source. REFIO also serves as a
reference output when the DAC operates in internal ref-
erence mode. For stable operation with the internal ref-
erence, decouple REFIO to GND with a 1µF capacitor.
Due to its limited output-drive capability, buffer REFIO
with an external amplifier when driving large
external loads.
The MAX5874’s reference circuit (Figure 2) employs a
control amplifier to regulate the full-scale current
IOUTFS for the differential current outputs of the DAC.
Calculate the full-scale output current as follows:
where IOUTFS is the full-scale output current of the
DAC. RSET (located between FSADJ and DACREF)
determines the amplifier’s full-scale output current for
the DAC. See Table 1 for a matrix of different IOUTFS
and RSET selections.
IV
R
OUTFS REFIO
SET
=× ×
⎛
⎝
⎜
⎞
⎠
⎟
−32 1 1
214
Pin Description (continued)
PIN NAME FUNCTION
42 XOR DAC Exclusive-OR Select Input. Set XOR low to allow the data stream to pass unchanged to the
DAC input. Set XOR high to invert the input data into the DAC. If unused, connect XOR to GND.
44 SELIQ
DAC Select Input. Set SELIQ low to direct data into the Q-DAC inputs. Set SELIQ high to direct
data into the I-DAC inputs. If unused, connect SELIQ to GND. SELIQ’s logic state is only valid in
single-port (interleaved) mode.
45–58
B13, B12, B11,
B10, B9, B8,
B7, B6, B5, B4,
B3, B2, B1, B0
Data Bits B13–B0. In dual-port mode, data is directed to the I-DAC. In single-port mode, the state
of SELIQ determines where the data bits are directed.
61 DVDD1.8 Digital Supply Voltage. Accepts a 1.71V to 1.89V supply voltage range. Bypass with a 0.1µF
capacitor to GND.
62–68 A13, A12, A11,
A10, A9, A8, A7
Data Bits A13–A7. In dual-port mode, data is directed to the Q-DAC. In single-port mode, data
bits are not used. Connect bits A13–A7 to GND in single-port mode.
— EP Exposed Pad. Must be connected to GND through a low-impedance path.
Table 1. IOUTFS and RSET Selection
Matrix Based on a Typical 1.200V
Reference Voltage
RSET (Ω)
FULL-SCALE
CURRENT IOUTFS (mA) CALCULATED 1% EIA STD
2 19.2k 19.1k
5 7.68k 7.5k
10 3.84k 3.83k
15 2.56k 2.55k
20 1.92k 1.91k
MAX5874
14-Bit, 200Msps, High-Dynamic-Performance,
Dual DAC with CMOS Inputs
10 ______________________________________________________________________________________
Analog Outputs
(OUTIP, OUTIN, OUTQP, OUTQN)
Each MAX5874 DAC outputs two complementary cur-
rents (OUTIP/N, OUTQP/N) that operate in a single-
ended or differential configuration. A load resistor
converts these two output currents into complementary
single-ended output voltages. A transformer or a differ-
ential amplifier configuration converts the differential
voltage existing between OUTIP (OUTQP) and OUTIN
(OUTQN) to a single-ended voltage. If not using a
transformer, the recommended termination from the
output is a 25Ωtermination resistor to ground and a
50Ωresistor between the outputs.
To generate a single-ended output, select OUTIP (or
OUTQP) as the output and connect OUTIN (or OUTQN)
to GND. SFDR degrades with single-ended operation.
Figure 3 displays a simplified diagram of the internal
output structure of the MAX5874.
Clock Inputs (CLKP, CLKN)
The MAX5874 features flexible differential clock inputs
(CLKP, CLKN) operating from a separate supply
(AVCLK) to achieve the optimum jitter performance.
Drive the differential clock inputs from a single-ended
or a differential clock source. For single-ended opera-
tion, drive CLKP with a logic source and bypass CLKN
to GND with a 0.1µF capacitor.
CLKP and CLKN are internally biased to AVCLK / 2. This
facilitates the AC-coupling of clock sources directly to
the device without external resistors to define the DC
level. The dynamic input resistance from CLKP and
CLKN to ground is > 5kΩ.
Data Timing Relationship
Figure 4 displays the timing relationship between digital
CMOS data, clock, and output signals. The MAX5874
features a 1.5ns hold, a -1.2ns setup, and a 1.1ns propa-
gation delay time. A nine (eight)-clock-cycle latency
exists between CLKP/CLKN and OUTIP/OUTIN
(OUTQP/OUTQN) when operating in single-port (inter-
leaved) mode. In dual-port (parallel) mode, the clock
latency is 5.5 clock cycles for both channels. Table 2
shows the DAC output codes.
LATCH XOR/
DECODE LATCH
CMOS
RECEIVER LATCH
LATCH DAC
OUTIP
OUTIN
LATCH XOR/
DECODE LATCH LATCH DAC
OUTQP
OUTQN
FSADJ
TORB
SELIQ
XOR
AVCLK
CLKN
GND
CLKP
CLK
INTERFACE
DATA13–
DATA0
1.2V
REFERENCE
POWER-DOWN
BLOCK
REFIO
DACREF
PD GND
DVDD1.8
DVDD3.3 GND AVDD1.8 AVDD3.3
DORI
MAX5874
Figure 1. MAX5874 High-Performance, 14-Bit, Dual Current-Steering DAC
MAX5874
14-Bit, 200Msps, High-Dynamic-Performance,
Dual DAC with CMOS Inputs
______________________________________________________________________________________ 11
CMOS-Compatible Digital Inputs
Input Data Format Select (TORB,
DORI
)
The TORB input selects between two’s-complement or
binary digital input data. Set TORB to a CMOS-logic-
high level to indicate a two’s-complement input format.
Set TORB to a CMOS-logic-low level to indicate a binary
input format.
The DORI input selects between a dual-port (parallel) or
single-port (interleaved) DAC. Set DORI high to configure
the MAX5874 as a dual-port DAC. Set DORI low to con-
figure the MAX5874 as a single-port DAC. In dual-port
mode, connect SELIQ to ground.
CMOS DAC Inputs (A13/B13–A0/B0, XOR, SELIQ)
The MAX5874 latches input data on the rising edge of
the clock in a user-selectable two’s-complement or
binary format. A logic-high voltage on TORB selects
two’s-complement and a logic-low selects offset
binary format.
The MAX5874 includes a single-ended, CMOS-compati-
ble XOR input. Input data (all bits) are compared with the
bit applied to XOR through exclusive-OR gates. Pulling
XOR high inverts the input data. Pulling XOR low leaves
the input data noninverted. By applying a previously
encoded pseudo-random bit stream to the data input and
applying decoding to XOR, the digital input data can be
decorrelated from the DAC output, allowing for the trou-
bleshooting of possible spurious or harmonic distortion
degradation due to digital feedthrough on the printed
circuit board (PCB).
A13/B13–A0/B0, XOR, and SELIQ are latched on the ris-
ing edge of the clock. In single-port mode (DORI pulled
low) a logic-high signal on SELIQ directs the B13–B0
data onto the I-DAC inputs. A logic-low signal at SELIQ
directs data to the Q-DAC inputs. In dual-port (parallel)
mode (DORI pulled high), data on pins A13–A0 are
directed onto the Q-DAC inputs and B13–B0 are directed
onto the I-DAC inputs.
Power-Down Operation (PD)
The MAX5874 also features an active-high power-
down mode that reduces the DAC’s digital current
consumption from 22mA to less than 2µA and the ana-
log current consumption from 77mA to less than 2µA.
Set PD high to power down the MAX5874. Set PD low
for normal operation.
When powered down, the power consumption of the
MAX5874 is reduced to less than 14µW. The MAX5874
requires 10ms to wake up from power-down and enter a
fully operational state. The PD integrated pulldown resistor
activates the MAX5874 if PD is left floating.
OUTIP
OUTIN
1.2V
REFERENCE
CURRENT-SOURCE
ARRAY DAC
REFIO
FSADJ
RSET
IREF
10kΩ
DACREF
1µF
IREF = VREFIO / RSET
Figure 2. Reference Architecture, Internal Reference
Configuration
IOUT IOUT
OUTIN OUTIP
CURRENT
SOURCES
CURRENT
SWITCHES
AVDD
Figure 3. Simplified Analog Output Structure
Table 2. DAC Output Code Table
DIGITAL INPUT CODE
OFFSET
BINARY
TWO’S
COMPLEMENT
OUT_P OUT_N
00 0000 0000 0000 10 0000 0000 0000 0 IOUTFS
01 1111 1111 1111 00 0000 0000 0000 IOUTFS / 2 IOUTFS / 2
11 1111 1111 1111 01 1111 1111 1111 IOUTFS 0
MAX5874
14-Bit, 200Msps, High-Dynamic-Performance,
Dual DAC with CMOS Inputs
12 ______________________________________________________________________________________
Applications Information
CLK Interface
The MAX5874 features a flexible differential clock input
(CLKP, CLKN) with a separate supply (AVCLK) to
achieve optimum jitter performance. Use an ultra-low
jitter clock to achieve the required noise density. Clock
jitter must be less than 0.5psRMS for meeting the speci-
fied noise density. For that reason, the CLKP/CLKN
input source must be designed carefully. The differen-
tial clock (CLKN and CLKP) input can be driven from a
single-ended or a differential clock source. Differential
clock drive is required to achieve the best dynamic
performance from the DAC. For single-ended opera-
tion, drive CLKP with a low-noise source and bypass
CLKN to GND with a 0.1µF capacitor.
Figure 5 shows a convenient and quick way to apply a
differential signal created from a single-ended source
(e.g., HP/AGILENT 8644B signal generator) and a wide-
band transformer. Alternatively, these inputs can be
driven from a CMOS-compatible clock source; however, it
is recommended to use sinewave or AC-coupled differ-
ential ECL/PECL drive for best dynamic performance.
tStH
tPD
DATA13–DATA0, XOR
CLK
DAC OUTPUT
N - 1 N N + 1 N + 2
N - 5 N - 4 N - 3
N - 2
N - 6
SELIQ
CLK
DATAIN I0 Q2I2Q1I1 I3 Q3Q0
tStH
I OUT
Q OUT
tPD
I - 5 I - 4 I - 2
I - 3
I - 6
Q - 6 Q - 5
Q - 4
Q - 3 Q - 2
(a) DUAL-PORT (PARALLEL) TIMING DIAGRAM
(b) SINGLE-PORT (INTERLEAVED) TIMING DIAGRAM
Figure 4. Timing Relationships Between Clock and Input Data for (a) Dual-Port (Parallel) Mode and (b) Single-Port (Interleaved) Mode
MAX5874
14-Bit, 200Msps, High-Dynamic-Performance,
Dual DAC with CMOS Inputs
______________________________________________________________________________________ 13
Differential-to-Single-Ended Conversion
Using a Wideband RF Transformer
Use a pair of transformers (Figure 6) or a differential
amplifier configuration to convert the differential voltage
existing between OUTIP/OUTQP and OUTIN/OUTQN to
a single-ended voltage. Optimize the dynamic perfor-
mance by using a differential transformer-coupled output
to limit the output power to < 0dBm full scale. Pay close
attention to the transformer core saturation characteris-
tics when selecting a transformer for the MAX5874.
Transformer core saturation can introduce strong 2nd-
order harmonic distortion, especially at low output fre-
quencies and high signal amplitudes. For best results,
center tap the transformer to ground. When not using a
transformer, terminate each DAC output to ground with a
25Ωresistor. Additionally, place a 50Ωresistor between
the outputs (Figure 7).
For a single-ended unipolar output, select OUTIP
(OUTQP) as the output and ground OUTIN (OUTQN) to
GND. Driving the MAX5874 single-ended is not recom-
mended since additional noise and distortion will
be added.
The distortion performance of the DAC depends on the
load impedance. The MAX5874 is optimized for 50Ω
differential double termination. It can be used with a
transformer output as shown in Figure 6 or just one 25Ω
resistor from each output to ground and one 50Ωresis-
tor between the outputs (Figure 7). This produces a full-
scale output power of up to -2dBm, depending on the
output current setting. Higher termination impedance
can be used at the cost of degraded distortion perfor-
mance and increased output noise voltage.
Grounding, Bypassing, and Power-
Supply Considerations
Grounding and power-supply decoupling can strongly
influence the MAX5874 performance. Unwanted digital
crosstalk couples through the input, reference, power
supply, and ground connections, and affects dynamic
performance. High-speed, high-frequency applications
require closely followed proper grounding and power-
supply decoupling. These techniques reduce EMI and
internal crosstalk that can significantly affect the
MAX5874 dynamic performance.
Use a multilayer PCB with separate ground and power-
supply planes. Run high-speed signals on lines directly
above the ground plane. Keep digital signals as far
away from sensitive analog inputs and outputs, refer-
ence input sense lines, and clock inputs as practical.
Use a controlled-impedance symmetric design of
clock input and the analog output lines to minimize
2nd-order harmonic distortion components, thus
WIDEBAND RF TRANSFORMER
PERFORMS SINGLE-ENDED-TO-
DIFFERENTIAL CONVERSION
SINGLE-ENDED
CLOCK SOURCE
GND
1:1
25Ω
25Ω
CLKP
CLKN
TO DAC
0.1µF
0.1µF
Figure 5. Differential Clock-Signal Generation
MAX5874
14
OUTIP/OUTQP
OUTIN/OUTQN
DATA13–DATA0
WIDEBAND RF TRANSFORMER T2 PERFORMS THE
DIFFERENTIAL-TO-SINGLE-ENDED CONVERSION
T1, 1:1
T2, 1:1
GND
50Ω
100Ω
50Ω
VOUT, SINGLE-ENDED
Figure 6. Differential-to-Single-Ended Conversion Using a Wideband RF Transformer
MAX5874
14-Bit, 200Msps, High-Dynamic-Performance,
Dual DAC with CMOS Inputs
14 ______________________________________________________________________________________
optimizing the DAC’s dynamic performance. Keep digi-
tal signal paths short and run lengths matched to avoid
propagation delay and data skew mismatches.
The MAX5874 requires five separate power-supply
inputs for analog (AVDD1.8 and AVDD3.3), digital
(DVDD1.8 and DVDD3.3), and clock (AVCLK) circuitry.
Decouple each AVDD, DVDD, and AVCLK input pin with
a separate 0.1µF capacitor as close to the device as
possible with the shortest possible connection to the
ground plane (Figure 8). Minimize the analog and digi-
tal load capacitances for optimized operation.
Decouple all three power-supply voltages at the point
they enter the PCB with tantalum or electrolytic capaci-
tors. Ferrite beads with additional decoupling capaci-
tors forming a pi-network could also improve
performance.
The analog and digital power-supply inputs AVDD3.3,
AVCLK, and DVDD3.3 allow a 3.135V to 3.465V supply
voltage range. The analog and digital power-supply
inputs AVDD1.8 and DVDD1.8 allow a 1.71V to 1.89V
supply voltage range.
The MAX5874 is packaged in a 68-pin QFN-EP pack-
age, providing greater design flexibility and optimized
DAC AC performance. The EP enables the use of nec-
essary grounding techniques to ensure highest perfor-
mance operation. Thermal efficiency is not the key
factor, since the MAX5874 features low-power opera-
tion. The exposed pad ensures a solid ground connec-
tion between the DAC and the PCB’s ground layer.
The data converter die attaches to an EP lead frame
with the back of this frame exposed at the package
bottom surface, facing the PCB side of the package.
This allows for a solid attachment of the package to the
PCB with standard infrared (IR) reflow soldering tech-
niques. A specially created land pattern on the PCB,
matching the size of the EP (6mm x 6mm), ensures the
proper attachment and grounding of the DAC. Refer to
the MAX5874 EV kit data sheet. Designing vias into the
land area and implementing large ground planes in the
PCB design allow for the highest performance opera-
tion of the DAC. Use an array of at least 4 x 4 vias
(≤0.3mm diameter per via hole and 1.2mm pitch
between via holes) for this 68-pin QFN-EP package.
Connect the MAX5874 exposed paddle to GND. Vias
connect the land pattern to internal or external copper
planes. Use as many vias as possible to the ground
plane to minimize inductance.
MAX5874
14
OUTIP/OUTQP
OUTIN/OUTQN
DATA13–DATA0
GND
25Ω
50Ω
25Ω
OUTP
OUTN
Figure 7. Differential Output Configuration
MAX5874
14
OUTIP/OUTQP
OUTIN/OUTQN
DATA13–DATA0
0.1µF
AVDD1.8
DVDD1.8
0.1µF
0.1µF0.1µF
AVDD3.3
DVDD3.3
0.1µF
AVCLK
BYPASSING—DAC LEVEL
*BYPASS EACH POWER-SUPPLY PIN INDIVIDUALLY.
Figure 8. Recommended Power-Supply Decoupling and
Bypassing Circuitry
MAX5874
14-Bit, 200Msps, High-Dynamic-Performance,
Dual DAC with CMOS Inputs
______________________________________________________________________________________ 15
Static Performance Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an
actual transfer function from either a best straight-line fit
(closest approximation to the actual transfer curve) or a
line drawn between the end points of the transfer func-
tion, once offset and gain errors have been nullified. For a
DAC, the deviations are measured at every individual
step.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an actu-
al step height and the ideal value of 1 LSB. A DNL error
specification of less than 1 LSB guarantees a monoton-
ic transfer function.
Offset Error
The offset error is the difference between the ideal and
the actual offset current. For a DAC, the offset point is
the average value at the output for the two midscale
digital input codes with respect to the full scale of the
DAC. This error affects all codes by the same amount.
Gain Error
A gain error is the difference between the ideal and the
actual full-scale output voltage on the transfer curve,
after nullifying the offset error. This error alters the slope
of the transfer function and corresponds to the same
percentage error in each step.
Dynamic Performance Parameter Definitions
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital sam-
ples, the theoretical maximum SNR is the ratio of the full-
scale analog output (RMS value) to the RMS quantization
error (residual error). The ideal, theoretical minimum can
be derived from the DAC’s resolution (N bits):
SNR = 6.02 x N + 1.76
However, noise sources such as thermal noise, reference
noise, clock jitter, etc., affect the ideal reading; therefore,
SNR is computed by taking the ratio of the RMS signal to
the RMS noise, which includes all spectral components
minus the fundamental, the first four harmonics, and the
DC offset.
Noise Spectral Density
The DAC output noise floor is the sum of the quantiza-
tion noise and the output amplifier noise (thermal and
shot noise). Noise spectral density is the noise power in
1Hz bandwidth, specified in dBFS/Hz.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of RMS amplitude of the carrier fre-
quency (maximum signal components) to the RMS value
of their next-largest distortion component. SFDR is usual-
ly measured in dBc and with respect to the carrier fre-
quency amplitude or in dBFS with respect to the DAC’s
full-scale range. Depending on its test condition, SFDR is
observed within a predefined window or to Nyquist.
Two-Tone Intermodulation Distortion (IMD)
The two-tone IMD is the ratio expressed in dBc (or dBFS)
of the worst 3rd-order (or higher) IMD product(s) to either
output tone.
Adjacent Channel Leakage Power Ratio (ACLR)
Commonly used in combination with wideband code-
division multiple-access (W-CDMA), ACLR reflects the
leakage power ratio in dB between the measured
power within a channel relative to its adjacent channel.
ACLR provides a quantifiable method of determining
out-of-band spectral energy and its influence on an
adjacent channel when a bandwidth-limited RF signal
passes through a nonlinear device.
Settling Time
The settling time is the amount of time required from the
start of a transition until the DAC output settles its new
output value to within the converter’s specified accuracy.
Glitch Impulse
A glitch is generated when a DAC switches between two
codes. The largest glitch is usually generated around the
midscale transition, when the input pattern transitions from
011...111 to 100...000. The glitch impulse is found by inte-
grating the voltage of the glitch at the midscale transition
over time. The glitch impulse is usually specified in pV•s.
MAX5874
14-Bit, 200Msps, High-Dynamic-Performance,
Dual DAC with CMOS Inputs
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
68L QFN.EPS
C
12
21-0122
PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM
C
12
21-0122
PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM
Revision History
Pages changed at Rev 2: 1–16