SN74LVC1G175DBVR - TEXAS INSTRUMENTS

May 1988

Revised September 2000

74F374 Octal D-Type Flip-Flop with 3-STATE Outputs

74F374

Octal D-Type Flip-Flop with 3-STATE Outputs

General Description

The 74F374 is a high-speed, low-power octal D-type flip-

flop fe aturing separate D-type inp uts for each fli p-flop and

3-STATE outputs for bus-oriented applications. A buffered

Clock (CP) and Ou tpu t Enab l e (OE) are common to all flip-

flops.

Features

■Edge-triggered D-type inputs

■Buffered positive edg e- trigg er ed cl ock

■3-STATE outputs for bus-oriented applications

■Guaranteed 4000V minimum ESD pro tection

Ordering Code:

Devices also available in Tape and R eel. Speci fy by append ing the suffix let t er “X” to the o rdering code.

Logic Symbols

IEEE/IEC

Connection Diagram

Order Number Package Number Package Description

74F374SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

74F374SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74F374MSA MSA20 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide

74F374PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

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74F374

Unit Loading/Fan Out

Functional Description

The 74 F374 con sists of ei ght edg e-trigger ed flip-f lops with

individual D-type inputs and 3-STATE true outputs. The

buffered cl ock and buffered Output Enable ar e common to

all flip-flops. The eight flip-flops will store the state of their

individual D inputs that meet the setup and hold time

requirements on the LOW-to-HIGH Clock (CP) transition.

With the Output Enable (OE) LOW, the contents of the

eight flip-flops are availab le at the ou tputs. When the OE is

HIGH, th e outputs go to the high imp edance state . Opera-

tion of the OE input does no t affected th e state of the flip -

flops.

Truth Table

H = HIGH Voltage Lev el

L = LOW Voltage Level

X = Immaterial

Z = High Impedance



= LOW-to-HIGH Clock Transition

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation dela ys.

Pin Names Description U.L. In put IIH/IIL

HIGH/LOW Output IOH/IOL

D0–D7Data Inputs 1.0/1.0 20 µA/−0.6 mA

CP Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 µA/−0.6 mA

OE 3-STATE Output Enable Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA

O0–O73-STATE Outputs 150/40 (33.3) −3 mA/24 mA (20 mA)

Inputs Internal Output

DnCP OE Register On



LH H



LL L

XXH X Z

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74F374

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: Absolute maximum ratings are values beyond which the device

may be damaged or have its useful life impaired. Functional operation

under these conditions is not implied.

Note 2: Eith er v oltage lim it or c urrent limit is sufficie nt to protect inputs.

DC Electrical Characteristics

Storage Temperature −65°C to +150°C

Ambient Temper atu re und er Bias −55°C to +125°C

Junction Temperature under Bias −55°C to +150°C

VCC Pin Potential to Ground Pin −0.5V to +7.0V

Input Voltage (Note 2) −0.5V to +7.0V

Input Current (Note 2) −30 mA to +5.0 mA

Voltage Applied to Output

in HIGH State (with VCC = 0V)

Standa rd Outp ut −0.5V to VCC

3-STATE Output −0.5V to +5.5V

Current Applied to Output

in LOW State (Ma x) twice the rat ed IOL (mA)

ESD Last Passing Voltage (Min) 4000V

Free Air Ambient Temperature 0°C to +70°C

Supply Voltage +4.5V to +5.5V

Symbol Parameter Min Typ Max Units VCC Conditions

VIH Input HIGH Voltage 2.0 V Recognized as a HIGH Signal

VIL Input LOW Voltage 0.8 V Recognized as a LOW Signal

VCD Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA

VOH Output HIGH 10% VCC 2.5

VMin

IOH = −1 mA

Voltage 10% VCC 2.4 IOH = −3 mA

5% VCC 2.7 IOH = −1 mA

5% VCC 2.7 IOH = −3 mA

VOL Output LOW Voltage 10% VCC 0.5 V Min IOL = 24 mA

IIH Input HIGH 5.0 µAMaxV

IN = 2.7 V

Current

IBVI Input HIGH Current 7.0 µAMaxV

IN = 7.0 V

Breakdown Test

ICEX Output HIGH 50 µAMaxV

OUT = VCC

Leakage Current

VID Input Leakage 4.75 V 0.0 IID = 1.9 µA

Test All Other Pins Grounded

IOD Output Leakage 3.75 µA0.0

VIOD = 150 mV

Circuit Current All Other Pins Grounded

IIL Input LOW Current −0.6 mA Max VIN = 0.5V

IOZH Output Leakage Current 50 µAMaxV

OUT = 2.7V

IOZL Output Leakage Current −50 µAMaxV

OUT = 0.5V

IOS Output Short-Circuit Current −60 −150 mA Max VOUT = 0V

IZZ Bus Drainage Test 500 µA0.0VV

OUT = 5.25V

ICCZ Power Supply Current 55 86 mA Max VO = HIGH Z

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74F374

AC Electrical Characteristics

AC Operating Requirements

Symbol Parameter

TA = +25°CT

A = −55°C to +125°CT

A = 0°C to +70°C

Units

VCC = +5.0V VCC = +5.0V VCC = +5.0V

CL = 50 pF CL = 50 pF CL = 50 pF

Min Typ Max Min Max Min Max

fMAX Maximum Clock Frequency 100 140 60 70 MHz

tPLH Propagation Delay 4.0 6.5 8.5 4.0 10.5 4.0 10.0 ns

tPHL CP to On4.0 6.5 8.5 4.0 11.0 4.0 10.0

tPZH Output Enable Time 2.0 9.0 11.5 2.0 14.0 2.0 12.5

tPZL 2.0 5.8 7.5 2.0 10.0 2.0 8.5

tPHZ Output Disable Time 2.0 5.3 7.0 2.0 8.0 2.0 8.0

tPLZ 1.54.35.51.57.51.56.5

Symbol Parameter

TA = +25°CT

A = −55°C to +125°CT

A = 0°C to +70°C

UnitsVCC = +5.0V VCC = +5.0V VCC = +5.0V

Min Max Min Max Min Max

tS(H) Setup Time, HIGH or LOW 2.0 2.5 2.0

tS(L) Dn to CP 2.0 2.0 2.0

tH(H) Hold Time, HIGH or LOW 2.0 2.0 2.0

tH(L) Dn to CP 2.0 2.5 2.0

tW(H) CP Puls e Widt h 7.0 7.0 7.0 ns

tW(L) HIGH or LOW 6.0 6.0 6.0

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74F374

Physical Dimensions inches (millimeters) unless otherwise noted

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

Package Number M20B

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74F374

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Sma ll Outline Package (SOP), EI AJ TYPE II, 5.3mm W ide

Package Number M20D

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74F374

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide

Package N umber MSA20

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74F374 Octal D-Type Flip-Flop with 3-STATE Outputs

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N20A

Fairchild does not assu me any responsibility for use of any circuitry de scribed, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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user.

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