TPS92075 www.ti.com SLUSB88B - DECEMBER 2012 - REVISED JANUARY 2014 Non-Isolated, Phase Dimmable, Buck PFC LED Driver with Digital Reference Control Check for Samples: TPS92075 FEATURES DESCRIPTION * * * * * * * The TPS92075 is a hybrid power factor controller (PFC) with a built-in phase dimming decoder. The device analyzes line cycles continuously using an internal, low-power, digital controller for shape and symmetry. The power converter stage generates an analog current reference and uses it to regulate the output current. The device uses control algorithms to manipulate the analog reference. These algorithms optimize dimmer compatibility, power factor and total harmonic distortion (THD). 1 * * * * * * * Controlled Reference Derived PFC Integrated Digital Phase-Angle Decoder Digital 50/60 Hz Synchronization Phase-Symmetry Balancing Constant LED current operation Fast Start-up Dimming Implemented Via Analog Reference Control Smooth Dimming Transitions Overvoltage Protection Feedback Short-Circuit Protection Leading and Trailing Edge Dimmer Compatibility Low BOM Cost and Small PCB Footprint Patent Pending Digital Architecture Available in 8-Pin SOIC and 6-Pin TSOT Using a constant off-time control, the solution achieves low component count, high efficiency and inherently provides variation in the switching frequency. This variation creates an emulated spread spectrum effect easing the converters EMI signature and allowing a smaller input filter. The TPS92075 also includes standard features: current limit, overvoltage protection, thermal shutdown, and VCC undervoltage lockout, all in packages utilizing only 6 pins. APPLICATIONS * * * Bulb Replacement Area Lighting Dimmable and Non-Dimmable LED Lamps SIMPLIFIED APPLICATION DIAGRAM A VIN AC A TPS92075 EMI Filter Triac Dimmer ASNS COFF GND VCC ISNS GATE OR B B Buck-Boost Buck UDG-12144 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2012-2014, Texas Instruments Incorporated TPS92075 SLUSB88B - DECEMBER 2012 - REVISED JANUARY 2014 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) TEMPERATURE RANGE (TJ) PACKAGE (2) PINS -40 to 125C SOIC 8 -40 to 125C (1) (2) 2 TSOT 6 ORDERABLE DEVICE NUMBER TRANSPORT MEDIUM QUANTITY TPS92075D Rail 95 TPS92075DR Tape and Reel 2500 TPS92075DDC Tape and Mini-Reel 1000 TPS92075DDCR Tape and Reel 3000 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: TPS92075 TPS92075 www.ti.com SLUSB88B - DECEMBER 2012 - REVISED JANUARY 2014 ABSOLUTE MAXIMUM RATINGS (1) All voltages are with respect to GND, -40C < TJ = TA < 125C, all currents are positive into and negative out of the specified terminal (unless otherwise noted) VALUE MIN Input voltage range Bias and ISNS MAX VCC -0.3 22 ASNS, COFF -0.3 6.0 IQ bias current (non-switching) Gate mA 2.5 V -0.3 18 V -2.5 20.5 V -0.3 GATE - continuous GATE - 100 ns Internally Limited Electrostatic discharge Human Body Model (HBM) 2 Field Induced Charged Device Model (FICDM) Operating junction temperature, TJ (3) Storage temperature range, Tstg -65 Lead temperature, soldering, 10s (1) (2) (3) V 2.5 ISNS (2) to Ground Continuous power dissipation UNIT kV 750 V 160 C 150 C 260 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ISNS can sustain -2 V for 100 ns without damage. Maximum junction temperature is internally limited. THERMAL INFORMATION TPS92075 THERMAL METRIC (1) Junction-to-ambient thermal resistance (2) JA (3) SOIC (D) TSOT (DDC) 8 PINS 6 PINS 112.3 165.5 JCtop Junction-to-case (top) thermal resistance 58.4 28.8 JB Junction-to-board thermal resistance (4) 52.5 24.6 JT Junction-to-top characterization parameter (5) 12.5 0.3 JB Junction-to-board characterization parameter (6) 51.9 23.8 NA NA JCbot (1) (2) (3) (4) (5) (6) (7) Junction-to-case (bottom) thermal resistance (7) UNITS C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, JT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining JA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, JB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining JA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Spacer Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: TPS92075 3 TPS92075 SLUSB88B - DECEMBER 2012 - REVISED JANUARY 2014 www.ti.com RECOMMENDED OPERATING CONDITIONS (1) Unless otherwise noted, all voltages are with respect to GND, -40C < TJ = TA < 125C. MIN Supply input voltage range VCC 11 Operating junction temperature (1) TYP -40 MAX UNIT 18 V 125 C Operating Ratings are conditions under which operation of the device is specified and do not imply assured performance limits. For specified performance limits and associated test conditions, see the Electrical Characteristics table. ELECTRICAL CHARACTERISTICS Unless otherwise specified -40C TJ = TA 125C, VCC = 14 V, CVCC = 10 F CGATE = 2.2 nF PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY VOLTAGE INPUT (VCC) IQ VCC quiescent current Not switching 1.3 2.5 mA IQ_SD VCC low power mode current VCC < VCC(UVLO) 120 250 A VVCC Input range VCC VCC(OVP) 18 V VCC(OVP) Overvoltage protection threshold VCC > VCC(OVP) 20.0 V VCC(UVLO) VCC UVLO threshold 10.5 V VCC(HYS) VCC UVLO hysteresis 18.0 VCC rising VCC falling 9.8 5.75 6.40 V 3.3 V ANGLE DEMODULATION ASNSTH-Hi Angle detect rising threshold 0.9 1.0 1.1 V ASNSTH-Low Angle detect falling threshold 0.465 0.500 0.540 V 1.14 OFF-TIME CONTROL VCOFF OFF capacitor threshold 1.20 1.285 V RCOFF OFF capacitor pull-down resistance 33 60 tOFF-max Maximum off-time 280 s GATE DRIVER OUTPUT (GATE) RGATE(H) Gate sourcing resistance 3 8 RGATE(L) Gate sinking resistance 3 8 500 555 mV CURRENT SENSE VISNS Average ISNS limit threshold VCL Current Limit 1.2 V Leading edge blanking 240 ns Current limit reset delay 280 s ISNS limit to GATE delay 33 ns OFF capacitor limit to GATE delay 33 ns tISNS tCOFF_DLY DAC: 63/127 445 THERMAL SHUTDOWN TSD Thermal limit threshold 160 C THYS Thermal limit hysteresis 20 C 4 Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: TPS92075 TPS92075 www.ti.com SLUSB88B - DECEMBER 2012 - REVISED JANUARY 2014 DEVICE INFORMATION FUNCTIONAL BLOCK DIAGRAM VCC VCC Regulator ASNS Filter Internal Regulator VCC OVP VCC UVLO DAC Logic Thermal Shutdown 0V to 1V (Analog) Standby PWM + ISNS ILIM + 240 ns Delay 1.2 V COFF GATE Control Logic + 1.2 V 280 Ps Max Offtimer GND TPS92075 UDG-12177 Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: TPS92075 5 TPS92075 SLUSB88B - DECEMBER 2012 - REVISED JANUARY 2014 www.ti.com SOIC (D) PACKAGE 8 PINS (TOP VIEW) GND 1 8 ASNS COFF 2 7 NC VCC 3 6 NC GATE 4 5 ISNS TSOT (DDC) PACKAGE 6 PINS (TOP VIEW) ASNS 1 6 COFF GND 2 5 VCC ISNS 3 4 GATE PIN DESCRIPTIONS PIN NUMBERS 6 NAME SIOC (D) TSOT (DDC) I/O ASNS 8 1 I The phase of the TRIAC is detected through this pin and is then fed to the digital decoder. Sensing thresholds are 1V rising and 0.5V falling - nominal. COFF 2 6 I Used to set the converter constant off-time. A current and capacitor connected from the output to this pin sets the constant off-time of the switching controller. GATE 4 4 O Power MOSFET driver pin. This output provides the gate drive for the power switching MOSFET. GND 1 2 -- Circuit ground connection ISNS 5 3 I VCC 3 5 -- DESCRIPTION LED current sense pin. Connect a resistor from main switching MOSFET source to GND to set the maximum switching cycle LED current. Connect ISNS to the switching FET source. Input voltage pin. This pin provides the power for the internal control circuitry and gate driver. VCC undervoltage lockout has been implemented with a wide range: 10V rising, 6V falling to ensure operation with start-up methods that allow elimination of the linear pass device. This includes using a coupled inductor with resistive start-up. Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: TPS92075 TPS92075 www.ti.com SLUSB88B - DECEMBER 2012 - REVISED JANUARY 2014 TYPICAL CHARACTERISTICS 1.1630 1400 1.1625 1200 VCC Input Current (A) COFF Voltage Threshold (V) Unless otherwise stated, -40C TA = TJ 125C, VCC = 14 V, CVCC = 10 F CGATE = 2.2 nF 1.1620 1.1615 1.1610 1.1605 1.1600 -40 -25 -10 800 600 400 200 5 20 35 50 65 Temperature (C) 80 95 0 110 125 0 2 4 6 8 10 12 14 VCC Input Voltage (V) 16 18 20 G000 Figure 2. VCC Input Current vs Vcc Input Voltage 6.48 9.82 6.46 UVLO Threshold (V) 9.84 9.80 9.78 9.76 9.74 6.44 6.42 6.40 6.38 9.72 9.70 -40 -25 -10 VCC Rising VCC Falling G000 Figure 1. COFF Threshold Voltage vs Temperature UVLO Threshold (V) 1000 5 20 35 50 65 Temperature (C) 80 95 110 125 6.36 -40 -25 -10 5 20 35 50 65 Temperature (C) G000 Figure 3. Input Voltage (UVLO Rising) vs Junction Temperature 80 95 110 125 G000 Figure 4. Input Voltage (UVLO Falling) vs Junction Temperature 50 45 Number of Devices 40 35 30 25 20 15 10 5 0. 47 <0 0 .4 0. to 0 70 47 .4 5 75 0 . to 0 48 .4 0 80 0 . to 0 48 .4 5 85 0 . to 0 49 .4 0 9 0 . to 0 0 49 . 4 5 0. to 95 50 0 0 .5 0. to 0 00 50 5 .5 0. to 05 51 0 0 .5 0. to 0 10 51 5 .515 to 0. 52 >0 0 .5 20 0 ISNS Mid-Scale Voltage Range (V) Figure 5. ISNS 0.5V Threshold Distribution Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: TPS92075 7 TPS92075 SLUSB88B - DECEMBER 2012 - REVISED JANUARY 2014 www.ti.com APPLICATION INFORMATION The TPS92075 is an AC-DC power factor correction (PFC) controller for phase-cut dimmer-compatible, LED lighting applications. A hysteretic, peak current, constant off-time approach implements the conversion. Rectified AC A A Vcc C3 C3 TPS92075 ASNS COFF GND VCC ISNS GATE D2 C8 D2 B B Buck-Boost Buck Q2 R7 UDG-12180 Figure 6. Simplified TPS92075 Schematic The TPS92075 controls the inductor current by controlling two features: (A) The peak inductor current, and (B) The cycle off-time. The following items summarize the basics of the switch operation in this hysteretic controller. * The main switch Q2 turns on and current ramps in the inductor. * The Q2 current flows through the sense resistor R7. The R7 voltage is compared to a reference voltage at ISNS. The Q2 on-time ends when the voltage on R7 is equal to a controlled reference voltage and the inductor current has reached its set peak current level for that switching cycle. * Q2 is turned off and a constant off-time timer begins. Voltage begins ramping on C8. * The next cycle begins when the voltage on C8 reaches 1.2 V. This ends the constant off-time and discharges C8. * Capacitor C3 eliminates most of the ripple current seen in the LEDs. iL (A) Peak Inductor Current 'iL-PP (B) tOFF tON (constant) Ts 0 Time UDG-12176 Figure 7. Current Regulation Method The TPS92075 incorporates a patent-pending control methodology to generate the reference for the conversion stage. The controlled reference used for the comparison of the ISNS signal may be DC or another shape depending on the mode of operation. Each mode controls the peak current level using a different methodology. 8 Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: TPS92075 TPS92075 www.ti.com SLUSB88B - DECEMBER 2012 - REVISED JANUARY 2014 Initial Start-Up The TPS92075 is designed to achieve instant turn-on using an external linear regulator circuit. The start-up sequence is internally controlled by a VCC under-voltage lockout (UVLO) circuit. Sufficient headroom has been incorporated to support the use of an auxiliary winding with start-up linear, resistive or coupled capacitor start-up methods. VCC Bias Supply The TPS92075 can be configured to use a linear regulator with or without the use of an auxiliary winding. Using a linear regulator to provide VCC incurs more losses than an auxiliary winding, but has several advantages: * allows the use of inexpensive off-the-shelf inductors as the main magnetic * speeds start-up time under deep dimming conditions * can reduce the size of the required VCC capacitor * the extra current draw when dimming can improve dimming compatibility Another consideration when selecting a bias method involves the OVP configuration. Because the feature is enabled via the VCC pin, an auxiliary winding provides the simplest implementation of output over-voltage protection. A typical start-up sequence begins with VCC input voltage below the UVLO threshold and the device operating in low-power, shut-down mode. The VCC input voltage increases to the UVLO threshold of 9.8V typical. At this point all of the device features are enabled. The device loads the initial start-up value as the output reference and switching begins. The device operates until the VCC level falls below the VCC(UVLO) falling threshold. (6.4V typical) When VCC is below this threshold, the device enters low-power shut-down mode. Angle Sense Operation The ASNS (angle sense) pin is the only input to the digital controller. The time between the rising edge and the falling edge of the signal determines converter functions. The pin incorporates internal analog and digital filtering so that any transition that remains beyond the threshold for more than approximately 150 s will cause the device to record a change-of-state. V Signal at ASNS pin ASNS Internal Signal 1.0 9 0.5 ; tASNS1 tASNS2 TL UDG-12179 Figure 8. Angle Sense Operation Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: TPS92075 9 TPS92075 SLUSB88B - DECEMBER 2012 - REVISED JANUARY 2014 www.ti.com Controller Basic Operation and Modes The controller continuously monitors the line cycle period and the present conduction angle length to determine the state of operation and configure other control features. Control algorithms use a normalized line period of 256 samples from ASNS fall to ASNS fall and a normalized converter reference control of 127 levels over a range of 0V to 1V . The four main controller states are: * Start-up * Non-Dimming * Dimming * ASNS signal lost With the exception of start-up, the controller can enter any of the states at any time as conditions demand. The two primary modes of controlling the converter reference are: * DC mode * Ramp mode During active dimming, a DC control reference increases or decreases depending on the input AC duty cycle derived from the ASNS signal. The relationship follows the algorithm: (ASNS Length + Fixed Offset) = Output Set point. When the conduction angle is long enough, the converter reference is changed to a triangular ramp to achieve a high power factor. The ramp is generated gradually over several cycles ensuring the implementation is undetectable. The controller maintains the ramp between the rising and falling ASNS signals. The controller also sets DC reference levels during start-up and when the ASNS signal is lost. Active states in the controller and controlled ranges are shown in Table 1. Table 1. Control States and Controlled Reference Values MODE LINE DUTY CYCLE Start-up Any CONTROLLED REFERENCE VALUE (value / 127 ) X 1V = reference 50 > 70%, typical average 55 > 70%, typical ramp range 22 to 127 Dimming 70% 35 to 63 No ASNS Any 42 Non-Dimming Initial Start-up Line Synchronization When the device reaches the turn-on UVLO threshold, the output current reference resets to 0.393V (50/127) and switching begins. The controller samples the line for approximately 80 ms (t1 to t2 , Figure 9) to determine the line frequency and establish the present state of operation. After determining the line frequency, the controller uses the information to calibrate the internal oscillator. The controller supports line frequencies from 45Hz to 65Hz. After determining frequency and duty cycle, the controller enters the appropriate control state. 10 Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: TPS92075 TPS92075 www.ti.com SLUSB88B - DECEMBER 2012 - REVISED JANUARY 2014 VREC VASNS Controlled Reference VISNS(peak) VGATE Time t0 t1 t2 UDG-12168 Figure 9. Line Synchronization Non-Dimming Ramp Mode When the conduction angle is greater than 70%, the controller begins to create a triangular ramp that is synchronized to the line and is centered between rising and falling edges of the ASNS signal as shown in Figure 10. The triangular shape is much easier to generate than a sine wave while maintaining a high power factor and low THD. The edges of the ramp do not decrease completely to zero to ensure compatibility with TRIAC dimmers that can provide conduction angles approaching 100%. V Rectified AC ASNS Controlled Reference Internal Time UDG-12169 Figure 10. Controlled Reference Output, Non-dimming When changing between dimming mode and non-dimming mode, the ramp is created over 127 line cycles (see Figure 11) or approximately 1 second (t2 to t3 1 second). Because the output level before and after the change is very similar and the change very gradual, it is impossible for the user to perceive a change in output level. The ramp morphs from a DC level to a ramp using a method that further ensures transparency to the user. Ramp transition occurs during construction and deconstruction of the ramp and is reversed if the conduction angle changes sufficiently during the change process. A hysteresis in angle length is also built in to the change-toramp-mode and change-from-ramp-mode transition. Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: TPS92075 11 TPS92075 SLUSB88B - DECEMBER 2012 - REVISED JANUARY 2014 VREC ... VASNS ... VISNS(peak) ... www.ti.com Time t2 t3 UDG-12178 Figure 11. Transition Stages of the Controlled Reference Dimming Mode When the conduction angle is reduced below the 70% threshold the output is controlled with a DC reference level based on: (angle sense rise to fall length count) / 2 + 35, 63. The control level clamps at both the high and low end of the range to increase TRIAC dimmer compatibility. Rather than adding passive (heat generating) hold current or implementing other means to draw sufficient current from the TRIAC dimmer to maintain optimal operation, the TPS92075 implements a translation that shifts output demand higher, lower in the dimming range. The effect is that more current is drawn at low angles, eliminating the need for hold circuitry. A net reduction in light output occurs because of the energy transfer relation. As the phase-dimmer conduction decreases, the time during which the converter can provide output power during each cycle decreases, and a reduction in light output follows. Triac Asymmetry Balancing Triacs are two silicon-controlled rectifiers (SCRs) configured so that one device conducts current in the positive AC cycle and the other device conducts current in the negative AC cycle. It is common for the devices to have different trigger levels and this leads to differences in conduction angle for each of the positive and negative AC cycles. The amount of variation between each cycle varies greatly between dimmer brands, makes and models. In all single stage TRIAC compatible dimming solutions, the ability of the converter to provide output power depends on the length of the conduction time. If the output current demand remains constant during each cycle and if there is a difference in TRIAC conduction angles, the result is a difference in light output for each cycle. The TPS92075 incorporates a balancing algorithm to reduce the difference in LED current (and light output) between cycles that have a conduction angle difference greater than 20%. ILED Active Hold VRECT AC VISNS Pk Offset Figure 12. LED current variation, Constant Reference Figure 13. LED current variation, TPS92075 with Balancing When the difference in conduction becomes greater than 20%, the controller begins to adjust the controller reference line-cycle by line-cycle to balance the energy provided to the LEDs. In this example the difference in conduction angles is 800 s and flicker was visible with the constant reference (Figure 12). With the TPS92075 balancing feature the peaks in the LED current have been equalized and flicker cannot be seen (Figure 13). 12 Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: TPS92075 TPS92075 www.ti.com SLUSB88B - DECEMBER 2012 - REVISED JANUARY 2014 Lossless or 'Active' Hold When used in the buck configuration, the converter enters a drop-out condition each cycle as the input AC line drops below the LED stack voltage. When this occurs, a resonance in the input filter can be excited causing a ring in the input current at the end of the conduction cycle. This can lead to output flicker if not controlled. One method of eliminating this is to modify the control method to send the energy that would otherwise affect the ringing to the output. To do this, the controller increases the output set-point at the end of each cycle after the ASNS fall (< 0.5 V) signal is received. The increse in set point can be seen in Figure 14. ILED Active Hold VRECT AC VISNS Pk Offset Figure 14. TPS92075 Reference Control - Active Hold Another benefit of the active hold is that a low impedance path is created to the LED stack. This ensures the current demand is as high as possible for as long as possible before the converter fully enters drop-out. Active Hold, ASNS, and Buck-Boost Topology When using the converter in a buck-boost configuration attention must be given to the configuration of the ASNS signal to ensure there is some added delay in the signal crossing the 0.5V threshold. Because the converter can continue to provide energy to the output below the LED stack voltage, it is best to configure the ASNS signal to fall when the rectified AC signal is as close to zero as possible. Rectified AC R9 D4 ASNS D3 R2 C7 UDG-12171 Figure 15. Buck-Boost Angle Sense Circuit This can be implemented by adding an additional zener and capacitor on the ASNS pin. Capacitance between 2200 pF and 4700 pF provides a good balance between allowing the ASNS signal to fall below 0.5V and extending the ASNS time. The D4 zener allows the ASNS signal to be widened further. This component can be the same type of zener selected for the input voltage linear supply, in many prototyping examples a 15V zener diode is used. The buck-boost configuration tends to provide greater dimmer compatibility because of its ability to continue to draw power below the LED stack. This increases the time the converter can provide output current and increases the light output at a given dimmer setting. A higher light output for a given dimmer setting is an important control technique which increases the probability that the design will remain flicker-free over its lifetime and range of installations. This trade-off between dimming ratio, dimmer compatibility and component count make the components a desirable addition. Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: TPS92075 13 TPS92075 SLUSB88B - DECEMBER 2012 - REVISED JANUARY 2014 www.ti.com Loss of Angle Sense When using a dimmer that can control the phase angle to very short conduction times (< 250 s), the ASNS signal may become so narrow that the controller cannot determine its length. When this occurs the controller simply sets the reference to a default value 0.33V (42/127) and waits for the ASNS signal to return. A simplified version of the TPS92075 circuit can be implemented by grounding the ASNS signal if minimum component count and size are essential design criteria. In this configuration balancing, ramp mode and active hold are not implemented. The output is controlled with a default, static reference of 0.394V (50/127). If used in conjunction with an on-time clamp, good dimming and power factors (>0.9) can still be achieved. Thermal Shutdown The TPS92075 includes thermal shutdown protection. If the die temperature reaches approximately 160C the device stops switching (GATE pin low). When the die temperature cools to approximately 140C, the device resumes normal operation. If thermal fold back is desired at levels below the IC thermal shut down, application circuits have been created to implement this feature. The simplest of these is the addition of a thermistor in the off-time circuitry. Thermal Foldback To implement thermal foldback, adjust the resistance of an existing circuit resistor with the use of an NTC (negative temperature coefficient) thermistor. For example, a resistor combination creating a dominant effect when the thermistor reaches the desired temperature and resistance can be incorporated by paralleling a thermistor and another resistor with R10 (Figure 17). This circuit option creates a shorter on-time as the temperature increases, reducing the output current. The use of a thermistor in these types of circuit implementations is simple and saves costly added circuitry and additional device pins. Overvoltage Protection (OVP) The implementation of overvoltage protection is simple and built-in if using a two-coil magnetic (coupled inductor) to derive VCC. If the LED string is opened the auxiliary VCC rises and reaches the VCC(OVP) trip point. This action disables and grounds the gate pin, preventing the converter from switching. The converter remains disabled until VCC drops 0.5V after a 1 second time-out. If an inductor is used, implement other discrete circuits to disable the converter. Output Bulk Capacitor The required output bulk capacitor, CBULK, stores energy during the input voltage zero crossing interval and limits twice the line frequency ripple component flowing through the LEDs. Equation 1 describes the calculation of the of output capacitor value. PIN CBULK 4p fL RLED VLED ILED(ripple ) where * * * RLED is the dynamic resistance of LED string ILED(ripple) is the peak to peak LED ripple current and fL is line frequency (1) RLED is found by computing the difference in LED forward voltage divided by the difference in LED current for a given LED using the manufacturer's VF vs. IF curve. For a rough initial estimate a typical value of 0.25 per LED can be used. More detail can be found in Application Note 1656. In typical applications, the solution size becomes a limiting factor and dictates the maximum dimensions of the bulk capacitor. When selecting an electrolytic capacitor, manufacturer recommended de-rating factors should be applied based on the worst case capacitor ripple current, output voltage and operating temperature to achieve the desired operating lifetime. It should also be a consideration to provide a minimum load at the output of the driver to discharge the capacitor after the power is switched off or during LED open circuit failures. 14 Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: TPS92075 TPS92075 www.ti.com SLUSB88B - DECEMBER 2012 - REVISED JANUARY 2014 Design Guidelines This TPS92075 application design requires the selection of components for the power conversion stage and angle sensing. Output inductor, sense resistor and switching frequency are the key aspects of the power stage design. Another important consideration is the inclusion of an on-time clamp. The combination of the line voltage going to zero each cycle and the hysteretic control method can lead to large increases in current draw at the start and end of each cycle. The components required for the on-time clamp are very inexpensive and return results that make their inclusion a common choice for LED driver designers. This simplified design procedure assumes the use of an on-time clamp in the design. UDG-12183 iL(ave) Peak Inductor Current follows this Controlled Reference. Ipk(t) = VISNS(t)/RSENSE RSENSE adjusts the average, peak inductor current The Inductance (L) defines 'iL(P-P) uiL-PP = (VLED * toff ) L Rectified AC Inductor Current Ripple The average output current = the average peak 1/2 the peak to peak inductor ripple iL(ave)= iLave(pk) uiL(P-P) 2 iLave(pk) = VISNS(ave) RSENSE Time tON Time tOFF Figure 16. TPS92075 Output Current Control The mode of operation that determines average continuous output current is non-dimming, during which the reference is a triangular waveform. The device uses the controller reference every switching cycle to set the peak current through the main switch and sense resistor. The average value of this reference and the inductor ripple current can be used to calculate the average output current. Another consideration is the length of time the converter is providing power to the LEDs. A conversion factor (CF) that accounts for a lower level of power conversion at the ends of each cycle is used to provide a more accurate sense resistor value. The lower level of power conversion in these areas also helps to increase the power factor. For the RSENSE calculation use VISNS (ave) = 0.433V (55/127). The CF calculation involves computing the normalized time length of the angle sense pulse using a formula shown in Equation 3. Simplified design expressions are provided below. For a more comprehensive approach refer to the TPS92075 Design Spreadsheet. To calculate RSENSE, use Equation 2. ae o c V / ISNS ave ( ) / RSENSE = c CF c DiL(P-P ) / c ILED + / 2 e o (2) To calculate the conversion factor, use Equation 3. ae ae VLED c sin-1 c c 2V c RMS e CF = 1 - c 90 c c e o o / / / 3/ o / 2/ / o (3) To calculate inductance ripple, use Equation 4. t aeV o DiL(P-P ) = c LED OFF / L e o (4) To calculate the constant off-time, use Equation 5 Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: TPS92075 15 TPS92075 SLUSB88B - DECEMBER 2012 - REVISED JANUARY 2014 www.ti.com ae ae ae 1.2 ooo tOFF = c ln c - c - 1/ / / (-CTOFF RCOFF ) / c c e VVCC o o /o e e (5) To calculate the average switching frequency, use Equation 6. ae o 1 fSW = c / c tOFF + (tOFF CF ) / e o (6) On-Time Clamp The use of an on-time clamp (Figure 17) provides a soft-start and soft-stop action to the conversion each line cycle. It also adds a means to control the energy in these conversion areas to optimize dimming performance. For example, cutting the energy conversion in these areas in half maintains strong current pull through these critical TRIAC regions, but is not high enough to excite circuit resonances. TPS92075 ISNS GATE R10 R11 D5b D5a ISNS ISNS R8 C10 UDG-12172 Figure 17. On-time Clamp Circuitry The circuit uses the gate drive output to generate a ramp. The ramp increases at a rate to reach the current sense trip point at the desired maximum conduction time. The gate signal, resistor R10 and capacitor C10 create the ramp. Diode D5b resets the ramp for each switching cycle. Resistor R11 provides an impedance so this signal can override ISNS. In the regions at the start and end of a line cycle the current sense reference is controlled to 0.173V (22/127). To select an R-C to reach this point in the desired time use Equation 7. A good starting estimate for the maximum on-time clamp is ~tOFF/2 . For example, choosing 33 nF as the value of capacitor C10, and assuming VGATE VCC, R10 (Rton(max)) is calculated in Equation 7. tOFF R ton(max ) = e ae ae 0.173 o ou - 1/ / u -Cton(max ) 2 eln c - c c / ee e e VGATE o o uu (7) 16 Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: TPS92075 TPS92075 www.ti.com SLUSB88B - DECEMBER 2012 - REVISED JANUARY 2014 Angle Sense Circuitry and Minimum ASNS Signal Length If implementing a buck converter, select the divider so the falling 0.5V ASNS threshold is reached when the rectified AC voltage is at the LED stack voltage. For example, if the LED stack is 20V and the top resistor is 400 k, the bottom resistor should be 10.25 k to provide a falling ASNS signal at 0.5V when the rectified AC reaches 20V. A 20V ASNS falling signal will mean a 40V ASNS rising threshold because of the 2:1 hysteresis. This will provide an ASNS signal length of ~7.4 ms, adequate to activate the ramp mode when not connected to a dimmer. This buck configuration and ASNS divider will activate the hold feature each time the rectified AC reaches the LED stack voltage. This method is shown in Figure 18. Regardless of the ASNS connection method used, the divider must ensure an adequate angle sense length (tASNS > 5.9 ms) when non-dimming to activate the creation of the ramp if this is desired. For example, if a straight resistor divider (Figure 18) is implemented and the design LED stack is more than 42V, the ASNS conduction time may not be adequate to activate the use of the ramp reference. LED(+) LED(-) LED(-) ASNS ASNS ASNS UDG-12173 Figure 18. Angle Sense for Low Voltage Buck Applications UDG-12175 UDG-12174 Figure 19. Angle Sense for Buck Applications up to 65V Figure 20. Angle Sense for BuckBoost Applications For LED stack voltages between 3V and 65V, use an alternate method that senses from LED(-). Because LED(-) reaches ground each line cycle, the absolute ASNS comparison limits of 0.5V and 1V can be used, providing extra conduction time for the ASNS signal as shown in Figure 19. Beyond a ~65V LED stack, alternate ASNS methods utilizing a bridge tap can be used. For buck-boost applications, implement the circuit shown in Figure 20. A capacitor on the ASNS pin may be required, depending on operating conditions. EMI Filtering: AC versus DC side of the rectifier bridge The TPS92075 requires a minimal amount of EMI filtering to pass conducted and radiated emissions levels to comply with agency requirements. Applications have been tested with the filter on the AC or DC side of the diode bridge and have obtained passing results. The use of an R-C snubber to damp filter resonances and optimize TRIAC compatibility is strongly recommended. The EMI filter design involves optimizing several factors and design considerations, including: * the use of `X' versus non-X rated filter capacitors * the use of ceramic versus film capacitors * component rating requirements when on the AC or DC side of the diode bridge * filtering on the AC or DC side of the bridge and the effect on the TRIAC firing angle and dimming range * snubber time constant and position in the design schematic * filter design choices and audible noise Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: TPS92075 17 TPS92075 SLUSB88B - DECEMBER 2012 - REVISED JANUARY 2014 www.ti.com Application Circuits + TPS92075 ASNS COFF Triac Dimmer GND VCC ISNS GATE UDG-12181 Figure 21. TPS92075 Application Circuit for Buck Topology with AC Side Filter + TPS92075 ASNS COFF GND VCC ISNS GATE Triac Dimmer ISNS ISNS UDG-12182 Figure 22. TPS92075 Application Circuit for Buck-Boost Topology with DC Side Filter 18 Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: TPS92075 TPS92075 www.ti.com SLUSB88B - DECEMBER 2012 - REVISED JANUARY 2014 + TPS92075 ASNS COFF GND VCC ISNS GATE Triac Dimmer ISNS ISNS UDG-12184 Figure 23. TPS92075 Application Circuit for Buck-Boost with Resistive Start-up and AUX Supply Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: TPS92075 19 TPS92075 SLUSB88B - DECEMBER 2012 - REVISED JANUARY 2014 www.ti.com REVISION HISTORY Changes from Revision A (JANUARY 2013) to Revision B * Page Changed TSOT package availability status in FEATURES section ..................................................................................... 1 Changes from Original (DECEMBER 2012) to Revision A Page * Changed title of Figure 7 ...................................................................................................................................................... 8 * Changed Figure 17 to correct resistor position ................................................................................................................... 16 * Changed Figure 22 to correct resistor position ................................................................................................................... 18 * Changed Figure 23 to correct resistor position ................................................................................................................... 19 20 Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: TPS92075 PACKAGE OPTION ADDENDUM www.ti.com 28-Feb-2017 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) TPS92075D/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 T92075 TPS92075DDC/NOPB ACTIVE SOT-23-THIN DDC 6 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SN8B TPS92075DDCR/NOPB ACTIVE SOT-23-THIN DDC 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SN8B TPS92075DR/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 T92075 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 28-Feb-2017 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 3-Mar-2017 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) TPS92075DDC/NOPB SOT23-THIN DDC 6 1000 178.0 8.4 TPS92075DDCR/NOPB SOT23-THIN DDC 6 3000 178.0 TPS92075DR/NOPB SOIC D 8 2500 330.0 3.2 3.2 1.4 4.0 8.0 Q3 8.4 3.2 3.2 1.4 4.0 8.0 Q3 12.4 6.5 5.4 2.0 8.0 12.0 Q1 Pack Materials-Page 1 W Pin1 (mm) Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 3-Mar-2017 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS92075DDC/NOPB SOT-23-THIN DDC 6 1000 210.0 185.0 35.0 TPS92075DDCR/NOPB SOT-23-THIN DDC 6 3000 210.0 185.0 35.0 TPS92075DR/NOPB SOIC D 8 2500 367.0 367.0 35.0 Pack Materials-Page 2 PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] A .004 [0.1] C PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .150 [3.81] .189-.197 [4.81-5.00] NOTE 3 4X (0 -15 ) 4 5 B 8X .012-.020 [0.31-0.51] .010 [0.25] C A B .150-.157 [3.81-3.98] NOTE 4 .069 MAX [1.75] .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 [0.11-0.25] 0 -8 .016-.050 [0.41-1.27] DETAIL A (.041) [1.04] TYPICAL 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] 6X (.050 ) [1.27] SYMM 5 4 (R.002 ) TYP [0.05] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X METAL SOLDER MASK OPENING EXPOSED METAL .0028 MAX [0.07] ALL AROUND SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL .0028 MIN [0.07] ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] 6X (.050 ) [1.27] SYMM 5 4 (R.002 ) TYP [0.05] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. 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