3.3 V, ±15 kV ESD-Protected, Half- and
Full-Duplex, RS-485/RS-422 Transceivers
ADM3483E/ADM3486E/ADM3488E/ADM3490E/ADM3491E
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.
FEATURES
TIA/EIA RS-485/RS-422 compliant
±15 kV ESD protection on RS-485 input/output pins
Data rates
ADM3483E/ADM3488E: 250 kbps
ADM3486E: 2.5 Mbps
ADM3490E/ADM3491E: 12 Mbps
Half- and full-duplex options
Up to 32 nodes on the bus
Receiver open-circuit, fail-safe design
Low power shutdown current
(ADM3483E/ADM3486E/ADM3491E only)
Outputs high-Z when disabled or powered off
Common-mode input range: −7 V to +12 V
Thermal shutdown and short-circuit protection
Industry-standard 75176 pinout
8-lead and 14-lead narrow SOIC packages
APPLICATIONS
Power/energy metering
Telecommunications
EMI-sensitive systems
Industrial control
Local area networks
GENERAL DESCRIPTION
The ADM3483E/ADM3486E/ADM3488E/ADM3490E/
ADM3491E are 3.3 V, low power data transceivers with
±15 kV ESD protection suitable for full- and half-duplex
communication on multipoint bus transmission lines. They
are designed for balanced data transmission, and they
comply with TIA/EIA standards RS485 and RS-422. The
ADM3483E/ADM3486E are half-duplex transceivers that
share differential lines and have separate enable inputs for
the driver and receiver. The full-duplex ADM3488E/
ADM3490E/ADM3491E transceivers have dedicated
differential line driver outputs and receiver inputs. The
ADM3491E also features separate enable inputs for the
driver and receiver.
The devices have a 12 kΩ receiver input impedance,
which allows up to 32 transceivers on a bus. Because only
one driver should be enabled at any time, the output of a
disabled or powered-down driver is tristated to avoid
overloading the bus.
FUNCTIONAL BLOCK DIAGRAMS
ADM3483E/
ADM3486E
RO
RE
DE
DI
V
CC
A
B
GND
D
R
0
6284-001
Figure 1.
ADM3488E/
ADM3490E
RO
DI
V
CC
A
B
Z
Y
GND
R
D
0
6284-002
Figure 2.
ADM3491E
RO
RE
DE
DI
V
CC
A
B
Z
Y
GND
R
D
06284-003
Figure 3.
(continued on Page 3)
ADM3483E/ADM3486E/ADM3488E/ADM3490E/ADM3491E
Rev. A | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagrams............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 4
Driver Timing Specifications...................................................... 5
Receiver Timing Specifications .................................................. 6
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configurations and Function Descriptions ........................... 8
Test Circuits and Switching Characteristics.................................. 9
Typical Performance Characteristics ........................................... 11
Circuit Description......................................................................... 14
Devices with Receiver/Driver Enable—ADM3483E/
ADM3486E/ ADM3491E ........................................................... 14
Devices Without Receiver/Driver Enable― ADM3488E/
ADM3490E ................................................................................. 14
Low Power Shutdown Mode—ADM3483E/ ADM3486E/
ADM3491E ................................................................................. 14
Driver Output Protection.......................................................... 14
Propagation Delay...................................................................... 14
Line Length vs. Data Rate ......................................................... 14
±15 kV ESD Protection ............................................................. 15
Human Body Model .................................................................. 15
Typical Applications................................................................... 15
Outline Dimensions ....................................................................... 18
Ordering Guide .......................................................................... 18
REVISION HISTORY
10/06—Rev. 0 to Rev. A
Added ADM3483E and ADM3488E ...............................Universal
Changes to Figure 1 and Figure 2................................................... 1
Inserted Table 3................................................................................. 5
Changes to Figure 4 and Figure 5................................................... 8
Inserted Figure 28 and Figure 29.................................................. 13
Changes to Figure 31 and Figure 32............................................. 16
Changes to Figure 34...................................................................... 17
Updated Outline Dimensions....................................................... 18
Changes to Ordering Guide .......................................................... 18
8/06—Revision 0: Initial Version
ADM3483E/ADM3486E/ADM3488E/ADM3490E/ADM3491E
Rev. A | Page 3 of 20
GENERAL DESCRIPTION
(continued from Page 1)
The driver outputs of the ADM3483E/ADM3486E/
ADM3488E are slew rate limited, in order to reduce EMI
and data errors caused by reflections from improperly
terminated buses. The receiver has a fail-safe feature that
ensures a logic high output when the inputs are floating.
Excessive power dissipation caused by bus contention
or by output shorting is prevented with a thermal shut-
down circuit.
The parts are fully specified over the industrial temperature range
and are available in 8-lead and 14-lead narrow SOIC packages.
Table 1. Selection Table
Part No.
Guaranteed Data
Rate (Mbps)
Supply
Voltage (V)
Half/Full
Duplex
Slew Rate
Limited
Driver/Receiver
Enable
±15 kV ESD Protection
on Bus Pins Pin Count
ADM3483E 0.25 3.0 to 3.6 Half Yes Yes Yes 8
ADM3486E 2.5 3.0 to 3.6 Half Yes Yes Yes 8
ADM3488E 0.25 3.0 to 3.6 Full Yes No Yes 8
ADM3490E 12 3.0 to 3.6 Full No No Yes 8
ADM3491E 12 3.0 to 3.6 Full No Yes Yes 14
ADM3483E/ADM3486E/ADM3488E/ADM3490E/ADM3491E
Rev. A | Page 4 of 20
SPECIFICATIONS
VCC = 3.3 V ± 0.3 V, TA = TMIN to TMAX, unless otherwise noted.
Table 2. ADM3483E/ADM3486E/ADM3488E/ADM3490E/ADM3491E
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DRIVER
Differential Outputs
Differential Output Voltage VOD 2.0 V RL = 100 Ω (RS-422) (see Figure 7)
1.5 V RL = 54 Ω (RS-485) (see Figure 7)
1.5 V RL = 60 Ω (RS-485) (see Figure 8)
Δ|VOD| for Complementary Output States1 ∆VOD 0.2 V RL = 54 Ω or 100 Ω (see Figure 7)
Common-Mode Output Voltage VOC 3 V RL = 54 Ω or 100 Ω (see Figure 7)
Δ|VOC| for Complementary Output States1 ∆VOC 0.2 V RL = 54 Ω or 100 Ω (see Figure 7)
Short-Circuit Output Current IOSD −250 mA VOUT = −7 V
250 mA VOUT = 12 V
Output Leakage (Y, Z) (ADM3491E Only) IO
Normal Mode 20 μA DE = 0 V, RE = 0 V, VCC = 0 V or 3.6 V,
VOUT = 12 V
−20 μA
DE = 0 V, RE = 0 V, VCC = 0 V or 3.6 V,
VOUT = −7 V
Shutdown Mode 1 μA DE = 0 V, RE = VCC, VCC = 0 V or 3.6 V,
VOUT = 12 V
−1 μA
DE = 0 V, RE = VCC, VCC = 0 V or 3.6 V,
VOUT = −7 V
Logic Inputs
Input High Voltage VIH 2.0 V
DE, DI, RE
Input Low Voltage VIL 0.8 V
DE, DI, RE
Logic Input Current IIN1 ±2 μA
DE, DI, RE
RECEIVER
Differential Inputs
Differential Input Threshold Voltage VTH −0.2 0.2 V −7 V < VCM < +12 V
Input Hysteresis ∆VTH 50 mV VCM = 0 V
Input Resistance (A, B) RIN 12
kΩ −7 V < VCM < +12 V
Input Current (A, B) IIN2 1.0 mA DE = 0 V, VCC = 0 V or 3.6 V, VIN = 12 V
−0.8 mA DE = 0 V, VCC = 0 V or 3.6 V, VIN = −7 V
RO Logic Output
Output High Voltage VOH V
CC − 0.4 V IOUT = −1.5 mA, VID = 200 mV (see Figure 9)
Output Low Voltage VOL 0.4 V IOUT = 2.5 mA, VID = 200 mV (see Figure 9)
Short-Circuit Output Current IOSR ±8 ±60 mA 0 V < VRO < VCC
Tristate Output Leakage Current IOZR ±1 μA VCC = 3.6 V, 0 V < VOUT < VCC
POWER SUPPLY
Voltage Range VCC 3.0 3.6 V
Supply Current ICC 1.1 2.2 mA
No load, DI = 0 V or VCC, DE = VCC,
RE = 0 V or VCC
0.95 1.9 mA
No load, DI = 0 V or VCC, DE = 0 V,
RE = 0 V
Shutdown Current ISHDN 0.002 1 μA
DE = 0 V, RE = VCC, DI = 0 V or VCC
ESD PROTECTION
A, B, Y, Z Pins ±15 kV Human body model
All Pins Except A, B, Y, Z Pins ±4 kV Human body model
1 Δ|VOD| and Δ|VOC| are the changes in VOD and VOC, respectively, when DI input changes state.
ADM3483E/ADM3486E/ADM3488E/ADM3490E/ADM3491E
Rev. A | Page 5 of 20
DRIVER TIMING SPECIFICATIONS
VCC = 3.3 V, TA = 25°C.
Table 3. ADM3483E/ADM3488E
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
MAXIMUM DATA RATE 250 kbps
DIFFERENTIAL OUTPUT DELAY tDD 600 900 1400 ns RL = 60 Ω (see Figure 10)
DIFFERENTIAL OUTPUT TRANSITION TIME tTD 400 740 1200 ns RL = 60 Ω (see Figure 10)
PROPAGATION DELAY
From Low to High Level tPLH 700 930 1500 ns RL = 27 Ω (see Figure 11)
From High to Low Level tPHL 700 930 1500 ns RL = 27 Ω (see Figure 11)
|tPLH − tPHL| PROPAGATION DELAY SKEW1 t
PDS ±50 ns RL = 27 Ω (see Figure 11)
ENABLE/DISABLE TIMING (ADM3483E ONLY)
Enable Time to Low Level tPZL 900 1300 ns RL = 110 Ω (see Figure 13)
Enable Time to High Level tPZH 600 800 ns RL = 110 Ω (see Figure 12)
Disable Time from Low Level tPLZ 50 80 ns RL = 110 Ω (see Figure 13)
Disable Time from High Level tPHZ 50 80 ns RL = 110 Ω (see Figure 12)
Enable Time from Shutdown to Low Level tPSL 1.9 2.7 μs RL = 110 Ω (see Figure 13)
Enable Time from Shutdown to High Level tPSH 2.2 3.0 μs RL = 110 Ω (see Figure 12)
1 Measured on |tPLH (Y) − tPHL (Y)| and |tPLH (Z) − tPHL (Z)|.
VCC = 3.3 V, TA = 25°C.
Table 4. ADM3486E
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
MAXIMUM DATA RATE 2.5 Mbps
DIFFERENTIAL OUTPUT DELAY tDD 20 42 70 ns RL = 60 Ω (see Figure 10)
DIFFERENTIAL OUTPUT TRANSITION TIME tTD 15 28 60 ns RL = 60 Ω (see Figure 10)
PROPAGATION DELAY
From Low to High Level tPLH 20 42 75 ns RL = 27 Ω (see Figure 11)
From High to Low Level tPHL 20 42 75 ns RL = 27 Ω (see Figure 11)
|tPLH − tPHL| PROPAGATION DELAY SKEW1tPDS −6 ±12 ns RL = 27 Ω (see Figure 11)
ENABLE/DISABLE TIMING
Enable Time to Low Level tPZL 52 100 ns RL = 110 Ω (see Figure 13)
Enable Time to High Level tPZH 52 100 ns RL = 110 Ω (see Figure 12)
Disable Time from Low Level tPLZ 40 80 ns RL = 110 Ω (see Figure 13)
Disable Time from High Level tPHZ 40 80 ns RL = 110 Ω (see Figure 12)
Enable Time from Shutdown to Low Level tPSL 700 1000 ns RL = 110 Ω (see Figure 13)
Enable Time from Shutdown to High Level tPSH 700 1000 ns RL = 110 Ω (see Figure 12)
1 Measured on |tPLH (Y) − tPHL (Y)| and |tPLH (Z) − tPHL (Z)|.
ADM3483E/ADM3486E/ADM3488E/ADM3490E/ADM3491E
Rev. A | Page 6 of 20
VCC = 3.3 V, TA = 25°C.
Table 5. ADM3490E/ADM3491E
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
MAXIMUM DATA RATE 12 15 Mbps
DIFFERENTIAL OUTPUT DELAY tDD 1 22 35 ns RL = 60 Ω (see Figure 10)
DIFFERENTIAL OUTPUT TRANSITION TIME tTD 3 11 25 ns RL = 60 Ω (see Figure 10)
PROPAGATION DELAY
From Low to High Level tPLH 7 23 35 ns RL = 27 Ω (see Figure 11)
From High to Low Level tPHL 7 23 35 ns RL = 27 Ω (see Figure 11)
|tPLH − tPHL| PROPAGATION DELAY SKEW1 t
PDS −1.4 ±8 ns RL = 27 Ω (see Figure 11)
ENABLE/DISABLE TIMING (ADM3491E ONLY)
Enable Time to Low Level tPZL 42 90 ns RL = 110 Ω (see Figure 13)
Enable Time to High Level tPZH 42 90 ns RL = 110 Ω (see Figure 12)
Disable Time from Low Level tPLZ 35 80 ns RL = 110 Ω (see Figure 13)
Disable Time from High Level tPHZ 35 80 ns RL = 110 Ω (see Figure 12)
Enable Time from Shutdown to Low Level tPSL 650 900 ns RL = 110 Ω (see Figure 13)
Enable Time from Shutdown to High Level tPSH 650 900 ns RL = 110 Ω (see Figure 12)
1 Measured on |tPLH (Y) − tPHL (Y)| and |tPLH (Z) − tPHL (Z)|.
RECEIVER TIMING SPECIFICATIONS
VCC = 3.3 V, TA = 25°C.
Table 6. ADM3483E/ADM3486E/ADM3488E/ADM3490E/ADM3491E
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
PROPAGATION DELAY
From Low to High Level tRPLH
ADM3486E/ADM3490E/ADM3491E 25 62 90 ns VID = 0 V to 3.0 V, CL = 15 pF (see Figure 14)
ADM3483E/ADM3488E 25 75 120 ns VID = 0 V to 3.0 V, CL = 15 pF (see Figure 14)
From High to Low Level tRPHL
ADM3486E/ADM3490E/ADM3491E 25 62 90 ns VID = 0 V to 3.0 V, CL = 15 pF (see Figure 14)
ADM3483E/ADM3488E 25 75 120 ns VID = 0 V to 3.0 V, CL = 15 pF (see Figure 14)
|tRPLH − tRPHL| PROPAGATION DELAY SKEW tRPDS
ADM3486E/ADM3490E/ADM3491E +6 ±10 ns VID = 0 V to 3.0 V, CL = 15 pF (see Figure 14)
ADM3483E/ADM3488E +12 ±20 ns VID = 0 V to 3.0 V, CL = 15 pF (see Figure 14)
ENABLE/DISABLE TIMING (ADM3483E/ADM3486E/
ADM3491E ONLY)
Enable Time to Low Level tRPZL 25 50 ns CL = 15 pF (see Figure 15)
Enable Time to High Level tRPZH 25 50 ns CL = 15 pF (see Figure 15)
Disable Time from Low Level tRPLZ 25 45 ns CL = 15 pF (see Figure 15)
Disable Time from High Level tRPHZ 25 45 ns CL = 15 pF (see Figure 15)
Enable Time from Shutdown to Low Level tRPSL 720 1400 ns CL = 15 pF (see Figure 15)
Enable Time from Shutdown to High Level tRPSH 720 1400 ns CL = 15 pF (see Figure 15)
Time to Shutdown1 t
SHDN 80 190 300 ns
1 The transceivers are put into shutdown mode by bringing the RE high and the DE low. If the inputs are in this state for less than 80 ns, the parts are guaranteed not to
enter shutdown. If the parts are in this state for 300 ns or more, the parts are guaranteed to enter shutdown.
ADM3483E/ADM3486E/ADM3488E/ADM3490E/ADM3491E
Rev. A | Page 7 of 20
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 7.
Parameter Rating
VCC to GND −0.3 V to +6 V
Digital Input/Output Voltage (DE, RE, DI) −0.3 V to +6 V
Receiver Output Voltage (RO) −0.3 V to (VCC + 0.3 V)
Driver Output (A, B, Y, Z)/Receiver Input
(A, B) Voltage −8 V to +13 V
Driver Output Current ±250 mA
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
θJA Thermal Impedance
8-Lead SOIC_N 158°C/W
14-Lead SOIC_N 120°C/W
Lead Temperature, Soldering (20 sec) 260°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ADM3483E/ADM3486E/ADM3488E/ADM3490E/ADM3491E
Rev. A | Page 8 of 20
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
RO
1
RE
2
DE
3
DI
4
V
CC
8
B
7
A
6
GND
5
ADM3483E/
ADM3486E
TOP VIEW
(Not to Scale)
06284-004
V
CC 1
RO
2
DI
3
GND
4
A
8
B
7
Z
6
Y
5
ADM3488E/
ADM3490E
TOP VIEW
(Not to Scale)
06284-005
NC
1
RO
2
RE
3
DE
4
V
CC
14
V
CC
13
A
12
B
11
DI
5
Z
10
GND
6
Y
9
GND
7
NC
NC = NO CONNECT
8
ADM3491E
TOP VIEW
(Not to Scale)
06284-006
Figure 4. ADM3483E/ADM3486E
Pin Configuration
Figure 5. ADM3488E/ADM3490E
Pin Configuration
Figure 6. ADM3491E
Pin Configuration
Table 8. Pin Function Descriptions
ADM3483E/
ADM3486E
Pin No.
ADM3488E/
ADM3490E
Pin No.
ADM3491E
Pin No. Mnemonic Description
1 2 2 RO
Receiver Output. If A > B by 200 mV, RO is high; if A < B by 200 mV,
RO is low.
2 N/A 3 RE Receiver Output Enable. A low level enables the receiver output. A high
level places it in a high impedance state. If RE is high and DE is low, the
device enters a low power shutdown mode.
3 N/A 4 DE
Driver Output Enable. A high level enables the driver differential A and B
outputs. A low level places it in a high impedance state. If RE is high and DE
is low, the device enters a low power shutdown mode.
4 3 5 DI
Driver Input. With a half-duplex part when the driver is enabled, a logic low
on DI forces A low and B high; a logic high on DI forces A high and B low.
With a full-duplex part when the driver is enabled, a logic low on DI forces Y
low and Z high; a logic high on DI forces Y high and Z low.
5 4 6, 7 GND Ground.
N/A 5 9 Y Noninverting Driver Output.
6 N/A N/A A Noninverting Receiver Input A and Noninverting Driver Output A.
N/A 8 12 A Noninverting Receiver Input A.
N/A 6 10 Z Inverting Driver Output.
7 N/A N/A B Inverting Receiver Input B and Inverting Driver Output B.
N/A 7 11 B Inverting Receiver Input B.
8 1 13, 14 VCC Power Supply, 3.3 V ± 0.3 V. Bypass VCC to GND with a 0.1 μF capacitor.
N/A N/A 1, 8 NC No Connect. Not internally connected. Can be connected to GND.
ADM3483E/ADM3486E/ADM3488E/ADM3490E/ADM3491E
Rev. A | Page 9 of 20
TEST CIRCUITS AND SWITCHING CHARACTERISTICS
V
OC
R
L
/2
R
L
/2
Z
Y
V
OD
06284-007
Figure 7. Driver Differential Output Voltage and
Common-Mode Output Voltage
R
L
375
375
V
OD
V
CM
=
–7V TO +12V
D
V
CC
06284-008
Figure 8. Driver Differential Output Voltage with
Varying Common-Mode Voltage
V
OH
I
OH
(–)
V
ID
R
0
I
OL
(+)
V
OL
06284-009
Figure 9. Receiver Output Voltage High and Output Voltage Low
IN
OUT
+1.5V +1.5V
+3V
0V
+2V
–2V
t
DD
t
DD
t
TD
t
TD
50%50%
10%10%
90%90%
D
GENERATOR
1
V
CC
50
C
L
R
L
=
60
C
L
= 15pF
2
OUT
1
PPR = 250kHz, 50% DUTY CYCLE,
t
R
6.0ns, Z
O
= 50.
2
C
L
INCLUDES PROBE AND STRAY CAPACITANCE.
06284-010
Figure 10. Driver Differential Output Delay and Transition Times
3V
0V
V
OH
V
OL
V
OH
V
OL
V
OM
V
OM
V
OM
V
OM
IN
Y
OUT
Z
OUT
1.5V 1.5V
t
PLH
t
PHL
t
PHL
t
PLH
D
V
OM
R
L
= 27
OUT
C
L
= 15pF
2
GENERATOR
1
V
CC
50
S1
V
OM
=
V
OH
+ V
OL
2
1.5V
1
PPR = 250kHz, 50% DUTY CYCLE,
t
R
6.0ns, Z
O
= 50.
2
C
L
INCLUDES PROBE AND STRAY CAPACITANCE.
06284-011
Figure 11. Driver Propagation Delays
DOUT
C
L
= 50pF
2
GENERATOR
1
50
S1
V
OM
=
V
OH
+ V
OL
2
1.5V
R
L
= 110
0V OR 3V
1
PPR = 250kHz, 50% DUTY CYCLE,
t
R
6.0ns, Z
O
= 50.
2
C
L
INCLUDES PROBE AND STRAY CAPACITANCE.
0V
V
OH
0V
3V
1.5V1.5V
0.25V
IN
OUT V
OM
t
PZH
t
PHZ
06284-012
Figure 12. Driver Enable and Disable Times (tPZH, tPSH, tPHZ)
ADM3483E/ADM3486E/ADM3488E/ADM3490E/ADM3491E
Rev. A | Page 10 of 20
V
OL
V
CC
0V
3V
0.25V
IN
OUT
1.5V 1.5V
t
PSL
t
PLZ
V
OM
DOUT
C
L
= 50pF
2
GENERATOR
1
50
S1
0V OR 3V
V
CC
R
L
= 110
1
PPR = 250kHz, 50% DUTY CYCLE,
t
R
6.0ns, Z
O
= 50.
2
C
L
INCLUDES PROBE AND STRAY CAPACITANCE.
06284-013
Figure 13. Driver Enable and Disable Times (tPZL, tPSL, tPLZ)
3V
0V
V
CC
0V
IN
OUT V
OM
V
OM
1.5V1.5V
t
RPHL
t
RPLH
GENERATOR
1
50C
L
= 15pF
2
R
1.5V
0V V
OM
=
V
CC
2
OUT
V
ID
1
PPR = 250kHz, 50% DUTY CYCLE,
t
R
6.0ns, Z
O
= 50.
2
C
L
INCLUDES PROBE AND STRAY CAPACITANCE.
06284-014
Figure 14. Receiver Propagation Delays
+3V
0V
V
OH
0V
S1 OPEN
S2 CLOSED
S3 = +1.5V
S1 CLOSED
S2 OPEN
S3 = –1.5V
S1 OPEN
S2 CLOSED
S3 = +1.5V
S1 CLOSED
S2 OPEN
S3 = –1.5V
+3V
0V
V
CC
V
OL
+3V
0V
V
CC
V
OL
+3V
0V
V
OH
0V
+1.5V
+1.5V
+1.5V
IN
OUT
IN
OUT
IN
OUT
IN
OUT
t
RPZL
t
RPSL
t
RPLZ
t
RPHZ
+0.25V
+0.25V
+1.5V
+1.5V
+1.5V
t
RPZH
t
RPSH
R
GENERATOR
1
50
C
L2
S3 S1
S2
V
CC
+1.5V
–1.5V V
ID
1k
1
PPR = 250kHz, 50% DUTY CYCLE,
t
R
6.0ns, Z
O
= 50.
2
C
L
INCLUDES PROBE AND STRAY CAPACITANCE.
06284-015
Figure 15. Receiver Enable and Disable Times
ADM3483E/ADM3486E/ADM3488E/ADM3490E/ADM3491E
Rev. A | Page 11 of 20
OUTPUT LOW VOLTAGE (V)
OUTPUT CURRENT (mA)
TYPICAL PERFORMANCE CHARACTERISTICS
25
0
03
.5
0.5 1.0 1.5 2.0 2.5 3.0
20
15
10
5
06284-021
Figure 16. Output Current vs. Receiver Output Low Voltage
–
18
0
03
.5
OUTPUT HIGH VOLTAGE (V)
OUTPUT CURRENT (mA)
0.5 1.0 1.5 2.0 2.5 3.0
–16
–14
–12
–10
–8
–6
–4
–2
06284-022
Figure 17. Output Current vs. Receiver Output High Voltage
TEMPERATURE (°C)
OUTPUT HIGH VOLTAGE (V)
3.00
3.05
3.10
3.15
3.20
3.25
3.30
–50 –25 0 25 50 75
IRO = –1.5mA
06284-023
Figure 18. Receiver Output High Voltage vs. Temperature
TEMPERATURE (°C)
OUTPUT LOW VOLTAGE (V)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
–40 10 60 85
I
RO
= 2.5mA
06284-024
100
0
03.5
DIFFERENTIAL OUTPUT VOLTAGE (V)
OUTPUT CURRENT (mA)
Figure 19. Receiver Output Low Voltage vs. Temperature
0.5 1.0 1.5 2.0 2.5 3.0
90
80
70
60
50
40
30
20
10
06284-025
Figure 20. Driver Output Current vs. Differential Output Voltage
2.6
1.6
–50
TEMPERATURE (°C)
DIFFERENTIAL OUTPUT VOLTAGE (V)
–25 0 25 50 75
2.5
2.4
2.3
2.2
2.1
2.0
1.9
1.8
1.7
R
L
= 54
06284-026
Figure 21. Driver Differential Output Voltage vs. Temperature
ADM3483E/ADM3486E/ADM3488E/ADM3490E/ADM3491E
Rev. A | Page 12 of 20
OUTPUT LOW VOLTAGE (V)
OUTPUT CURRENT (mA)
0
20
40
60
80
100
120
024681012
06284-027
Figure 22. Output Current vs. Driver Output Low Voltage
OUTPUT HIGH VOLTAGE (V)
OUTPUT CURRENT (mA)
0
20
40
60
80
100
120
–7–6–5–4–3–2–101234
06284-028
Figure 23. Output Current vs. Driver Output High Voltage
1.2
0.5
–40
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
–10 20 50 80
1.1
1.0
0.9
0.8
0.7
0.6
06284-029
Figure 24. Supply Current vs. Temperature
0.9
0
–50
TEMPERATURE (°C)
SHUTDOWN CURRENT (µA)
–25 0 25 50 75
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
06284-030
Figure 25. Shutdown Current vs. Temperature
CH1 1.0V CH2 1.0V IT 400ps/pt
CH3 2.0V M20ns 1.25GS/s
A CH3 1.44V
3
C
H1
C
H2
Y
Z
DI
06284-031
Figure 26. ADM3490E/ADM3491E Driver Propagation Delay
CH3 2.0V 4ns/pt
MATH1 2.01V 200ns
M200ns 250MS/s A CH2 1.24V
3
M1
V
A
– V
B
RO
06284-032
Figure 27. ADM3490E/ADM3491E Receiver Propagation Delay,
Driven by External RS-485 Device
ADM3483E/ADM3486E/ADM3488E/ADM3490E/ADM3491E
Rev. A | Page 13 of 20
06284-033
CH1 500mV CH2 500mV
CH3 5.0V
M2.0µs 25.0MS/s 40.0ns/pt
A CH3 2.4V
3
DI
Y
Z
Figure 28. ADM3483E/ADM3488E Driver Propagation Delay
06284-034
CH1 2.00V
MATH 2.00V 20.0ms
M20.0ms A CH1 40.0mV
1
M
V
A
– V
B
RO
Figure 29. ADM3483E/ADM3488E Receiver Propagation Delay
ADM3483E/ADM3486E/ADM3488E/ADM3490E/ADM3491E
Rev. A | Page 14 of 20
CIRCUIT DESCRIPTION
The ADM34xxE are low power transceivers for RS-485 and RS422
communications. The ADM3483E/ADM3488E operate at data
rates up to 250 kbps. The ADM3486E operates at data rates up
to 2.5 Mbps, and the ADM3490E/ADM3491E transmit at up to
12 Mbps. The ADM3488E/ADM3490E/ADM3491E are full-
duplex transceivers, and the ADM3483E/ADM3486E are half
duplex. Driver enable (DE) and receiver enable (RE) pins are
included on the ADM3483E/ADM3486E/ADM3491E. When
disabled, the driver and receiver outputs are high impedance.
DEVICES WITH RECEIVER/DRIVER ENABLE—
ADM3483E/ ADM3486E/ ADM3491E
Table 9. Transmitting Truth Table
Transmitting Inputs Transmitting Outputs
RE DE DI A1, Y2 B
1, Z2 Mode
X3 1 1 1 0 Normal
X3 1 0 0 1 Normal
0 0 X3 High-Z4 High-Z4 Normal
1 0 X3 High-Z4 High-Z4 Shutdown
1 ADM3483E and ADM3486E only.
2 ADM3491E only.
3 X = don’t care.
4 High-Z = high impedance.
Table 10. Receiving Truth Table
Receiving Inputs Receiving Output
RE DE1 DE2 A – B RO Mode
0 0 X3 ≥ +0.2 V 1 Normal
0 0 X3 ≤ −0.2 V 0 Normal
0 0 X3 Inputs open 1 Normal
1 0 X3 X
3 High-Z4 Shutdown
1 ADM3483E and ADM3486E only.
2 ADM3491E only.
3 X = don’t care.
4 High-Z = high impedance.
DEVICES WITHOUT RECEIVER/DRIVER ENABLE―
ADM3488E/ ADM3490E
Table 11. Transmitting Truth Table
Transmitting Input Transmitting Outputs
DI Z Y
1 0 1
0 1 0
Table 12. Receiving Truth Table
Receiving Input Receiving Output
A – B RO
≥ +0.2 V 1
≤ −0.2 V 0
Inputs open 1
LOW POWER SHUTDOWN MODE—ADM3483E/
ADM3486E/ ADM3491E
The ADM3483E/ADM3486E/ADM3491E are put into a low
power shutdown mode by bringing both RE high and DE low.
The devices do not shut down unless both the driver and the
receiver are disabled (high impedance). In shutdown mode, the
devices typically draw less than 1 μA of supply current. For
these devices, the tPSH and the tPSL enable times assume the part
was in the low power shutdown mode; the tPZH and the tPZL
enable times assume the receiver or the driver was disabled, but
the part was not shut down.
DRIVER OUTPUT PROTECTION
The ADM34xxE family implements two ways to prevent
excessive output current and power dissipation caused by faults
or by bus contention. A current limit on the output stage
provides immediate protection against short circuits over the
whole common-mode voltage range (see the Typical
Performance Characteristics section). In addition, a thermal
shutdown circuit forces the driver outputs into a high
impedance state if the die temperature rises excessively.
PROPAGATION DELAY
Figure 11, Figure 14, Figure 26, and Figure 27 show the typical
propagation delays. Skew time is simply the difference between
the low-to-high and the high-to-low propagation delays. Small
driver/receiver skew times help maintain a symmetrical mark-
space ratio (50% duty cycle).
The receiver skew time, |tPRHL – tPRHL|, is under 10 ns (20 ns for
the ADM3483E/ADM3488E). The driver skew time is 8 ns for
the ADM3490E/ADM3491E, 12 ns for the ADM3486E, and
typically under 50 ns for the ADM3483E/ADM3488E.
LINE LENGTH VS. DATA RATE
The RS-485/RS-422 standard covers line lengths up to 4000 feet.
For line lengths greater than 4000 feet, Figure 34 illustrates an
example of a line repeater.
ADM3483E/ADM3486E/ADM3488E/ADM3490E/ADM3491E
Rev. A | Page 15 of 20
±15 kV ESD PROTECTION
Two coupling methods are used for ESD testing: con-
tact discharge and air-gap discharge. Contact discharge
calls for a direct connection to the unit being tested. Air-
gap discharge uses a higher test voltage but does not make
direct contact with the test unit. With air-gap discharge,
the discharge gun is moved toward the unit under test,
developing an arc across the air gap, therefore the term air-
gap discharge. This method is influenced by humidity,
temperature, barometric pressure, distance, and rate of
closure of the discharge gun. The contact discharge
method, while less realistic, is more repeatable and is
gaining acceptance and preference over the air-
gap method.
Although very little energy is contained within an ESD pulse,
the extremely fast rise time, coupled with high voltages, can
cause failures in unprotected semiconductors. Catastrophic
destruction can occur immediately as a result of arcing or
heating. Even if catastrophic failure does not occur immediately,
the device can suffer from parametric degradation that can
result in degraded performance. The cumulative effects of
continuous exposure can eventually lead to complete failure.
Input/output lines are particularly vulnerable to ESD damage.
Simply touching or connecting an input/output cable can result
in a static discharge that can damage or completely destroy the
interface product connected to the input/output port. It is
extremely important, therefore, to have high levels of ESD
protection on the input/output lines.
The ESD discharge can induce latch-up in the device under test,
so it is important that ESD testing on the input/output pins be
carried out while device power is applied. This type of testing is
more representative of a real-world input/output discharge,
which occurs when the equipment is operating normally.
The transmitter outputs and receiver inputs of the ADM34xxE
family are characterized for protection to a ±15 kV limit using
the human body model.
HUMAN BODY MODEL
Figure 30 shows the human body model and the current wave-
form it generates when discharged into a low impedance. This
model consists of a 100 pF capacitor charged to the ESD voltage
of interest, which is then discharged into the test device
through a 1.5 kΩ resistor.
100%
90%
36.8
10%
t
RL
t
DL
IPEAK
TIME
t
R2
C1
R1
HIGH
VOLTAGE
GENERATOR DEVICE
UNDER
TEST
ESD TEST METHOD
HUMAN BODY MODEL
ESD ASSOC. STD 55.1
R2
1.5k
C1
100pF
06284-016
Figure 30. Human Body Model and Current Waveform
TYPICAL APPLICATIONS
The ADM3483E/ADM3486E/ADM3491E transceivers are
designed for bidirectional data communications on multipoint
bus transmission lines. The ADM3488E/ADM3490E full-duplex
transceiver is designed to be used in a daisy-chain network
topology or in a point-to-point application (see Figure 32). The
ADM3483E/ADM3486E are half-duplex RS-485 transceivers
that can be used in a multidrop bus configuration, as shown in
Figure 31. The ADM3488E/ADM3490E/ADM3491E can also
be used as a line repeater, for use with cable lengths longer than
4000 feet, as shown in Figure 34. To minimize reflections, the
line must be terminated at both ends in its characteristic
impedance, and stub lengths off the main line should be kept as
short as possible.
ADM3483E/ADM3486E/ADM3488E/ADM3490E/ADM3491E
Rev. A | Page 16 of 20
B
A
R
D
RO
DI
DE
ADM3483E/
ADM3486E
ADM3483E/
ADM3486E
ADM3483E/
ADM3486E
ADM3483E/
ADM3486E
B
AR
D
RO
DI
DE
B
A
R
D
RO RE DI
DE
B
A
R
D
RO RE DI
DE
R
T
R
T
NOTES
1. MAXIMUM NUMBER OF TRANSCEIVERS ON BUS: 32.
2. R
T
IS EQUAL TO THE CHARACTERISTIC IMPEDANCE OF THE CABLE USED.
RE RE
06284-017
Figure 31. ADM3483E/ADM3486E Typical Half-Duplex RS-485 Network
B
A
R
D
RO
DI RO
DI
Y
ZB
A
Y
Z
MASTE
R
R
D
SL
A
V
E
ADM3488E/
ADM3490E
ADM3488E/
ADM3490E
06284-018
Figure 32. ADM3488E/ADM3490E Full-Duplex Point-to-Point Applications
ADM3483E/ADM3486E/ADM3488E/ADM3490E/ADM3491E
Rev. A | Page 17 of 20
R
D
RO
DI
DE
ADM3491E
NOTES
1. MAXIMUM NUMBER OF NODES: 32.
2
.
R
T
IS EQUAL TO THE CHARACTERISTIC IMPEDANCE OF THE CABLE USED.
A
B
Y
Z
RO
R
T
R
T
R
D
RO DI
DE
ADM3491E
SLAVE AB Y
Z
R
DI
DE
ADM3491E
B
A
Z
Y
D
R
D
RO DI
DE
ADM3491E
SLAVE
MASTER SL
A
V
E
AB Y
Z
RERE
RE
RE
06284-019
Figure 33. ADM3491E Full-Duplex RS-485 Network
R
D
RO
RE
DI
DATA IN
DATA OUT
DE
ADM3488E/
ADM3490E/
ADM3491E
NOTES
1. R
T
IS EQUAL TO THE CHARACTERISTIC
IMPEDANCE OF THE CABLE USED.
2. RE AND DE PINS ON ADM3491E ONLY.
A
B
Y
Z
R
T
R
T
06284-020
Figure 34. Line Repeater for ADM3488E/ADM3490E/ADM3491E
ADM3483E/ADM3486E/ADM3488E/ADM3490E/ADM3491E
Rev. A | Page 18 of 20
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-A A
060506-A
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099) 45°
8°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
85
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2440)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
Figure 35. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AB
060606-A
14 8
7
1
6.20 (0.2441)
5.80 (0.2283)
4.00 (0.1575)
3.80 (0.1496)
8.75 (0.3445)
8.55 (0.3366)
1.27 (0.0500)
BSC
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0039)
0.51 (0.0201)
0.31 (0.0122)
1.75 (0.0689)
1.35 (0.0531)
0.50 (0.0197)
0.25 (0.0098)
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
COPLANARITY
0.10
8°
0°
45°
Figure 36. 14-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-14)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model
Temperature
Range Package Description Package Option Ordering Quantity
ADM3483EARZ1–40°C to +85°C 8-Lead Standard Small Outline Package (SOIC_N) R-8
ADM3483EARZ-REEL71–40°C to +85°C 8-Lead Standard Small Outline Package (SOIC_N) R-8 1,000
ADM3486EARZ1–40°C to +85°C 8-Lead Standard Small Outline Package (SOIC_N) R-8
ADM3486EARZ-REEL71–40°C to +85°C 8-Lead Standard Small Outline Package (SOIC_N) R-8 1,000
ADM3488EARZ1–40°C to +85°C 8-Lead Standard Small Outline Package (SOIC_N) R-8
ADM3488EARZ-REEL71–40°C to +85°C 8-Lead Standard Small Outline Package (SOIC_N) R-8 1,000
ADM3490EARZ1–40°C to +85°C 8-Lead Standard Small Outline Package (SOIC_N) R-8
ADM3490EARZ-REEL71–40°C to +85°C 8-Lead Standard Small Outline Package (SOIC_N) R-8 1,000
ADM3491EARZ1–40°C to +85°C 14-Lead Standard Small Outline Package (SOIC_N) R-14
ADM3491EARZ-REEL71–40°C to +85°C 14-Lead Standard Small Outline Package (SOIC_N) R-14 1,000
1 Z = Pb-free part.
ADM3483E/ADM3486E/ADM3488E/ADM3490E/ADM3491E
Rev. A | Page 19 of 20
NOTES
ADM3483E/ADM3486E/ADM3488E/ADM3490E/ADM3491E
Rev. A | Page 20 of 20
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06284-0-10/06(A)
NOTES