LP3996SD-2533/NOPB - Texas Instruments

LP3996

VIN

EN1

EN2

CBYP SET

POR

VOUT1

VOUT2

1 PF 1 PF

1 PF

VIN

EN1

EN2

VOUT1

VOUT2

POR

470 k:

GND

10 nF

Sets delay

for POR

LP3996

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SNVS360D –NOVEMBER 2006–REVISED OCTOBER 2013

LP3996 Dual Linear Regulator with 300 mA and 150 mA Outputs and Power-On-Reset

Check for Samples: LP3996

1FEATURES APPLICATIONS

2• 2 LDO Outputs with Independent Enable • Cellular Handsets

• 1.5% Accuracy at Room Temperature, 3% Over • PDAs

Temperature • Wireless Network Adaptors

• Power-On-Reset Function with Adjustable

Delay DESCRIPTION

The LP3996 is a dual low dropout regulator with

• Thermal Shutdown Protection power-on-reset circuit. The first regulator can source

• Stable with Ceramic Capacitors 150 mA, while the second is capable of sourcing 300

mA and has a power-on-reset function included.

KEY SPECIFICATIONS The LP3996 provides 1.5% accuracy requiring an

• Input Voltage Range 2.0V to 6.0V ultra low quiescent current of 35 µA. Separate enable

• Low Dropout Voltage 210 mV at 300 mA pins allow each output of the LP3996 to be shut

down, drawing virtually zero current.

• Ultra-Low IQ(Enabled) 35 µA

• Virtually Zero IQ(Disabled) <10 nA The LP3996 is designed to be stable with small

footprint ceramic capacitors down to 1 µF. An

• Package Available in Lead-Free Option external capacitor may be used to set the POR delay

10-pin 3 mm x 3 mm time as required.

The LP3996 is available in fixed output voltages and

comes in a 10-pin, 3 mm x 3 mm package.

Typical Application Circuit

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

LDO1

LDO2

VREF

POR

VIN

EN1

EN2

CBYP

GND SET

POR

VOUT2

VOUT1

1 PA

LP3996

SNVS360D –NOVEMBER 2006–REVISED OCTOBER 2013

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Functional Block Diagram

Pin Functions

Pin No Symbol Name and Function

1 VIN Voltage Supply Input. Connect a 1 µF capacitor between this pin and GND.

2 EN1 Enable Input to Regulator 1. Active high input.

High = On. Low = OFF.

3 EN2 Enable Input to Regulator 2. Active high input.

High = On. Low = OFF.

4 CBYP Internal Voltage Reference Bypass. Connect a 10nF capacitor from this pin to GND to reduce output

noise and improve line transient and PSRR.

This pin may be left open.

5 SET Set Delay Input. Connect a capacitor between this pin and GND to set the POR delay time. If left open,

there will be no delay.

6 GND Common Ground pin. Connect externally to exposed pad.

7 N/C No Connection. Do not connect to any other pin.

8 POR Power-On Reset Output. Open drain output. Active low indicates under-voltage output on Regulator 2.

A pull-up resistor is required for correct operation.

9 VOUT2 Output of Regulator 2. 300 mA maximum current output. Connect a 1 µF capacitor between this pin

and GND.

10 VOUT1 Output of Regulator 1. 150 mA maximum current output. Connect a 1 µF capacitor between this pin

and GND.

Pad GND Common Ground. Connect to Pin 6.

Product Folder Links: LP3996

VIN

GND

EN1

POR

VOUT1

GND

N/C

Top View

78910

VOUT2

EN2 SET

CBYP

LP3996

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SNVS360D –NOVEMBER 2006–REVISED OCTOBER 2013

Connection Diagram

Figure 1. WSON-10 Package

See Package Number DSC0010A

Table 1. Additional Device Information (1)

VOUT1/VOUT2 (V) ORDER NUMBER

0.8/3.3 LP3996SD/X-0833/NOPB

1.0/1.8 LP3996SD/X-1018/NOPB

1.5/2.5 LP3996SD/X-1525/NOPB

1.8/3.3 LP3996SD/X-1833/NOPB

2.5/3.3 LP3996SD/X-2533/NOPB

2.8/2.8 LP3996SD/X-2828/NOPB

3.0/3.0 LP3996SD/X-3030/NOPB

3.0/3.3 LP3996SD/X-3033/NOPB

3.3/0.8 LP3996SD/X-3308/NOPB

3.3/3.3 LP3996SD/X-3333/NOPB

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

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LP3996

SNVS360D –NOVEMBER 2006–REVISED OCTOBER 2013

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ABSOLUTE MAXIMUM RATINGS(1)(2)

Input Voltage to GND –0.3V to 6.5V

VOUT1, VOUT2 EN1 and EN2 Voltage to GND –0.3V to (VIN + 0.3V) with 6.5V

(max)

POR to GND –0.3V to 6.5V

Junction Temperature (TJ-MAX) 150°C

Lead/Pad Temp(3) 235°C

Storage Temperature –65°C to 150°C

Continuous Power Dissipation Internally Limited(4)

Human Body Model 2.0kV

ESD Rating(5) Machine Model 200V

(1) All Voltages are with respect to the potential at the GND pin.

(2) Absolute Maximum Ratings are limits beyond which damage can occur. Recommended Operating Conditions are conditions under

which operation of the device is ensured. Recommended Operating Conditions do not imply ensured performance limits. For ensured

performance limits and associated test conditions, see the Electrical Characteristics tables.

(3) For detailed soldering specifications and information, please refer to Texas Instruments Application Note AN-1187, Leadless Leadframe

Package.

(4) Internal thermal shutdown circuitry protects the device from permanent damage.

(5) The human body model is 100 pF discharged through a 1.5 kΩresistor into each pin. The machine model is a 200 pF capacitor

discharged directly into each pin.

RECOMMENDED OPERATING CONDITIONS(1)(2)

Input Voltage 2.0V to 6.0V

EN1, EN2, POR Voltage 0 to (VIN + 0.3V) to 6.0V (max)

Junction Temperature –40°C to 125°C

Ambient Temperature TARange(3) –40°C to 85°C

(1) Absolute Maximum Ratings are limits beyond which damage can occur. Recommended Operating Conditions are conditions under

which operation of the device is ensured. Recommended Operating Conditions do not imply ensured performance limits. For ensured

performance limits and associated test conditions, see the Electrical Characteristics tables.

(2) All Voltages are with respect to the potential at the GND pin.

(3) The maximum ambient temperature (TA(max)) is dependant on the maximum operating junction temperature (TJ(max-op) = 125°C), the

maximum power dissipation of the device in the application (PD(max)), and the junction to ambient thermal resistance of the part/package

in the application (θJA), as given by the following equation: TA(max) = TJ(max-op) - (θJA × PD(max)).

THERMAL PROPERTIES(1)

Junction-To-Ambient Thermal Resistance(2)

θJA WSON-10 Package 55°C/W

(1) Absolute Maximum Ratings are limits beyond which damage can occur. Recommended Operating Conditions are conditions under

which operation of the device is ensured. Recommended Operating Conditions do not imply ensured performance limits. For ensured

performance limits and associated test conditions, see the Electrical Characteristics tables.

(2) Junction-to-ambient thermal resistance is dependant on the application and board layout. In applications where high maximum power

dissipation is possible; special care must be paid to thermal dissipation issues in board design.

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SNVS360D –NOVEMBER 2006–REVISED OCTOBER 2013

ELECTRICAL CHARACTERISTICS(1)(2)

Unless otherwise noted, VEN = 950 mV, VIN = VOUT + 1.0V, or 2.0V, whichever is higher, where VOUT is the higher of VOUT1 and

VOUT2. CIN = 1 µF, IOUT = 1 mA, COUT1 = COUT2 = 1.0 µF.

Typical values and limits appearing in normal type apply for TA= 25°C. Limits appearing in boldface type apply over the full

junction temperature range for operation, −40 to +125°C. LIMIT

SYMBOL PARAMETER CONDITIONS TYP UNITS

MIN MAX

VIN Input Voltage See(3) 2 6 V

ΔVOUT Output Voltage Tolerance IOUT = 1mA 1.5V < VOUT ≤3.3V –2.5 +2.5

–3.75 +3.75 %

VOUT ≤1.5V –2.75 +2.75

–4 +4

Line Regulation Error VIN = (VOUT(NOM) + 1.0V) to 6.0V 0.03 0.3 %/V

Load Regulation Error IOUT = 1 mA to 150 mA 85 155

(LDO 1) µV/mA

IOUT = 1 mA to 300 mA 26 85

(LDO 2)

VDO Dropout Voltage(4) IOUT = 1 mA to 150 mA 110 220

(LDO 1) mV

IOUT = 1 mA to 300 mA 210 550

(LDO 2)

IQQuiescent Current LDO 1 ON, LDO 2 ON 35 100

IOUT1= IOUT2 = 0 mA

LDO 1 ON, LDO 2 OFF 45 110

IOUT1 = 150 mA µA

LDO 1 OFF, LDO 2 ON 45 110

IOUT2 = 300 mA

LDO 1 ON, LDO 2 ON 70 170

IOUT1 = 150 mA, IOUT2 = 300 mA

VEN1 = VEN2 = 0.4V 0.5 10 nA

(1) All Voltages are with respect to the potential at the GND pin.

(2) Min and Max limits are specified by design, test or statistical analysis. Typical numbers are not ensured, but do represent the most likely

norm.

(3) VIN(MIN) = VOUT(NOM) +0.5V, or 2.0V, whichever is higher.

(4) Dropout voltage is voltage difference between input and output at which the output voltage drops to 100 mV below its nominal value.

This parameter only for output voltages above 2.0V

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ELECTRICAL CHARACTERISTICS(1)(2) (continued)

Unless otherwise noted, VEN = 950 mV, VIN = VOUT + 1.0V, or 2.0V, whichever is higher, where VOUT is the higher of VOUT1 and

VOUT2. CIN = 1 µF, IOUT = 1 mA, COUT1 = COUT2 = 1.0 µF.

Typical values and limits appearing in normal type apply for TA= 25°C. Limits appearing in boldface type apply over the full

junction temperature range for operation, −40 to +125°C. LIMIT

SYMBOL PARAMETER CONDITIONS TYP UNITS

MIN MAX

ISC Short Circuit Current Limit LDO 1 420 750 mA

LDO 2 550 840

IOUT Maximum Output Current LDO 1 150 mA

LDO 2 300

PSRR Power Supply Rejection Ratio(5) f = 1kHz, IOUT = LDO1 58

1mA to 150 mA LDO2 70

CBYP = 10 nF dB

f = 20 kHz, IOUT LDO1 45

= 1mA to 150

mA LDO2 60

CBYP = 10 nF

enOutput noise Voltage(5) BW = 10 Hz to VOUT = 0.8V 36

100kHz µVRMS

VOUT = 3.3V 75

CBYP = 10 nF

TSHUTDOWN Thermal Shutdown Temperature 160 °C

Hysteresis 20

Enable Control Characteristics

IEN Input Current at VEN1 or VEN2 VEN = 0.0V 0.005 0.1 µA

VEN = 6V 2 5

VIL Low Input Threshold at VEN1 or 0.4 V

VEN2

VIH High Input Threshold at VEN1 or 0.95 V

VEN2

POR Output Characteristics

VTH Low Threshold % 0f VOUT2 (NOM) Flag ON 88 %

High Threshold % 0f VOUT2 (NOM) Flag OFF 96

IPOR Leakage Current Flag OFF, VPOR = 6.5V 30 nA

VOL Flag Output Low Voltage ISINK = 250 µA 20 mV

Timing Characteristics

TON Turn On Time(5) To 95% Level 300 µs

CBYP = 10 nF

Transient Line Transient Response Trise = Tfall = 10 µs 20

Response |δVOUT|(5) δVIN = 1VCBYP = 10 nF

Load Transient Response Trise = Tfall = 1 LDO 1

|δVOUT|(5) µs IOUT = 1 mA to 150 175 mV

mA (pk - pk)

LDO 2

IOUT = 1 mA to 300 150

SET Input Characteristics

ISET SET Pin Current Source VSET = 0V 1.3 µA

VTH(SET) SET Pin Threshold Voltage POR = High 1.25 V

(5) This electrical specification is specified by design.

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VOUT

Load Rise Time = Fall =

VOUT ± tolerance

VIN

1 Ps

Load Step LDO1 = 1 mA to 150 mA

Load Step LDO2 = 1 mA to 300 mA

VOUT

VOUT(NOM) + 1V

trise = tfall =

VOUT ± tolerance

VIN

10 Ps Line Step = 1V

ILOAD(LDO1) = 150 mA

ILOAD(LDO2) = 300 mA

LP3996

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SNVS360D –NOVEMBER 2006–REVISED OCTOBER 2013

OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS LIMIT

SYMBOL PARAMETER CONDITIONS NOM UNITS

MIN MAX

COUT Output Capacitance Capacitance(1) 1.0 0.7 µF

ESR 5 500 mΩ

(1) The Capacitor tolerance should be 30% or better over temperature. The full operating conditions for the application should be

considered when selecting a suitable capacitor to ensure that the minimum value of capacitance is always met. Recommended

capacitor is X7R. However, depending on the application, X5R, Y5V and Z5U can also be used. (See Capacitor sections in

APPLICATION HINTS.)

Transient Test Conditions

Figure 2. PSRR Input Signal

Figure 3. Line Transient Input Test Signal

Figure 4. Load Transient Input Signal

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TYPICAL PERFORMANCE CHARACTERISTICS

Unless otherwise specified, CIN = 1.0 µF Ceramic, COUT1 = COUT2 = 1.0 µF Ceramic, CBYP = 10 nF, VIN = VOUT2(NOM) + 1.0V, TA

= 25°C, VOUT1(NOM) = 3.3V, VOUT2(NOM) = 3.3V, Enable pins are tied to VIN.

Output Voltage Change vs Temperature Ground Current vs Load Current, LDO1

Figure 5. Figure 6.

Ground Current vs Load Current, LDO2 Ground Current vs VIN. ILOAD = 1mA

Figure 7. Figure 8.

Dropout Voltage vs ILOAD, LDO1 Dropout Voltage vs ILOAD, LDO2

Figure 9. Figure 10.

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SNVS360D –NOVEMBER 2006–REVISED OCTOBER 2013

TYPICAL PERFORMANCE CHARACTERISTICS (continued)

Unless otherwise specified, CIN = 1.0 µF Ceramic, COUT1 = COUT2 = 1.0 µF Ceramic, CBYP = 10 nF, VIN = VOUT2(NOM) + 1.0V, TA

= 25°C, VOUT1(NOM) = 3.3V, VOUT2(NOM) = 3.3V, Enable pins are tied to VIN.

Short Circuit Current, LDO1 Short Circuit Current, LDO2

Figure 11. Figure 12.

Power Supply Rejection Ratio, LDO1 Power Supply Rejection Ratio, LDO2

Figure 13. Figure 14.

Enable Start-up Time, CBYP=0 Enable Start-up Time, CBYP=10nF

Figure 15. Figure 16.

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TYPICAL PERFORMANCE CHARACTERISTICS (continued)

Unless otherwise specified, CIN = 1.0 µF Ceramic, COUT1 = COUT2 = 1.0 µF Ceramic, CBYP = 10 nF, VIN = VOUT2(NOM) + 1.0V, TA

= 25°C, VOUT1(NOM) = 3.3V, VOUT2(NOM) = 3.3V, Enable pins are tied to VIN.

Line Transient, CBYP=10nF Line Transient, CBYP=0

Figure 17. Figure 18.

Load Transient, LDO1 Load Transient, LDO2

Figure 19. Figure 20.

Noise Density LDO1 Noise Density, LDO2

Figure 21. Figure 22.

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SNVS360D –NOVEMBER 2006–REVISED OCTOBER 2013

TYPICAL PERFORMANCE CHARACTERISTICS (continued)

Unless otherwise specified, CIN = 1.0 µF Ceramic, COUT1 = COUT2 = 1.0 µF Ceramic, CBYP = 10 nF, VIN = VOUT2(NOM) + 1.0V, TA

= 25°C, VOUT1(NOM) = 3.3V, VOUT2(NOM) = 3.3V, Enable pins are tied to VIN.

Power-on-Reset Start-up Operation Power-on-Reset Shutdown Operation

Figure 23. Figure 24.

POR Delay Time

Figure 25.

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LP3996

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APPLICATION HINTS

Operation Description

The LP3996 is a low quiescent current, power management IC, designed specifically for portable applications

requiring minimum board space and smallest components. The LP3996 contains two independently selectable

LDOs. The first is capable of sourcing 150 mA at outputs between 0.8V and 3.3V. The second can source 300

mA at an output voltage of 0.8V to 3.3V. In addition, LDO2 contains power good flag circuit, which monitors the

output voltage and indicates when it is within 8% of its nominal value. The flag will also act as a power-on-reset

signal and, by adding an external capacitor; a delay may be programmed for the POR output.

Input Capacitor

An input capacitor is required for stability. It is recommended that a 1.0 µF capacitor be connected between the

LP3996 input pin and ground (this capacitance value may be increased without limit).

This capacitor must be located a distance of not more than 1 cm from the input pin and returned to a clean

analogue ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input.

Important: Tantalum capacitors can suffer catastrophic failures due to surge current when connected to a low-

impedance source of power (like a battery or a very large capacitor). If a tantalum capacitor is used at the input,

it must be ensured by the manufacturer to have a surge current rating sufficient for the application.

There are no requirements for the ESR (Equivalent Series Resistance) on the input capacitor, but tolerance and

temperature coefficient must be considered when selecting the capacitor to ensure the capacitance will remain

approximately 1.0 µF over the entire operating temperature range.

Output Capacitor

The LP3996 is designed specifically to work with very small ceramic output capacitors. A 1.0 µF ceramic

capacitor (temperature types Z5U, Y5V or X7R) with ESR between 5 mΩto 500 mΩ, is suitable in the LP3996

application circuit.

For this device the output capacitor should be connected between the VOUT pin and ground.

It is also possible to use tantalum or film capacitors at the device output, COUT (or VOUT), but these are not as

attractive for reasons of size and cost (see Capacitor Characteristics).

The output capacitor must meet the requirement for the minimum value of capacitance and also have an ESR

value that is within the range 5 mΩto 500 mΩfor stability.

No-Load Stability

The LP3996 will remain stable and in regulation with no external load. This is an important consideration in some

circuits, for example CMOS RAM keep-alive applications.

Product Folder Links: LP3996

0 1.0 2.0

3.0

4.0

5.0

CAP VALUE (% OF NOM. 1 uF)

DC BIAS (V)

100%

80%

60%

40%_

20%

0402, 6.3V, X5R

0603, 10V, X5R

LP3996

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SNVS360D –NOVEMBER 2006–REVISED OCTOBER 2013

Capacitor Characteristics

The LP3996 is designed to work with ceramic capacitors on the output to take advantage of the benefits they

offer. For capacitance values in the range of 0.47 µF to 4.7 µF, ceramic capacitors are the smallest, least

expensive and have the lowest ESR values, thus making them best for eliminating high frequency noise. The

ESR of a typical 1.0 µF ceramic capacitor is in the range of 20 mΩto 40 mΩ, which easily meets the ESR

requirement for stability for the LP3996.

For both input and output capacitors, careful interpretation of the capacitor specification is required to ensure

correct device operation. The capacitor value can change greatly, depending on the operating conditions and

capacitor type.

In particular, the output capacitor selection should take account of all the capacitor parameters, to ensure that the

specification is met within the application. The capacitance can vary with DC bias conditions as well as

temperature and frequency of operation. Capacitor values will also show some decrease over time due to aging.

The capacitor parameters are also dependant on the particular case size, with smaller sizes giving poorer

performance figures in general. As an example, Figure 26 shows a typical graph comparing different capacitor

case sizes in a Capacitance vs. DC Bias plot. As shown in the graph, increasing the DC Bias condition can result

in the capacitance value falling below the minimum value given in the recommended capacitor specifications

table (0.7 µF in this case). Note that the graph shows the capacitance out of spec for the 0402 case size

capacitor at higher bias voltages. It is therefore recommended that the capacitor manufacturers’ specifications for

the nominal value capacitor are consulted for all conditions, as some capacitor sizes (that is, 0402) may not be

suitable in the actual application.

Figure 26. Graph Showing a Typical Variation in Capacitance vs DC Bias

The ceramic capacitor’s capacitance can vary with temperature. The capacitor type X7R, which operates over a

temperature range of –55°C to +125°C, will only vary the capacitance to within ±15%. The capacitor type X5R

has a similar tolerance over a reduced temperature range of –55°C to +85°C. Many large value ceramic

capacitors, larger than 1µF are manufactured with Z5U or Y5V temperature characteristics. Their capacitance

can drop by more than 50% as the temperature varies from 25°C to 85°C. Therefore X7R is recommended over

Z5U and Y5V in applications where the ambient temperature will change significantly above or below 25°C.

Tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more

expensive when comparing equivalent capacitance and voltage ratings in the 0.47 µF to 4.7 µF range.

Another important consideration is that tantalum capacitors have higher ESR values than equivalent size

ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within the

stable range, it would have to be larger in capacitance (which means bigger and more costly) than a ceramic

capacitor with the same ESR value. It should also be noted that the ESR of a typical tantalum will increase about

2:1 as the temperature goes from 25°C down to –40°C, so some guard band must be allowed.

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tDELAY = VTH(SET) X CSET

ISET

LP3996

SNVS360D –NOVEMBER 2006–REVISED OCTOBER 2013

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Enable Control

The LP3996 features active high enable pins for each regulator, EN1 and EN2, which turns the corresponding

LDO off when pulled low. The device outputs are enabled when the enable lines are set to high. When not

enabled the regulator output is off and the device typically consumes 2nA.

If the application does not require the Enable switching feature, one or both enable pins should be tied to VIN to

keep the regulator output permanently on.

To ensure proper operation, the signal source used to drive the enable inputs must be able to swing above and

below the specified turn-on / off voltage thresholds listed in the Electrical Characteristics section under VIL and

VIH.

Power-On-Reset

The POR pin is an open-drain output which will be set to Low whenever the output of LDO2 falls out of regulation

to approximately 90% of its nominal value. An external pull-up resistor, connected to VOUT or VIN, is required on

this pin. During start-up, or whenever a fault condition is removed, the POR flag will return to the High state after

the output reaches approximately 96% of its nominal value. By connecting a capacitor from the SET pin to GND,

a delay to the rising condition of the POR flag may be introduced. The delayed signal may then be used as a

Power-on -Reset for a microprocessor within the user's application.

The duration of the delay is determined by the time to charge the delay capacitor to a threshold voltage of 1.25V

at 1.2 µA from the SET pin as in the formula below.

(1)

A 0.1 µF capacitor will introduce a delay of approximately 100 ms.

Bypass Capacitor

The internal voltage reference circuit of the LP3996 is connected to the CBYP pin via a high value internal resistor.

An external capacitor, connected to this pin, forms a low-pass filter which reduces the noise level on both outputs

of the device. There is also some improvement in PSSR and line transient performance. Internal circuitry ensures

rapid charging of the CBYP capacitor during start-up. A 10 nF, high quality ceramic capacitor with either NPO or

COG dielectric is recommended due to their low leakage characteristics and low noise performance.

Safe Area of Operation

Due consideration should be given to operating conditions to avoid excessive thermal dissipation of the LP3996

or triggering its thermal shutdown circuit. When both outputs are enabled, the total power dissipation will be

PD(LDO1) + PD(LDO2) Where PD= (VIN - VOUT)xIOUT for each LDO.

In general, device options which have a large difference in output voltage will dissipate more power when both

outputs are enabled, due to the input voltage required for the higher output voltage LDO. In such cases,

especially at elevated ambient temperature, it may not be possible to operate both outputs at maximum current

at the same time.

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LP3996

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SNVS360D –NOVEMBER 2006–REVISED OCTOBER 2013

REVISION HISTORY

Changes from Revision B (March 2013) to Revision C Page

• Changed layout of National Data Sheet to TI format; ......................................................................................................... 14

Changes from Revision C (March 2013) to Revision D Page

• Added Additional Device Table back to datasheet ............................................................................................................... 3

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PACKAGE OPTION ADDENDUM

www.ti.com 23-Aug-2017

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LP3996SD-0833/NOPB ACTIVE WSON DSC 10 1000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 L167B

LP3996SD-1018/NOPB ACTIVE WSON DSC 10 1000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM L227B

LP3996SD-1525/NOPB ACTIVE WSON DSC 10 1000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 L168B

LP3996SD-1833/NOPB ACTIVE WSON DSC 10 1000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM L228B

LP3996SD-2533/NOPB ACTIVE WSON DSC 10 1000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM L229B

LP3996SD-3030/NOPB ACTIVE WSON DSC 10 1000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 L172B

LP3996SD-3033/NOPB ACTIVE WSON DSC 10 1000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 L170B

LP3996SD-3333/NOPB ACTIVE WSON DSC 10 1000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 L173B

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

PACKAGE OPTION ADDENDUM

www.ti.com 23-Aug-2017

Addendum-Page 2

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF LP3996 :

•Automotive: LP3996-Q1

NOTE: Qualified Version Definitions:

•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LP3996SD-0833/NOPB WSON DSC 10 1000 178.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1

LP3996SD-1018/NOPB WSON DSC 10 1000 178.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1

LP3996SD-1525/NOPB WSON DSC 10 1000 178.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1

LP3996SD-1833/NOPB WSON DSC 10 1000 178.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1

LP3996SD-2533/NOPB WSON DSC 10 1000 178.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1

LP3996SD-3030/NOPB WSON DSC 10 1000 178.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1

LP3996SD-3033/NOPB WSON DSC 10 1000 178.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1

LP3996SD-3333/NOPB WSON DSC 10 1000 178.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 24-Aug-2017

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LP3996SD-0833/NOPB WSON DSC 10 1000 210.0 185.0 35.0

LP3996SD-1018/NOPB WSON DSC 10 1000 210.0 185.0 35.0

LP3996SD-1525/NOPB WSON DSC 10 1000 210.0 185.0 35.0

LP3996SD-1833/NOPB WSON DSC 10 1000 210.0 185.0 35.0

LP3996SD-2533/NOPB WSON DSC 10 1000 210.0 185.0 35.0

LP3996SD-3030/NOPB WSON DSC 10 1000 210.0 185.0 35.0

LP3996SD-3033/NOPB WSON DSC 10 1000 210.0 185.0 35.0

LP3996SD-3333/NOPB WSON DSC 10 1000 210.0 185.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 24-Aug-2017

Pack Materials-Page 2

MECHANICAL DATA

DSC0010A

www.ti.com

SDA10A (Rev A)

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Mouser Electronics

Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

Texas Instruments:

LP3996SD-0833 LP3996SD-0833/NOPB LP3996SD-1018/NOPB LP3996SD-1525 LP3996SD-1525/NOPB

LP3996SD-1833/NOPB LP3996SD-2533/NOPB LP3996SD-2828 LP3996SD-2828/NOPB LP3996SD-2828EV

LP3996SD-3030 LP3996SD-3030/NOPB LP3996SD-3030EV LP3996SD-3033 LP3996SD-3033/NOPB LP3996SD-

3308 LP3996SD-3308/NOPB LP3996SD-3333 LP3996SD-3333/NOPB LP3996SD-3333EV LP3996SDX-0833

LP3996SDX-0833/NOPB LP3996SDX-1018/NOPB LP3996SDX-1525 LP3996SDX-1525/NOPB LP3996SDX-

1833/NOPB LP3996SDX-2533/NOPB LP3996SDX-2828 LP3996SDX-2828/NOPB LP3996SDX-3030 LP3996SDX-

3030/NOPB LP3996SDX-3033 LP3996SDX-3033/NOPB LP3996SDX-3308 LP3996SDX-3308/NOPB LP3996SDX-

3333 LP3996SDX-3333/NOPB