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NOT RECOMMNEDED FOR NEW DESIGN
Single-Channel: 6N137, HCPL2601, HCPL2611 Dual-Channel: HCPL2630, HCPL2631 — High Speed 10MBit/s Logic Gate Optocouplers
©2005 Fairchild Semiconductor Corporation www.fairchildsemi.com
6N137, HCPL2601, HCPL2611, HCPL2630, HCPL2631 Rev. 1.0.8
January 2011
Single-Channel: 6N137, HCPL2601, HCPL2611
Dual-Channel: HCPL2630, HCPL2631
High Speed 10MBit/s Logic Gate Optocouplers
Features
■
Very high speed – 10 MBit/s
■
Superior CMR – 10 kV/µs
■
Double working voltage-480V
■
Fan-out of 8 over -40°C to +85°C
■
Logic gate output
■
Strobable output
■
Wired OR-open collector
■
U.L. recognized (File # E90700)
Applications
■
Ground loop elimination
■
LSTTL to TTL, LSTTL or 5-volt CMOS
■
Line receiver, data transmission
■
Data multiplexing
■
Switching power supplies
■
Pulse transformer replacement
■
Computer-peripheral interface
Description
The 6N137, HCPL2601, HCPL2611 single-channel and
HCPL2630, HCPL2631 dual-channel optocouplers
consist of a 850 nm AlGaAS LED, optically coupled to a
very high speed integrated photo-detector logic gate with
a strobable output. This output features an open collec-
tor, thereby permitting wired OR outputs. The coupled
parameters are guaranteed over the temperature range
of -40°C to +85°C. A maximum input signal of 5mA will
provide a minimum output sink current of 13mA (fan out
of 8).
An internal noise shield provides superior common
mode rejection of typically 10kV/µs. The HCPL2601 and
HCPL2631 has a minimum CMR of 5kV/µs. The
HCPL2611 has a minimum CMR of 10kV/µs.
Schematics Package Outlines
8
1
8
1
8
1
A 0.1µF bypass capacitor must be connected between pins 8 and 5(1).
1
2
3
4 5
6
7
8
N/C
_
VCC
VE
VO
GND
+
N/C
VF
1
2
3
4 5
6
7
8
+
_
VF1
VCC
V01
V02
GND
VF2
_
+
HCPL2630
HCPL2631
6N137
HCPL2601
HCPL2611
Truth Table (Positive Logic)
Input Enable Output
H H L
L H H
H L H
L L H
H NC L
L NC H
NOT RECOMMNEDED FOR NEW DESIGN
©2005 Fairchild Semiconductor Corporation www.fairchildsemi.com
6N137, HCPL2601, HCPL2611, HCPL2630, HCPL2631 Rev. 1.0.8 2
Single-Channel: 6N137, HCPL2601, HCPL2611 Dual-Channel: HCPL2630, HCPL2631 — High Speed 10MBit/s Logic Gate Optocouplers
Absolute Maximum Ratings
(T
A
= 25°C unless otherwise specified)
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
*For peak soldering reflow, please refer to the Reflow Profile on page 11.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
*6.3mA is a guard banded value which allows for at least 20% CTR degradation. Initial input current threshold value
is 5.0mA or less.
Symbol Parameter Value Units
T
STG
Storage Temperature -55 to +125 °C
T
OPR
Operating Temperature -40 to +85 °C
T
SOL
Lead Solder Temperature (for wave soldering only)* 260 for 10 sec °C
EMITTER
I
F
DC/Average Forward Single Channel 50 mA
Input Current Dual Channel (Each Channel) 30
V
E
Enable Input Voltage Not to Exceed
V
CC
by more than 500mV
Single Channel 5.5 V
V
R
Reverse Input Voltage Each Channel 5.0 V
P
I
Power Dissipation Single Channel 100 mW
Dual Channel (Each Channel) 45
DETECTOR
V
CC
(1 minute max)
Supply Voltage 7.0 V
I
O
Output Current Single Channel 50 mA
Dual Channel (Each Channel) 50
V
O
Output Voltage Each Channel 7.0 V
P
O
Collector Output Single Channel 85 mW
Power Dissipation Dual Channel (Each Channel) 60
Symbol Parameter Min. Max. Units
I
FL
Input Current, Low Level 0 250 µA
I
FH
Input Current, High Level *6.3 15 mA
V
CC
Supply Voltage, Output 4.5 5.5 V
V
EL
Enable Voltage, Low Level 0 0.8 V
V
EH
Enable Voltage, High Level 2.0 V
CC
V
T
A
Low Level Supply Current -40 +85 °C
NFan Out (TTL load) 8
NOT RECOMMNEDED FOR NEW DESIGN
©2005 Fairchild Semiconductor Corporation www.fairchildsemi.com
6N137, HCPL2601, HCPL2611, HCPL2630, HCPL2631 Rev. 1.0.8 3
Single-Channel: 6N137, HCPL2601, HCPL2611 Dual-Channel: HCPL2630, HCPL2631 — High Speed 10MBit/s Logic Gate Optocouplers
Electrical Characteristics
(T
A
= 0 to 70°C unless otherwise specified)
Individual Component Characteristics
Switching Characteristics
(T
A
= -40°C to +85°C, V
CC
= 5V, I
F
= 7.5mA unless otherwise specified)
Symbol Parameter Test Conditions Min. Typ.* Max. Unit
EMITTER
V
F
Input Forward Voltage I
F
= 10mA 1.8 V
T
A
= 25°C 1.4 1.75
B
VR
Input Reverse Breakdown
Voltage
I
R
= 10µA 5.0 V
C
IN
Input Capacitance V
F
= 0, f = 1MHz 60 pF
∆
V
F
/
∆
T
A
Input Diode Temperature
Coefficient
I
F
= 10mA -1.4 mV/°C
DETECTOR
I
CCH
High Level Supply Current V
CC
= 5.5V, I
F
= 0mA,
V
E
= 0.5V
Single Channel 7 10 mA
Dual Channel 10 15
I
CCL
Low Level Supply Current Single Channel V
CC
= 5.5V,
I
F
= 10mA
913mA
Dual Channel V
E
= 0.5V 14 21
I
EL
Low Level Enable Current V
CC
= 5.5V, V
E
= 0.5V -0.8 -1.6 mA
I
EH
High Level Enable Current V
CC
= 5.5V, V
E
= 2.0V -0.6 -1.6 mA
V
EH
High Level Enable Voltage V
CC
= 5.5V, I
F
= 10mA 2.0 V
V
EL
Low Level Enable Voltage V
CC
= 5.5V, I
F
= 10mA
(3)
0.8 V
Symbol AC Characteristics Test Conditions Min. Typ.* Max. Unit
T
PLH
Propagation Delay
Time to Output HIGH
Level
R
L
= 350
Ω
,
C
L
= 15pF
(4)
(Fig. 12)
T
A
= 25°C 20 45 75 ns
100
T
PHL
Propagation Delay
Time to Output LOW
Level
T
A
= 25°C
(5)
25 45 75 ns
R
L
= 350
Ω
, C
L
= 15pF (Fig. 12) 100
|T
PHL
–T
PLH
|Pulse Width Distortion (R
L
= 350
Ω
, C
L
= 15pF (Fig. 12) 3 35 ns
t
r
Output Rise Time
(10–90%)
R
L
= 350
Ω
, C
L
= 15pF
(6)
(Fig. 12) 50 ns
t
f
Output Rise Time
(90–10%)
R
L
= 350
Ω
, C
L
= 15pF
(7)
(Fig. 12) 12 ns
t
ELH
Enable Propagation
Delay Time to Output
HIGH Level
I
F
= 7.5mA, V
EH
= 3.5V, R
L
= 350
Ω
, C
L
= 15pF
(8)
(Fig. 13)
20 ns
t
EHL
Enable Propagation
Delay Time to Output
LOW Level
I
F
= 7.5mA, V
EH
= 3.5V, RL = 350Ω, CL = 15pF(9)
(Fig. 13)
20 ns
|CMH| Common Mode
Transient Immunity
(at Output HIGH Level)
TA = 25°C, |VCM| = 50V
(Peak), IF = 0mA,
VOH (Min.) = 2.0V,
RL = 350Ω(10) (Fig. 14)
6N137, HCPL2630 10,000 V/µs
HCPL2601, HCPL2631 5000 10,000
|VCM| = 400V HCPL2611 10,000 15,000 V/µs
|CML| Common Mode
Transient Immunity
(at Output LOW Level)
RL = 350Ω, IF = 7.5mA,
VOL (Max.) = 0.8V,
TA = 25°C(11) (Fig. 14)
6N137, HCPL2630 10,000
HCPL2601, HCPL2631 5000 10,000
|VCM| = 400V HCPL2611 10,000 15,000
NOT RECOMMNEDED FOR NEW DESIGN
©2005 Fairchild Semiconductor Corporation www.fairchildsemi.com
6N137, HCPL2601, HCPL2611, HCPL2630, HCPL2631 Rev. 1.0.8 4
Single-Channel: 6N137, HCPL2601, HCPL2611 Dual-Channel: HCPL2630, HCPL2631 — High Speed 10MBit/s Logic Gate Optocouplers
Electrical Characteristics (Continued)
Transfer Characteristics (TA = -40 to +85°C unless otherwise specified)
Isolation Characteristics (TA = -40°C to +85°C unless otherwise specified.)
*All Typicals at VCC = 5V, TA = 25°C
Notes:
1. The VCC supply to each optoisolator must be bypassed by a 0.1µF capacitor or larger. This can be either a ceramic
or solid tantalum capacitor with good high frequency characteristic and should be connected as close as possible
to the package VCC and GND pins of each device.
2. Each channel.
3. Enable Input – No pull up resistor required as the device has an internal pull up resistor.
4. tPLH – Propagation delay is measured from the 3.75mA level on the HIGH to LOW transition of the input current
pulse to the 1.5 V level on the LOW to HIGH transition of the output voltage pulse.
5. tPHL – Propagation delay is measured from the 3.75mA level on the LOW to HIGH transition of the input current
pulse to the 1.5 V level on the HIGH to LOW transition of the output voltage pulse.
6. tr – Rise time is measured from the 90% to the 10% levels on the LOW to HIGH transition of the output pulse.
7. tf – Fall time is measured from the 10% to the 90% levels on the HIGH to LOW transition of the output pulse.
8. tELH – Enable input propagation delay is measured from the 1.5V level on the HIGH to LOW transition of the input
voltage pulse to the 1.5V level on the LOW to HIGH transition of the output voltage pulse.
9. tEHL – Enable input propagation delay is measured from the 1.5V level on the LOW to HIGH transition of the input
voltage pulse to the 1.5V level on the HIGH to LOW transition of the output voltage pulse.
10. CMH – The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the
HIGH state (i.e., VOUT > 2.0V). Measured in volts per microsecond (V/µs).
11. CML – The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the
LOW output state (i.e., VOUT < 0.8V). Measured in volts per microsecond (V/µs).
12. Device considered a two-terminal device: Pins 1, 2, 3 and 4 shorted together, and Pins 5, 6, 7 and 8 shorted
together.
Symbol DC Characteristics Test Conditions Min. Typ.* Max. Unit
IOH HIGH Level Output Current VCC = 5.5V, VO = 5.5V,
IF = 250µA, VE = 2.0V(2)
100 µA
VOL LOW Level Output Current VCC = 5.5V, IF = 5mA, VE = 2.0V,
ICL = 13mA(2)
.35 0.6 V
IFT Input Threshold Current VCC = 5.5V, VO = 0.6V, VE = 2.0V,
IOL = 13mA
3 5 mA
Symbol Characteristics Test Conditions Min. Typ.* Max. Unit
II-O Input-Output Insulation
Leakage Current
Relative humidity = 45%,
TA = 25°C, t = 5s,
VI-O = 3000 VDC(12)
1.0* µA
VISO Withstand Insulation Test
Voltage
RH < 50%, TA = 25°C,
II-O ≤ 2µA, t = 1 min.(12)
2500 VRMS
RI-O Resistance (Input to Output) VI-O = 500V(12) 1012 Ω
CI-O Capacitance (Input to Output) f = 1MHz(12) 0.6 pF
NOT RECOMMNEDED FOR NEW DESIGN
©2005 Fairchild Semiconductor Corporation www.fairchildsemi.com
6N137, HCPL2601, HCPL2611, HCPL2630, HCPL2631 Rev. 1.0.8 5
Single-Channel: 6N137, HCPL2601, HCPL2611 Dual-Channel: HCPL2630, HCPL2631 — High Speed 10MBit/s Logic Gate Optocouplers
Typical Performance Curves
Fig.1 Low Level Output Voltage vs. Ambient Temperature
TA – AMBIENT TEMPERATURE (°C)
TA – AMBIENT TEMPERATURE (°C)
TA – AMBIENT TEMPERATURE (°C)
-40 -20 0 20 40 60 80
V
OL
– LOW LEVEL OUTPUT VOLTAGE (V)
T
P
– PROPAGATION DELAY (ns)
I
F
– FORWARD CURRENT (mA)
I
OL
– LOW LEVEL OUTPUT CURRENT (mA)
V
O
– OUTPUT VOLTAGE (V)
I
F
– FORWARD CURRENT (mA)
I
F
- FORWARD CURRENT (mA)
IOL
= 16mA
Fig. 4 Low Level Output Current
vs. Ambient Temperature
-40 -20 0 20 40 60 80
-40 -20 0 20 40 60 80
IF
= 5mA
IF = 10mA
IF = 15mA
Fig. 5 Input Threshold Current
vs. Ambient Temperature
IFT – INPUT THRESHOLD CURRENT (mA)
RL = 350Ω
RL = 1kΩ
RL = 4kΩ
Fig. 6 Output Voltage vs. Input Forward Current
RL = 350Ω
RL = 1kΩ
RL = 4kΩ
IOL
= 6.4mA
IOL
= 9.6mA
IOL
= 12.8 mA
Conditions:
IF = 5 mA
VE = 2 V
VCC
= 5.5V
Conditions:
VCC
= 5.0 V
VO
= 0.6 V
Fig. 2 Input Diode Forward Voltage
vs. Forward Current
VF – FORWARD VOLTAGE (V)
0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6
Conditions:
VCC
= 5 V
VE = 2 V
VOL
= 0.6 V
Fig.3 Switching Time vs. Forward Current
5
0123456
791113 15
VCC = 5 V
RL = 1 kΩ(TPLH)
RL = 4 kΩ(TPLH)
RL = 350 Ω (TPLH)
RL = 1 kΩ
RL = 4 kΩ
RL = 350 kΩ
(TPHL)
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
1
2
3
4
0
20
40
60
80
100
120
20
25
30
35
40
45
50
0
1
2
3
4
5
6
0.001
0.01
0.1
1
10
16
30
NOT RECOMMNEDED FOR NEW DESIGN
©2005 Fairchild Semiconductor Corporation www.fairchildsemi.com
6N137, HCPL2601, HCPL2611, HCPL2630, HCPL2631 Rev. 1.0.8 6
Single-Channel: 6N137, HCPL2601, HCPL2611 Dual-Channel: HCPL2630, HCPL2631 — High Speed 10MBit/s Logic Gate Optocouplers
Typical Performance Curves (Continued)
Fig. 7 Pulse Width Distortion vs. Temperature
TA – TEMPERATURE (°C)
TA – TEMPERATURE (°C)
TA – TEMPERATURE (°C)
TA – TEMPERATURE (°C) TA – TEMPERATURE (°C)
-60 -40 -20 0 20 40 60 80 100
-60 -40 -20 0 20 40 60 80 100
-60 -40 -20 0 20 40 60 80 100
-60 -40 -20 0 20 40 60 80 100
-60 -40 -20 0 20 40 60 80 100
PWD – PULSE WIDTH DISTORTION (ns)
T
E
– ENABLE PROPAGATION DELAY (ns)
I
OH
– HIGH LEVEL OUTPUT CURRENT (µA)
T
P
– PROPAGATION DELAY (ns) Tr/Tf – RISE AND FALL TIME (ns)
RL = 4 kΩ
RL = 1 kΩ
RL = 350Ω
F
Conditions:
I = 7.5mA
VCC = 5A
Fig. 8 Rise and Fall Time vs. Temperature
LR = 4 kΩ(tr)
Conditions:
IF = 7.5 mA
VCC = 5 V
RL = 1 kΩ(tr)
RL = 350Ω (tr)
RL = 1 kΩ
RL = 4 kΩ(tf)
RL = 350Ω
Fig. 9 Enable Propagation Delay vs. Temperature
RL = 4 kΩ (TELH)
RL = 1 kΩ (TELH)
RL = 350Ω (TELH)
RL = 350Ω
RL = 1 kΩ
RL = 4 kΩ
(TEHL)
Fig. 10 Switching Time vs. Temperature
RL = 1 kΩ TPLH
RL = 350Ω TPLH
RL = 4 kΩ TPLH
RL = 1 kΩ
RL = 4 kΩ
RL = 350Ω
TPHL
Fig. 11 High Level Output Current
vs. Temperature
VCC = 5.5 V
Conditions:
VO = 5.5 V
VE = 2.0 V
IF = 250 µA
0
20
40
60
80
0
100
200
300
400
500
600
0
20
40
60
80
100
120
20
40
60
80
100
120
0
5
10
15
20
NOT RECOMMNEDED FOR NEW DESIGN
©2005 Fairchild Semiconductor Corporation www.fairchildsemi.com
6N137, HCPL2601, HCPL2611, HCPL2630, HCPL2631 Rev. 1.0.8 7
Single-Channel: 6N137, HCPL2601, HCPL2611 Dual-Channel: HCPL2630, HCPL2631 — High Speed 10MBit/s Logic Gate Optocouplers
Test Circuits
47
PHL
t
F
I = 7.5 mA
1.5 V
90%
10%
7.5 mA
+5V
1.5 V
3.0 V
1.5 V
3
2
1
4
8
7
6
5
4 5
Pulse
1
2
3
Generator
tr = 5ns
Z = 50Ω
O
8
7
6
+5V
GND
PLH
t
I = 3.75 mA
F
Output
O
(V )
Input
(I )
F
Output
(V )
O
f
t
r
t
CC
V
Output
(V )
O
L
R
C
L
(I )
Input
F
Monitor
O
Z = 50Ω
Pulse
Generator
tr = 5ns
(V )
E
Input
Monitor
GND
V
CC
O
(V )
Output
L
R
L
C
(V )
Output
O
Input
(V )
E
EHL
tt
ELH
bypass
.1 µf
bypass
.1 µf
Fig. 12 Test Circuit and Waveforms for tPLH, tPHL, trand tf
Fig. 13 Test Circuit tEHL and tELH
NOT RECOMMNEDED FOR NEW DESIGN
©2005 Fairchild Semiconductor Corporation www.fairchildsemi.com
6N137, HCPL2601, HCPL2611, HCPL2630, HCPL2631 Rev. 1.0.8 8
Single-Channel: 6N137, HCPL2601, HCPL2611 Dual-Channel: HCPL2630, HCPL2631 — High Speed 10MBit/s Logic Gate Optocouplers
Test Circuits (Continued)
+5V
Peak
3
2
1
4
8
7
6
5
GND
V
CC
O
(V )
Output
350Ω
V
CM
FF
V
A
B
Pulse Gen
I
F
CM
V
0V
O
V
5V Switching Pos. (A), I = 0
F
O
V (Max)
CM
0.5 V
O
V
Switching Pos. (B), I = 7
.5 mA
F
H
CM
L
V (Min)
O
bypass
.1 µf
Fig. 14 Test Circuit Common Mode Transient Immunity
NOT RECOMMNEDED FOR NEW DESIGN
©2005 Fairchild Semiconductor Corporation www.fairchildsemi.com
6N137, HCPL2601, HCPL2611, HCPL2630, HCPL2631 Rev. 1.0.8 9
Single-Channel: 6N137, HCPL2601, HCPL2611 Dual-Channel: HCPL2630, HCPL2631 — High Speed 10MBit/s Logic Gate Optocouplers
Ordering Information
Marking Information
Option Example Part Number Description
S 6N137S Surface Mount Lead Bend
SD 6N137SD Surface Mount; Tape and Reel
W 6N137W 0.4" Lead Spacing
V 6N137V VDE0884
WV 6N137WV VDE0884; 0.4” Lead Spacing
SV 6N137SV VDE0884; Surface Mount
SDV 6N137SDV VDE0884; Surface Mount; Tape and Reel
1
2
6
43 5
Definitions
1 Fairchild logo
2 Device number
3 VDE mark (Note: Only appears on parts ordered with VDE option –
See order entry table)
4 Two digit year code, e.g., ‘03’
5 Two digit work week ranging from ‘01’ to ‘53’
6 Assembly package code
2601
T1YYXXV
NOT RECOMMNEDED FOR NEW DESIGN
©2005 Fairchild Semiconductor Corporation www.fairchildsemi.com
6N137, HCPL2601, HCPL2611, HCPL2630, HCPL2631 Rev. 1.0.8 10
Single-Channel: 6N137, HCPL2601, HCPL2611 Dual-Channel: HCPL2630, HCPL2631 — High Speed 10MBit/s Logic Gate Optocouplers
Tape Specifications
Reflow Profile
4.0 ± 0.1
Ø1.55 ± 0.05
User Direction of Feed
4.0 ± 0.1
1.75 ± 0.10
7.5 ± 0.1
16.0 ± 0.3
12.0 ± 0.1
0.30 ± 0.05
13.2 ± 0.2
4.90 ± 0.20
0.1 MAX 10.30 ± 0.20
10.30 ± 0.20
Ø1.6 ± 0.1
• Peak reflow temperature: 225C (package surface temperature)
• Time of temperature higher than 183C for 60–150 seconds
• One time soldering reflow is recommended
215 C, 10–30 s
225 C peak
Time (Minute)
0
300
250
200
150
100
50
0
0.5 1 1.5 2 2.5 3 3.5 4 4.5
Temperature (°C)
Time above 183C, 60–150 sec
Ramp up = 3C/sec
NOT RECOMMNEDED FOR NEW DESIGN
NOT RECOMMNEDED FOR NEW DESIGN
NOT RECOMMNEDED FOR NEW DESIGN
NOT RECOMMNEDED FOR NEW DESIGN
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1
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