DATA SH EET
Product specification
Supersedes data of 1997 Feb 10
File under Integrated Circuits, IC02
1999 Jan 06
INTEGRATED CIRCUITS
TDA8763
10-bit high-speed low-power ADC
with internal reference regulator
1999 Jan 06 2
Philips Semiconductors Product specification
10-bit high-speed low-power ADC with
internal reference regulator TDA8763
FEATURES
•10-bit resolution
•Sampling rate up to 50 MHz
•DC sampling allowed
•One clock cycle conversion only
•High signal-to-noise ratio over a large analog input
frequency range (9.3 effective bits at 4.43 MHz
full-scale input at fclk = 40 MHz)
•No missing codes guaranteed
•In-Range (IR) CMOS output
•Levels TTL and CMOS compatible digital inputs
•3 to 5 V CMOS digital outputs
•Low-level AC clock input signal allowed
•Internal reference voltage regulator
•Power dissipation only 235 mW (typical)
•Low analog input capacitance, no buffer amplifier
required
•No sample-and-hold circuit required.
APPLICATIONS
High-speed analog-to-digital conversion for:
•Video data digitizing
•Radar pulse analysis
•Transient signal analysis
•High energy physics research
•Σ∆ modulators
•Medical imaging.
GENERAL DESCRIPTION
The TDA8763 is a 10-bit high-speed low-power
Analog-to-Digital Converter (ADC) for professional video
and other applications. It converts the analog input signal
into 10-bit binary-coded digital words at a maximum
sampling rate of 50 MHz. All digital inputs and outputs are
TTL and CMOS compatible, although a low-level sine
wave clock input signal is allowed.
The device includes an internal voltage reference
regulator. If the application requires that the reference is
driven via external sources the recommendation is to use
the TDA8763A.
ORDERING INFORMATION
TYPE
NUMBER PACKAGE SAMPLING
FREQUENCY (MHz)
NAME DESCRIPTION VERSION
TDA8763M/3 SSOP28 plastic shrink small outline package; 28 leads;
body width 5.3 mm
SOT341-1 30
TDA8763M/4 SSOP28 SOT341-1 40
TDA8763M/5 SSOP28 SOT341-1 50
1999 Jan 06 3
Philips Semiconductors Product specification
10-bit high-speed low-power ADC with
internal reference regulator TDA8763
QUICK REFERENCE DATA
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
VCCA analog supply voltage 4.75 5.0 5.25 V
VCCD digital supply voltage 4.75 5.0 5.25 V
VCCO output stages supply voltage 3.0 3.3 5.25 V
ICCA analog supply current −30 35 mA
ICCD digital supply current −16 21 mA
ICCO output stages supply current fclk = 40 MHz; ramp input −12mA
INL integral non-linearity fclk = 40 MHz; ramp input −±0.8 ±2.0 LSB
DNL differential non-linearity fclk = 40 MHz; ramp input −±0.5 ±0.9 LSB
fclk(max) maximum clock frequency
TDA8763M/3 30 −−MHz
TDA8763M/4 40 −−MHz
TDA8763M/5 50 −−MHz
Ptot total power dissipation fclk = 40 MHz; ramp input −235 305 mW
1999 Jan 06 4
Philips Semiconductors Product specification
10-bit high-speed low-power ADC with
internal reference regulator TDA8763
BLOCK DIAGRAM
Fig.1 Block diagram.
handbook, full pagewidth
12
DGND2
6
8
RLAD
7
9
VRB
VRM
VRT
VI
11
VCCD2
35
26
VCCA
21
22
23
24
20 D4
D5
D6
D7
D8
19
18
25
2
D3
D2
17 D1
16 D0
D9
IN-RANGE LATCH
CMOS
OUTPUTS
LATCHES
ANALOG -TO - DIGITAL
CONVERTER
CLOCK DRIVER
REFERENCE
VOLTAGE
REGULATOR
MBE553
CMOS OUTPUT
1
CLKDEC
10
OE
TC
TDA8763
13 VCCO
4
AGND
analog ground digital ground digital ground
27
DGND1
14
OGND
output ground
analog
voltage input data outputs
LSB
MSB
28 VCCD1
IR
output
1999 Jan 06 5
Philips Semiconductors Product specification
10-bit high-speed low-power ADC with
internal reference regulator TDA8763
PINNING
SYMBOL PIN DESCRIPTION
CLK 1 clock input
TC 2 two’s complement input (active LOW)
VCCA 3 analog supply voltage (+5 V)
AGND 4 analog ground
DEC 5 decoupling input
VRB 6 reference voltage BOTTOM input
VRM 7 reference voltage MIDDLE input
VI8 analog input voltage
VRT 9 reference voltage TOP input
OE 10 output enable input (CMOS level
input, active LOW)
VCCD2 11 digital supply voltage 2 (+5 V)
DGND2 12 digital ground 2
VCCO 13 supply voltage for output stages
(3 to 5 V)
OGND 14 output ground
n.c. 15 not connected
D0 16 data output; bit 0 (LSB)
D1 17 data output; bit 1
D2 18 data output; bit 2
D3 19 data output; bit 3
D4 20 data output; bit 4
D5 21 data output; bit 5
D6 22 data output; bit 6
D7 23 data output; bit 7
D8 24 data output; bit 8
D9 25 data output; bit 9 (MSB)
IR 26 in range data output
DGND1 27 digital ground 1
VCCD1 28 digital supply voltage 1 (+5 V) Fig.2 Pin configuration.
handbook, halfpage
1
2
3
4
5
6
7
8
9
10
11
12
13
28
27
26
25
24
23
22
21
20
19
18
17
16
1514
CLK
TC
CCA
AGND
DEC
RB
RM
I
RT
OE
CCD2
DGND2
CCO
OGND
CCD1
DGND1
IR
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
n.c.
V
V
V
V
V
V
V
V
TDA8763
MBE552
1999 Jan 06 6
Philips Semiconductors Product specification
10-bit high-speed low-power ADC with
internal reference regulator TDA8763
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
Note
1. The supply voltages VCCA, VCCD and VCCO may have any value between −0.3 V and +7.0 V provided that the supply
voltage differences ∆VCC are respected.
HANDLING
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.
THERMAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCCA analog supply voltage note 1 −0.3 +7.0 V
VCCD digital supply voltage note 1 −0.3 +7.0 V
VCCO output stages supply voltage note 1 −0.3 +7.0 V
∆VCC supply voltage difference
VCCA −VCCD −1.0 +1.0 V
VCCA −VCCO −1.0 +4.0 V
VCCD −VCCO −1.0 +4.0 V
VIinput voltage referenced to AGND −0.3 +7.0 V
Vi(sw)(p-p) AC input voltage for switching (peak-to-peak value) referenced to DGND −VCCD V
IOoutput current −10 mA
Tstg storage temperature −55 +150 °C
Tamb operating ambient temperature −40 +85 °C
Tjjunction temperature −150 °C
SYMBOL PARAMETER CONDITIONS VALUE UNIT
Rth(j-a) thermal resistance from junction to ambient in free air 110 K/W
1999 Jan 06 7
Philips Semiconductors Product specification
10-bit high-speed low-power ADC with
internal reference regulator TDA8763
CHARACTERISTICS
VCCA =V
3to V4= 4.75 to 5.25 V; VCCD =V
11 to V12 and V28 to V27 = 4.75 to 5.25 V; VCCO =V
13 to V14 = 3.0 to 5.25 V;
AGND and DGND shorted together; Tamb =0to+70°C; typical values measured at VCCA =V
CCD = 5 V and
VCCO = 3.3 V; CL= 15 pF and Tamb =25°C; unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supplies
VCCA analog supply voltage 4.75 5.0 5.25 V
VCCD1 digital supply voltage 1 4.75 5.0 5.25 V
VCCD2 digital supply voltage 2 4.75 5.0 5.25 V
VCCO output stages supply voltage 3.0 3.3 5.25 V
∆VCC supply voltage difference
VCCA −VCCD −0.20 −+0.20 V
VCCA −VCCO −0.20 −+2.25 V
VCCD −VCCO −0.20 −+2.25 V
ICCA analog supply current −30 35 mA
ICCD digital supply current −16 21 mA
ICCO output stages supply current fclk = 40 MHz; ramp input −12 mA
Inputs
CLOCK INPUT CLK (REFERENCED TO DGND); note 1
VIL LOW-level input voltage 0 −0.8 V
VIH HIGH-level input voltage 2 −VCCD V
IIL LOW-level input current Vclk = 0.8 V −10+1µA
I
IH HIGH-level input current Vclk =2V −210 µA
Z
iinput impedance fclk = 40 MHz −2−kΩ
Ciinput capacitance −2−pF
INPUTS OE AND TC (REFERENCED TO DGND); see Table 2
VIL LOW-level input voltage 0 −0.8 V
VIH HIGH-level input voltage 2 −VCCD V
IIL LOW-level input current VIL = 0.8 V −1−− µA
I
IH HIGH-level input current VIH =2V −−1µA
V
I
(ANALOG INPUT VOLTAGE REFERENCED TO AGND)
IIL LOW-level input current VI=V
RB = 1.3 V −0−µA
I
IH HIGH-level input current VI=V
RT = 3.67 V −35 −µA
Z
iinput impedance fi= 4.43 MHz −8−kΩ
Ciinput capacitance −5−pF
1999 Jan 06 8
Philips Semiconductors Product specification
10-bit high-speed low-power ADC with
internal reference regulator TDA8763
Reference voltages for the resistor ladder using the internal voltage regulator; see Table 1
VRB reference voltage BOTTOM 1.1 1.3 1.5 V
VRT reference voltage TOP 3.4 3.6 3.8 V
Vdiff differential reference voltage
VRT −VRB
2.25 2.3 2.35 V
Iref reference current −9.39 −mA
Rlad resistor ladder −245 −Ω
TCRlad temperature coefficient of the
resistor ladder −1860 −ppm
−456 −mΩ/K
Voffset(B) offset voltage BOTTOM note 2 −175 −mV
Voffset(T) offset voltage TOP note 2 −175 −mV
Vi(p-p) analog input voltage
(peak-to-peak value) note 3 1.90 1.95 2.00 V
Outputs
DIGITAL OUTPUTS D9 TO D0 AND IR (REFERENCED TO OGND)
VOL LOW-level output voltage IOL = 1 mA 0 −0.5 V
VOH HIGH-level output voltage IOH =−1mA V
CCO −0.5 −VCCO V
IOZ output current in 3-state mode 0.5V<V
o<V
CCO −20 −+20 µA
Switching characteristics
CLOCK INPUT CLK; see Fig.4; note 1
fclk(max) maximum clock frequency
TDA8763M/3 30 −− MHz
TDA8763M/4 40 −− MHz
TDA8763M/5 50 −− MHz
tCPH clock pulse width HIGH full effective bandwidth 8.5 −− ns
tCPL clock pulse width LOW full effective bandwidth 5.5 −− ns
Analog signal processing
LINEARITY
INL integral non-linearity fclk = 40 MHz; ramp input −±0.8 ±2.0 LSB
DNL differential non-linearity fclk = 40 MHz; ramp input −±0.5 ±0.9 LSB
Eoffset offset error middle code −±1−LSB
EGgain error (from device to device)
using internal reference voltage note 4 −±3−%
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
1999 Jan 06 9
Philips Semiconductors Product specification
10-bit high-speed low-power ADC with
internal reference regulator TDA8763
BANDWIDTH (fclk = 40 MHz)
B analog bandwidth full-scale sine wave;
note 5 −15 −MHz
75% full-scale sine wave;
note 5 −20 −MHz
small signal at mid-scale;
VI=±10 LSB at
code 512; note 5
−350 −MHz
tstLH analog input settling time
LOW-to-HIGH full-scale square wave;
see Fig.6; note 6 −1.5 3.0 ns
tstHL analog input settling time
HIGH-to-LOW full-scale square wave;
see Fig.6; note 6 −1.5 3.0 ns
HARMONICS (fclk =40MHZ); see Figs 7 and 8
Hfund(FS) fundamental harmonics
(full-scale) fi= 4.43 MHz −−0dB
H
all(FS) harmonics (full-scale);
all components fi= 4.43 MHz
second harmonics −−70 −63 dB
third harmonics −−72 −63 dB
THD total harmonic distortion fi= 4.43 MHz −−61 −dB
SIGNAL-TO-NOISE RATIO; see Figs 7 and 8; note 7
SNRFS signal-to-noise ratio (full-scale) without harmonics;
fclk = 40 MHz;
fi= 4.43 MHz
55 58 −dB
EFFECTIVE BITS; see Figs 7 and 8; note 7
EB effective bits TDA8763M/3;
fclk = 30 MHz
fi= 4.43 MHz −9.4 −bits
fi= 7.5 MHz −9.1 −bits
TDA8763M/4;
fclk = 40 MHz
fi= 4.43 MHz −9.3 −bits
fi= 7.5 MHz −9.0 −bits
fi= 10 MHz −8.9 −bits
fi= 15 MHz −8.1 −bits
TDA8763M/5;
fclk = 50 MHz
fi= 4.43 MHz −9.3 −bits
fi= 7.5 MHz −8.9 −bits
fi= 10 MHz −8.8 −bits
fi= 15 MHz −8.0 −bits
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
1999 Jan 06 10
Philips Semiconductors Product specification
10-bit high-speed low-power ADC with
internal reference regulator TDA8763
Notes
1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock
must not be less than 0.5 ns.
2. Analog input voltages producing code 0 up to and including code 1023:
a) Voffset(B) (voltage offset BOTTOM) is the difference between the analog input which produces data equal to 00
and the reference voltage BOTTOM (VRB) at Tamb =25°C.
b) Voffset(T) (voltage offset TOP) is the difference between reference voltage TOP (VRT) and the analog input which
produces data outputs equal to code 1023 at Tamb =25°C.
TWO-TONE; note 8
TTIR two-tone intermodulation
rejection fclk = 40 MHz −−69 −dB
BIT ERROR RATE
BER bit error rate fclk = 50 MHz;
fi= 4.43 MHz;
VI=±16 LSB at code 512
−10−13 −times/
sample
DIFFERENTIAL GAIN; note 9
Gdiff differential gain fclk = 40 MHz;
PAL modulated ramp −0.8 −%
DIFFERENTIAL PHASE; note 9
ϕdiff differential phase fclk = 40 MHz;
PAL modulated ramp −0.4 −deg
Timing (fclk = 40 MHz; CL= 15 pF); see Fig.4; note 10
tds sampling delay time −3−ns
thoutput hold time 4 −− ns
tdoutput delay time VCCO = 4.75 V −10 13 ns
VCCO = 3.15 V −12 15 ns
CLdigital output load capacitance −−15 pF
3-state output delay times; see Fig.5
tdZH enable HIGH −5.5 8.5 ns
tdZL enable LOW −12 15 ns
tdHZ disable HIGH −19 24 ns
tdLZ disable LOW −12 15 ns
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
1999 Jan 06 11
Philips Semiconductors Product specification
10-bit high-speed low-power ADC with
internal reference regulator TDA8763
3. In order to ensure the optimum linearity performance of such converter architecture the lower and upper extremities
of the converter reference resistor ladder (corresponding to output codes 0 and 1023 respectively) are connected to
pins VRB and VRT via offset resistors ROB and ROT as shown in Fig.3.
a) The current flowing into the resistor ladder is and the full-scale input range at the converter,
to cover code 0 to code 1023, is
b) Since RL, ROB and ROT have similar behaviour with respect to process and temperature variation, the ratio
will be kept reasonably constant from device to device. Consequently variation of the output
codes at a given input voltage depends mainly on the difference VRT −VRB and its variation with temperature and
supply voltage. When several ADCs are connected in parallel and fed with the same reference source, the
matching between each of them is then optimized.
4.
5. The analog bandwidth is defined as the maximum input sine wave frequency which can be applied to the device.
No glitches greater than 2 LSBs, neither any significant attenuation are observed in the reconstructed signal.
6. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale
input (square wave signal) in order to sample the signal and obtain correct output data.
7. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8 K acquisition points per equivalent
fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency
(NYQUIST frequency). Conversion to signal-to-noise ratio: SINAD = EB ×6.02 + 1.76 dB.
8. Intermodulation measured relative to either tone with analog input frequencies of 4.43 MHz and 4.53 MHz. The two
input signals have the same amplitude and the total amplitude of both signals provides full-scale to the converter.
9. Measurement carried out using video analyser VM700A, where the video analog signal is reconstructed through a
digital-to-analog converter.
10. Output data acquisition: the output data is available after the maximum delay time of td(max). For 50 MHz version it is
recommended to have the lowest possible output load.
ILVRT VRB
–
ROB RLROT
++
------------------------------------------
=
VIRLIL
×RL
ROB RLROT
++
------------------------------------------
== V(
RT
×VRB )–0.
˙848 V(RT VRB )–×=
RL
ROB RLROT
++
------------------------------------------
EGV1023 V0
–()V
ip p–()
–
V
ip p–()
------------------------------------------------------------ 100×=
Fig.3 Explanation of note 3.
handbook, halfpage
RLAD
ROT
VRT
VRM
VRB
ROB
code 1023
code 0
MGD281
IL
RL
1999 Jan 06 12
Philips Semiconductors Product specification
10-bit high-speed low-power ADC with
internal reference regulator TDA8763
Table 1 Output coding and input voltage (typical values; referenced to AGND)
Table 2 Mode selection
STEP Vi(p-p) IR BINARY OUTPUT BITS TWOS COMPLEMENT OUTPUT BITS
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
U/F <1.455 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0000000
0 1.455 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0000000
1 . 100000000011000000001
. . .....................
. . .....................
1022 . 111111111100111111110
1023 3.405 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1111111
O/F >3.405 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1111111
TC OE D9 to D0 IR
X 1 high impedance high impedance
0 0 active; two’s complement active
1 0 active; binary active
Fig.4 Timing diagram.
handbook, full pagewidth
ds
t
sample N + 1
sample N
CLK
MBG916
sample N + 2
0 V
50%
VCCO
0 V
50%
VCCO
V
l
DATA
D0 to D9
td
th
CPH
tCPL
t
DATA
N + 1
DATA
N
DATA
N - 1
DATA
N - 2
1999 Jan 06 13
Philips Semiconductors Product specification
10-bit high-speed low-power ADC with
internal reference regulator TDA8763
Fig.5 Timing diagram and test conditions of 3-state output delay time.
fOE = 100 kHz.
handbook, full pagewidth
MBE555 - 1
50%
50%
HIGH
LOW
dZH
t
dHZ
t
50%
HIGH
LOW
dZL
t
dLZ
t
10%
90%
output
data
VCCD
output
data
3.3 kΩ
15 pF
S1
VCCD
TDA8763
OE
OE
TEST
dLZ
t
dZL
t
dHZ
t
dZH
S1
CCD
V
CCD
V
DGND
DGND
t
Fig.6 Analog input settling-time diagram.
MBE566
50%
STLH
t
2 ns
code 0
code 1023
I
50%
0.5 ns
50%
2 ns
STHL
t
50%
0.5 ns
CLK
V
1999 Jan 06 14
Philips Semiconductors Product specification
10-bit high-speed low-power ADC with
internal reference regulator TDA8763
Fig.7 Typical Fast Fourier Transform (fclk = 40 MHz; fi= 4.43 MHz).
Effective bits: 9.42; THD = −71.8 dB.
Harmonic levels (dB): 2nd = −83.19; 3rd = −78.09; 4th = −78.72; 5th = −78.33; 6th = −77.55.
handbook, full pagewidth
0
−120
−140 0 2.50 5.00
MGD862
−40
−80
12.57.50 10.0 15.0 17.5 20.0
f (MHz)
−100
−20
−60
amplitude
(dB)
Fig.8 Typical Fast Fourier Transform (fclk = 50 MHz; fi= 10 MHz).
Effective bits: 8.91; THD = −62.96 dB.
Harmonic levels (dB): 2nd = −71.38; 3rd = −71.54; 4th = −74.14; 5th = −65.15; 6th = −77.16.
handbook, full pagewidth
0
−120
−140 0 2.50 5.00
MGD863
−40
−80
12.57.50 10.0 15.0 17.5 25.020.0 22.5f (MHz)
−100
−20
−60
amplitude
(dB)
1999 Jan 06 15
Philips Semiconductors Product specification
10-bit high-speed low-power ADC with
internal reference regulator TDA8763
INTERNAL PIN CONFIGURATIONS
Fig.9 CMOS data and in range outputs.
handbook, halfpage
MBG915
VCCO
OGND
D9 to D0
IR
Fig.10 Analog inputs.
handbook, halfpage
MGC040 - 1
AGND
VCCA
VI
Fig.11 OE and TC input.
handbook, halfpage
MBE557
VCCO
OGND
OE
TC
Fig.12 VRB, VRM and VRT.
handbook, halfpage
RLAD
MBE558 - 1
VRB
VRM
AGND
VRT
VCCA
REGULATOR
DEC
1999 Jan 06 16
Philips Semiconductors Product specification
10-bit high-speed low-power ADC with
internal reference regulator TDA8763
Fig.13 CLK input.
handbook, halfpage
1.5 V
VCCD
DGND
CLK
MBE559 - 1
1999 Jan 06 17
Philips Semiconductors Product specification
10-bit high-speed low-power ADC with
internal reference regulator TDA8763
APPLICATION INFORMATION
Fig.14 Application diagram.
The analog and digital supplies should be separated and well decoupled.
An application note is available and describes the design and the realization of a demonstration board that uses the version TDA8763M with an
application environment.
(1) VRB, VRM and VRT are decoupled to AGND.
(2) Pin 15 may be connected to DGND in order to prevent noise influence.
(3) Decoupling capacitor for supplies: must be placed close to the device.
handbook, full pagewidth
28
27
26
25
24
23
22
21
20
19
18
17
TDA8763
DGND1
D3
D4
D5
D6
D7
D8
D9
D2
D1
D0
n.c.(2)
1
2
3
4
5
6
7
8
9
10
11
12
CLK
AGND
DEC
VRB(1)
VCCA
VRT(1)
VRM(1)
VCCD2
DGND2
OGND
VCCO
VI
FCE167
16
15
13
14
1 nF
1 nF
100 nF
IR
OE
TC
VCCD1
AGND
4.7 nF
AGND
100 nF
100 nF
AGND
AGND
(3)
100 nF (3)
(3)
100 nF (3)
1999 Jan 06 18
Philips Semiconductors Product specification
10-bit high-speed low-power ADC with
internal reference regulator TDA8763
PACKAGE OUTLINE
UNIT A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC EIAJ
mm 0.21
0.05 1.80
1.65 0.38
0.25 0.20
0.09 10.4
10.0 5.4
5.2 0.65 1.25
7.9
7.6 0.9
0.7 1.1
0.7 8
0
o
o
0.13 0.10.2
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.
1.03
0.63
SOT341-1 MO-150AH 93-09-08
95-02-04
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
114
28 15
0.25
y
pin 1 index
0 2.5 5 mm
scale
SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm SOT341-1
A
max.
2.0
1999 Jan 06 19
Philips Semiconductors Product specification
10-bit high-speed low-power ADC with
internal reference regulator TDA8763
SOLDERING
Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our
“Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
•Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
•For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
•For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
1999 Jan 06 20
Philips Semiconductors Product specification
10-bit high-speed low-power ADC with
internal reference regulator TDA8763
Suitability of surface mount IC packages for wave and reflow soldering methods
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the
“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”
.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
DEFINITIONS
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
PACKAGE SOLDERING METHOD
WAVE REFLOW(1)
BGA, SQFP not suitable suitable
HLQFP, HSQFP, HSOP, HTSSOP, SMS not suitable(2) suitable
PLCC(3), SO, SOJ suitable suitable
LQFP, QFP, TQFP not recommended(3)(4) suitable
SSOP, TSSOP, VSO not recommended(5) suitable
Data sheet status
Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
1999 Jan 06 21
Philips Semiconductors Product specification
10-bit high-speed low-power ADC with
internal reference regulator TDA8763
NOTES
1999 Jan 06 22
Philips Semiconductors Product specification
10-bit high-speed low-power ADC with
internal reference regulator TDA8763
NOTES
1999 Jan 06 23
Philips Semiconductors Product specification
10-bit high-speed low-power ADC with
internal reference regulator TDA8763
NOTES
Internet: http://www.semiconductors.philips.com
Philips Semiconductors – a worldwide company
© Philips Electronics N.V. 1999 SCA61
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The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
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Printed in The Netherlands 545004/750/04/pp24 Date of release: 1999 Jan 06 Document order number: 9397 750 04692
