STM32F100x4 STM32F100x6 STM32F100x8 STM32F100xB Low & medium-density value line, advanced ARM-based 32-bit MCU with 16 to 128 KB Flash, 12 timers, ADC, DAC & 8 comm interfaces Features Core: ARM 32-bit CortexTM-M3 CPU - 24 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance - Single-cycle multiplication and hardware division Memories - 16 to 128 Kbytes of Flash memory - 4 to 8 Kbytes of SRAM Clock, reset and supply management - 2.0 to 3.6 V application supply and I/Os - POR, PDR and programmable voltage detector (PVD) - 4-to-24 MHz crystal oscillator - Internal 8 MHz factory-trimmed RC - Internal 40 kHz RC - PLL for CPU clock - 32 kHz oscillator for RTC with calibration Low power - Sleep, Stop and Standby modes - VBAT supply for RTC and backup registers Debug mode - Serial wire debug (SWD) and JTAG interfaces DMA - 7-channel DMA controller - Peripherals supported: timers, ADC, SPIs, I2Cs, USARTs and DACs 1 x 12-bit, 1.2 s A/D converter (up to 16 channels) - Conversion range: 0 to 3.6 V - Temperature sensor 2 x 12-bit D/A converters Up to 80 fast I/O ports - 37/51/80 I/Os, all mappable on 16 external interrupt vectors and almost all 5 V-tolerant April 2011 FBGA LQFP100 14 x 14 mm LQFP64 10 x 10 mm LQFP48 7 x 7 mm TFBGA64 (5 x 5 mm) Up to 12 timers - Up to three 16-bit timers, each with up to 4 IC/OC/PWM or pulse counter - 16-bit, 6-channel advanced-control timer: up to 6 channels for PWM output, dead time generation and emergency stop - One 16-bit timer, with 2 IC/OC, 1 OCN/PWM, dead-time generation and emergency stop - Two 16-bit timers, each with IC/OC/OCN/PWM, dead-time generation and emergency stop - 2 watchdog timers (Independent and Window) - SysTick timer: 24-bit downcounter - Two 16-bit basic timers to drive the DAC Up to 8 communications interfaces - Up to two I2C interfaces (SMBus/PMBus) - Up to 3 USARTs (ISO 7816 interface, LIN, IrDA capability, modem control) - Up to 2 SPIs (12 Mbit/s) - Consumer electronics control (CEC) interface CRC calculation unit, 96-bit unique ID ECOPACK(R) packages Table 1. Device summary Reference Part number STM32F100x4 STM32F100C4, STM32F100R4 STM32F100x6 STM32F100C6, STM32F100R6 STM32F100x8 STM32F100C8, STM32F100R8, STM32F100V8 STM32F100xB STM32F100CB, STM32F100RB, STM32F100VB Doc ID 16455 Rev 6 1/87 www.st.com 1 Contents STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2.1 ARM(R) CortexTM-M3 core with embedded Flash and SRAM . . . . . . . . . 14 2.2.2 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2.3 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 14 2.2.4 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2.5 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 14 2.2.6 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 15 2.2.7 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2.8 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2.9 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2.10 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2.11 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2.12 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2.13 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2.14 RTC (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . . 17 2.2.15 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2.16 IC bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2.17 Universal synchronous/asynchronous receiver transmitter (USART) . . 19 2.2.18 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2.19 HDMI (high-definition multimedia interface) consumer electronics control (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2.20 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2.21 Remap capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2.22 ADC (analog-to-digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2.23 DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.2.24 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.2.25 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 21 3 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2/87 Doc ID 16455 Rev 6 STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.1 6 Contents Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 34 5.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 34 5.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.3.6 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.3.7 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.3.8 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.3.9 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.3.10 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.3.11 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 54 5.3.12 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.3.13 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.3.14 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5.3.15 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.3.16 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.3.17 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.3.18 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 5.3.19 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.2.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.2.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . . 82 Doc ID 16455 Rev 6 3/87 Contents STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB 7 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 4/87 Doc ID 16455 Rev 6 STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 STM32F100xx features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 STM32F100xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 35 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Maximum current consumption in Run mode, code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Maximum current consumption in Run mode, code with data processing running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 STM32F100xxB maximum current consumption in Sleep mode, code running from Flash or RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 39 Typical current consumption in Run mode, code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Typical current consumption in Sleep mode, code running from Flash or RAM . . . . . . . . . 43 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 HSE 4-24 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 SCL frequency (fPCLK1= 24 MHz, VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 RAIN max for fADC = 12 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Doc ID 16455 Rev 6 5/87 List of tables Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. 6/87 STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 LQPF100 - 14 x 14 mm, 100-pin low-profile quad flat package mechanical data . . . . . . . 76 LQFP64 - 10 x 10 mm, 64-pin low-profile quad flat package mechanical data . . . . . . . . . 77 TFBGA64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package mechanical data. . . 78 LQFP48 - 7 x 7 mm, 48-pin low-profile quad flat package mechanical data . . . . . . . . . . . 80 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Doc ID 16455 Rev 6 STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. 39 Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. STM32F100xx value line block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 STM32F100xx value line LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 STM32F100xx value line LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 STM32F100xx value line LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 STM32F100xx value line TFBGA64 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Maximum current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals enabled. . . . . . . . . . . . . . . . . . 38 Maximum current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals disabled . . . . . . . . . . . . . . . . . 38 Typical current consumption on VBAT with RTC on vs. temperature at different VBAT values Typical current consumption in Stop mode with regulator in Run mode versus temperature at VDD = 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Typical current consumption in Stop mode with regulator in Low-power mode versus temperature at VDD = 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Typical current consumption in Standby mode versus temperature at VDD = 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Standard I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Standard I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5 V tolerant I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5 V tolerant I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 I2C bus AC waveforms and measurement circuit(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . . 71 Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . . 71 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 76 Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 LQFP64 - 10 x 10 mm, 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . 77 Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 TFBGA64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package outline . . . . . . . . . . 78 Recommended PCB design rules for pads (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . . . . 79 Doc ID 16455 Rev 6 7/87 List of figures Figure 43. Figure 44. Figure 45. 8/87 STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB LQFP48 - 7 x 7 mm, 48-pin low-profile quad flat package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 LQFP100 PD max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Doc ID 16455 Rev 6 STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB 1 Introduction Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32F100x4, STM32F100x6, STM32F100x8 and STM32F100xB value line microcontrollers. In the rest of the document, the STM32F100x4 and STM32F100x6 are referred to as low-density devices while the STM32F100x8 and STM32F100xB are identified as medium-density devices. The STM32F100xx datasheet should be read in conjunction with the low- and mediumdensity STM32F100xx reference manual. For information on programming, erasing and protection of the internal Flash memory please refer to the STM32F100xx Flash programming manual. The reference and Flash programming manuals are both available from the STMicroelectronics website www.st.com. For information on the CortexTM-M3 core please refer to the CortexTM-M3 Technical Reference Manual, available from the www.arm.com website at the following address: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/. Doc ID 16455 Rev 6 9/87 Description 2 STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB Description The STM32F100xx value line family incorporates the high-performance ARM CortexTM-M3 32-bit RISC core operating at a 24 MHz frequency, high-speed embedded memories (Flash memory up to 128 Kbytes and SRAM up to 8 Kbytes), and an extensive range of enhanced peripherals and I/Os connected to two APB buses. All devices offer standard communication interfaces (up to two I2Cs, two SPIs, one HDMI CEC, and up to three USARTs), one 12-bit ADC, two 12-bit DACs, up to six general-purpose 16-bit timers and an advanced-control PWM timer. The STM32F100xx low- and medium-density value line family operates in the -40 to +85 C and -40 to +105 C temperature ranges, from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving mode allows the design of low-power applications. The STM32F100xx value line family includes devices in three different packages ranging from 48 pins to 100 pins. Depending on the device chosen, different sets of peripherals are included. These features make the STM32F100xx value line microcontroller family suitable for a wide range of applications such as application control and user interfaces, medical and handheld equipment, PC and gaming peripherals, GPS platforms, industrial applications, PLCs, inverters, printers, scanners, alarm systems, video intercoms, and HVACs. 10/87 Doc ID 16455 Rev 6 STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB 2.1 Description Device overview The description below gives an overview of the complete range of peripherals proposed in this family. Figure 1 shows the general block diagram of the device family. Table 2. STM32F100xx features and peripheral counts Peripheral Flash - Kbytes 16 SRAM - Kbytes Timers STM32F100Cx 4 32 64 4 8 STM32F100Rx 128 16 8 4 32 64 4 8 STM32F100Vx 128 64 8 8 128 8 Advanced-control 1 1 1 1 1 General-purpose 5(1) 6 5(1) 6 6 SPI 1(2) 2 1(2) 2 2 2C 1(3) 2 1(3) 2 2 2(4) 3 2(4) 3 3 Communication I interfaces USART CEC 12-bit synchronized ADC number of channels GPIOs 1 1 10 channels 1 16 channels 1 16 channels 37 51 80 12-bit DAC Number of channels 2 2 CPU frequency 24 MHz Operating voltage Operating temperatures Packages 2.0 to 3.6 V Ambient operating temperature: -40 to +85 C /-40 to +105 C (see Table 8) Junction temperature: -40 to +125 C (see Table 8) LQFP48 LQFP64, TFBGA64 LQFP100 1. TIM4 not present. 2. SPI2 is not present. 3. I2C2 is not present. 4. USART3 is not present. Doc ID 16455 Rev 6 11/87 Description STM32F100xx value line block diagram AS !& .*4234 *4$) *4#+37#,+ *4-337$)/ *4$/ AS !& *4!' 37 4RACE CONTROLLER PBUS )BUS #ORTEX - #05 FMAX -(Z 6OLTAGE REG 6 TO 6 &LASH +" 3YSTEM '0 $-! BIT 32! +" 6$$! 0/2 2ESET 3UPPLY SUPERVISION )NT 0/2 0$2 2# (3 6$$! CHANNELS 0!;= '0)/ PORT ! 0";= '0)/ PORT " !(" & MAX -(Z %84) 4 7+50 6$$ 84!, /3# -(Z 0,, !& 633 .234 6$$! 633! 06$ 2# ,3 2ESET CLOCK CONTROL 6$$ 6 TO 6 6$$ $BUS .6)# 0OWER 6$$ &LASH OBL INTERFACE 42!#%#,+ 42!#%$;= "US MATRIX Figure 1. STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB /3#?). /3#?/54 )7$' 0#,+ 0#,+ (#,+ &#,+ 3TANDBY INTERFACE 6"! 4 6 TO 6 6"!4 84!, K(Z 24# !75 "ACKUP REGISTER /3#?). /3#?/54 4!- 0%2 24# !,!2- /54 "ACKUP INTERFACE 0#;= '0)/ PORT # 0$;= '0)/ PORT $ 0%;= '0)/ PORT % !(" !0" CHANNELS AS !& CHANNELS AS !& 4)- !(" !0" 4)- CHANNEL COMPL CHANNEL AND "+). AS !& 4)- CHANNEL COMPL CHANNEL AND "+). AS !& 4)- CHANNELS COMPL CHANNELS %42 AND "+). AS !& 4)- -/3) -)3/ 3#+ .33 AS !& 30) 28 48 #43 243 #+ AS !& 53!24 !0" & MAX -(Z CHANNELS COMPL CHANNEL AND "+). AS !& !0" & MAX -(Z 4)- 6 53!24 30) BIT !$# )& 28 48 #43 243 #+ AS !& -/3) -)3/ 3#+ .33 AS !& ($-) #%# AS !& 3#, 3$! 3-"! AS !& )# 77$' CHANNELS AS !& 28 48 #43 243 #+ AS !& 53!24 ($-) #%# 4EMP SENSOR !$# CHANNELS !$#?).X 4)- )# 3#, 3$! 3-"! AS !& 4)- )& BIT $!# )& $!#?/54 AS !& 4)- BIT $!# $!# ?/54 AS !& 2%& 6 2%&n 6$$! 6$$! AIB 1. Peripherals not present in low-density value line devices. 2. AF = alternate function on I/O port pin. 3. TA = -40 C to +85 C (junction temperature up to 105 C) or TA = -40 C to +105 C (junction temperature up to 125 C). 12/87 Doc ID 16455 Rev 6 STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB Figure 2. Description Clock tree -(Z (3) 2# (3) &,)4&#,+ TO &LASH PROGRAMMING INTERFACE (#,+ TO !(" BUS CORE MEMORY AND $-! -(Z MAX 0,,32# 37 0,,-5, (3) X X X X 0,, 393#,+ !(" 0RESCALER -(Z MAX 0,,#,+ #LOCK %NABLE !0" 0RESCALER (3% !0" 0RESCALER (3% /3# /3#?/54 ,3% /3# K(Z TO 24# ,3% 24##,+ !$# 0RESCALER 0#,+ -(Z MAX 0ERIPHERAL #LOCK %NABLE 4)- TIMERS )F !0" PRESCALER X ELSE X /3#?). TO 4)- AND 4)-X#,+ 0ERIPHERAL #LOCK %NABLE -(Z 0#,+ TO !0" PERIPHERALS 0ERIPHERAL #LOCK %NABLE 02%$)6 /3#?). -(Z MAX 4)- )F !0" PRESCALER X ELSE X #33 /3#?/54 TO #ORTEX 3YSTEM TIMER &#,+ #ORTEX FREE RUNNING CLOCK PERIPHERALS TO !0" TO 4)- 4)- 4)- AND 4)- 4)-X#,+ 0ERIPHERAL #LOCK %NABLE TO !$# !$##,+ -(Z MAX 24#3%,;= ,3) 2# K(Z TO INDEPENDENT WATCHDOG )7$' ,3) )7$'#,+ -AIN CLOC K OUT PUT -#/ 0,,#,+ ,EGEND (3% (IGH SPEED EXTERNAL CLOCK SIGNAL (3) (3) (IGH SPEED INTERNAL CLOCK SIGNAL (3% ,3) ,OW SPEED INTERNAL CLOCK SIGNAL 393#,+ ,3% ,OW SPEED EXTERNAL CLOCK SIGNAL -#/ AI 4. To have an ADC conversion time of 1.2 s, APB2 must be at 24 MHz. Doc ID 16455 Rev 6 13/87 Description STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB 2.2 Overview 2.2.1 ARM(R) CortexTM-M3 core with embedded Flash and SRAM The ARM CortexTM-M3 processor is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts. The ARM CortexTM-M3 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices. The STM32F100xx value line family having an embedded ARM core, is therefore compatible with all ARM tools and software. 2.2.2 Embedded Flash memory Up to 128 Kbytes of embedded Flash memory is available for storing programs and data. 2.2.3 CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location. 2.2.4 Embedded SRAM Up to 8 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states. 2.2.5 Nested vectored interrupt controller (NVIC) The STM32F100xx value line embeds a nested vectored interrupt controller able to handle up to 41 maskable interrupt channels (not including the 16 interrupt lines of CortexTM-M3) and 16 priority levels. Closely coupled NVIC gives low latency interrupt processing Interrupt entry vector table address passed directly to the core Closely coupled NVIC core interface Allows early processing of interrupts Processing of late arriving higher priority interrupts Support for tail-chaining Processor state automatically saved Interrupt entry restored on interrupt exit with no instruction overhead This hardware block provides flexible interrupt management features with minimal interrupt latency. 14/87 Doc ID 16455 Rev 6 STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB 2.2.6 Description External interrupt/event controller (EXTI) The external interrupt/event controller consists of 18 edge detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 80 GPIOs can be connected to the 16 external interrupt lines. 2.2.7 Clocks and startup System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-24 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example on failure of an indirectly used external crystal, resonator or oscillator). Several prescalers allow the configuration of the AHB frequency, the high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB and the APB domains is 24 MHz. 2.2.8 Boot modes At startup, boot pins are used to select one of three boot options: Boot from user Flash Boot from system memory Boot from embedded SRAM The boot loader is located in System Memory. It is used to reprogram the Flash memory by using USART1. For further details please refer to AN2606. 2.2.9 2.2.10 Power supply schemes VDD = 2.0 to 3.6 V: External power supply for I/Os and the internal regulator. Provided externally through VDD pins. VSSA, VDDA = 2.0 to 3.6 V: External analog power supplies for ADC, DAC, Reset blocks, RCs and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC or DAC is used). VDDA and VSSA must be connected to VDD and VSS, respectively. VBAT = 1.8 to 3.6 V: Power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present. Power supply supervisor The device has an integrated power on reset (POR)/power down reset (PDR) circuitry. It is always active, and ensures proper operation starting from/down to 2 V. The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR, without the need for an external reset circuit. The device features an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher Doc ID 16455 Rev 6 15/87 Description STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. 2.2.11 Voltage regulator The regulator has three operation modes: main (MR), low power (LPR) and power down. MR is used in the nominal regulation mode (Run) LPR is used in the Stop mode Power down is used in Standby mode: the regulator output is in high impedance: the kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and SRAM are lost) This regulator is always enabled after reset. It is disabled in Standby mode, providing high impedance output. 2.2.12 Low-power modes The STM32F100xx value line supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. Stop mode Stop mode achieves the lowest power consumption while retaining the content of SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low power mode. The device can be woken up from Stop mode by any of the EXTI line. The EXTI line source can be one of the 16 external lines, the PVD output or the RTC alarm. Standby mode The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Standby mode, SRAM and register contents are lost except for registers in the Backup domain and Standby circuitry. The device exits Standby mode when an external reset (NRST pin), a IWDG reset, a rising edge on the WKUP pin, or an RTC alarm occurs. Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop or Standby mode. 2.2.13 DMA The flexible 7-channel general-purpose DMA is able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports circular buffer management avoiding the generation of interrupts when the controller reaches the end of the buffer. 16/87 Doc ID 16455 Rev 6 STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB Description Each channel is connected to dedicated hardware DMA requests, with support for software trigger on each channel. Configuration is made by software and transfer sizes between source and destination are independent. The DMA can be used with the main peripherals: SPI, DAC, I2C, USART, all timers and ADC. 2.2.14 RTC (real-time clock) and backup registers The RTC and the backup registers are supplied through a switch that takes power either on VDD supply when present or through the VBAT pin. The backup registers are ten 16-bit registers used to store 20 bytes of user application data when VDD power is not present. The real-time clock provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and a periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low power RC oscillator or the high-speed external clock divided by 128. The internal low power RC has a typical frequency of 40 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural crystal deviation. The RTC features a 32-bit programmable counter for long term measurement using the Compare register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 kHz. 2.2.15 Timers and watchdogs The STM32F100xx devices include an advanced-control timer, six general-purpose timers, two basic timers and two watchdog timers. Table 3 compares the features of the advanced-control, general-purpose and basic timers. Table 3. Timer feature comparison Timer Counter resolution Counter type Prescaler factor DMA request Capture/compare Complementary generation channels outputs TIM1 16-bit Up, down, up/down Any integer between 1 and 65536 Yes 4 Yes TIM2, TIM3, TIM4 16-bit Up, down, up/down Any integer between 1 and 65536 Yes 4 No TIM15 16-bit Up Any integer between 1 and 65536 Yes 2 Yes TIM16, TIM17 16-bit Up Any integer between 1 and 65536 Yes 1 Yes TIM6, TIM7 16-bit Up Any integer between 1 and 65536 Yes 0 No Doc ID 16455 Rev 6 17/87 Description STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB Advanced-control timer (TIM1) The advanced-control timer (TIM1) can be seen as a three-phase PWM multiplexed on 6 channels. It has complementary PWM outputs with programmable inserted dead times. It can also be seen as a complete general-purpose timer. The 4 independent channels can be used for: Input capture Output compare PWM generation (edge or center-aligned modes) One-pulse mode output If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If configured as the 16-bit PWM generator, it has full modulation capability (0-100%). The counter can be frozen in debug mode. Many features are shared with those of the standard TIM timers which have the same architecture. The advanced control timer can therefore work together with the TIM timers via the Timer Link feature for synchronization or event chaining. General-purpose timers (TIM2, TIM3, TIM4, TIM15, TIM16 & TIM17) There are six synchronizable general-purpose timers embedded in the STM32F100xx devices (see Table 3 for differences). Each general-purpose timers can be used to generate PWM outputs, or as simple time base. TIM2, TIM3, TIM4 STM32F100xx devices feature three synchronizable 4-channels general-purpose timers. These timers are based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. They feature 4 independent channels each for input capture/output compare, PWM or onepulse mode output. This gives up to 12 input captures/output compares/PWMs on the largest packages. The TIM2, TIM3, TIM4 general-purpose timers can work together or with the TIM1 advanced-control timer via the Timer Link feature for synchronization or event chaining. TIM2, TIM3, TIM4 all have independent DMA request generation. These timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors. Their counters can be frozen in debug mode. TIM15, TIM16 and TIM17 These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. TIM15 has two independent channels, whereas TIM16 and TIM17 feature one single channel for input capture/output compare, PWM or one-pulse mode output. The TIM15, TIM16 and TIM17 timers can work together, and TIM15 can also operate with TIM1 via the Timer Link feature for synchronization or event chaining. TIM15 can be synchronized with TIM16 and TIM17. TIM15, TIM16, and TIM17 have a complementary output with dead-time generation and independent DMA request generation 18/87 Doc ID 16455 Rev 6 STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB Description Their counters can be frozen in debug mode. Basic timers TIM6 and TIM7 These timers are mainly used for DAC trigger generation. They can also be used as a generic 16-bit time base. Independent watchdog The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 40 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode. Window watchdog The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. SysTick timer This timer is dedicated for OS, but could also be used as a standard down counter. It features: 2.2.16 A 24-bit down counter Autoreload capability Maskable system interrupt generation when the counter reaches 0. Programmable clock source IC bus The IC bus interface can operate in multimaster and slave modes. It can support standard and fast modes. It supports dual slave addressing (7-bit only) and both 7/10-bit addressing in master mode. A hardware CRC generation/verification is embedded. The interface can be served by DMA and it supports SM Bus 2.0/PM Bus. 2.2.17 Universal synchronous/asynchronous receiver transmitter (USART) The STM32F100xx value line embeds three universal synchronous/asynchronous receiver transmitters (USART1, USART2 and USART3). The available USART interfaces communicate at up to 3 Mbit/s. They provide hardware management of the CTS and RTS signals, they support IrDA SIR ENDEC, the multiprocessor communication mode, the single-wire half-duplex communication mode and have LIN Master/Slave capability. The USART interfaces can be served by the DMA controller. Doc ID 16455 Rev 6 19/87 Description 2.2.18 STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB Serial peripheral interface (SPI) Up to two SPIs are able to communicate up to 12 Mbit/s in slave and master modes in fullduplex and simplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. Both SPIs can be served by the DMA controller. 2.2.19 HDMI (high-definition multimedia interface) consumer electronics control (CEC) The STM32F100xx value line embeds a HDMI-CEC controller that provides hardware support of consumer electronics control (CEC) (Appendix supplement 1 to the HDMI standard). This protocol provides high-level control functions between all audiovisual products in an environment. It is specified to operate at low speeds with minimum processing and memory overhead. 2.2.20 GPIOs (general-purpose inputs/outputs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high currentcapable except for analog inputs. The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers. 2.2.21 Remap capability This feature allows the use of a maximum number of peripherals in a given application. Indeed, alternate functions are available not only on the default pins but also on other specific pins onto which they are remappable. This has the advantage of making board design and port usage much more flexible. For details refer to Table 4: STM32F100xx pin definitions; it shows the list of remappable alternate functions and the pins onto which they can be remapped. See the STM32F10xxx reference manual for software considerations. 2.2.22 ADC (analog-to-digital converter) The 12-bit analog to digital converter has up to 16 external channels and performs conversions in single-shot or scan modes. In scan mode, automatic conversion is performed on a selected group of analog inputs. The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. 20/87 Doc ID 16455 Rev 6 STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB 2.2.23 Description DAC (digital-to-analog converter) The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs. The chosen design structure is composed of integrated resistor strings and an amplifier in noninverting configuration. This dual digital Interface supports the following features: two DAC converters: one for each output channel up to 10-bit output left or right data alignment in 12-bit mode synchronized update capability noise-wave generation triangular-wave generation dual DAC channels' independent or simultaneous conversions DMA capability for each channel external triggers for conversion input voltage reference VREF+ Eight DAC trigger inputs are used in the STM32F100xx. The DAC channels are triggered through the timer update outputs that are also connected to different DMA channels. 2.2.24 Temperature sensor The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 2 V < VDDA < 3.6 V. The temperature sensor is internally connected to the ADC1_IN16 input channel which is used to convert the sensor output voltage into a digital value. 2.2.25 Serial wire JTAG debug port (SWJ-DP) The ARM SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. Doc ID 16455 Rev 6 21/87 Pinouts and pin description 3 STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB Pinouts and pin description STM32F100xx value line LQFP100 pinout 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 VDD_3 VSS_3 PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 Figure 3. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 LQFP100 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VDD_2 VSS_2 NC PA 13 PA 12 PA 11 PA 10 PA 9 PA 8 PC9 PC8 PC7 PC6 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12 PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VSS_1 VDD_1 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PE2 PE3 PE4 PE5 PE6 VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT VSS_5 VDD_5 OSC_IN OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VREFVREF+ VDDA PA0-WKUP PA1 PA2 ai14386b 22/87 Doc ID 16455 Rev 6 STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB STM32F100xx value line LQFP64 pinout VDD_3 VSS_3 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14 Figure 4. Pinouts and pin description 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 8 LQFP64 40 9 39 10 38 11 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VDD_2 VSS_2 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PB15 PB14 PB13 PB12 PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PB10 PB11 VSS_1 VDD_1 VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT PD0 OSC_IN PD1 OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VDDA PA0-WKUP PA1 PA2 ai14387b VDD_3 VSS_3 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PA15 PA14 STM32F100xx value line LQFP48 pinout VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT PD0-OSC_IN PD1-OSC_OUT NRST VSSA VDDA PA0-WKUP PA1 PA2 48 47 46 45 44 43 42 41 40 39 38 37 36 1 2 35 34 3 33 4 32 5 31 6 LQFP48 30 7 29 8 28 9 27 10 26 11 25 12 13 14 15 16 17 18 19 20 21 22 23 24 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB10 PB11 VSS_1 VDD_1 Figure 5. Doc ID 16455 Rev 6 VDD_2 VSS_2 PA13 PA12 PA11 PA10 PA9 PA8 PB15 PB14 PB13 PB12 ai14378d 23/87 Pinouts and pin description Figure 6. STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB STM32F100xx value line TFBGA64 ballout 1 A 2 PC14PC13OSC32_IN TAMPER-RTC 3 4 5 6 7 8 PB9 PB4 PB3 PA15 PA14 PA13 B PC15OSC32_OUT VBAT PB8 BOOT0 PD2 PC11 PC10 PA12 C OSC_IN VSS_4 PB7 PB5 PC12 PA10 PA9 PA11 D OSC_OUT VDD_4 PB6 VSS_3 VSS_2 VSS_1 PA8 PC9 E NRST PC1 PC0 VDD_3 VDD_2 VDD_1 PC7 PC8 F VSSA PC2 PA2 PA5 PB0 PC6 PB15 PB14 G VREF+ PA0-WKUP PA3 PA6 PB1 PB2 PB10 PB13 H VDDA PA1 PA4 PA7 PC4 PC5 PB11 PB12 AI15494 STM32F100xx pin definitions Alternate functions(3)(4) TFBGA64 LQFP48 Default LQFP64 Main function(3) (after reset) LQFP100 Type(1) Pins I / O level(2) Table 4. Pin name 1 - - - PE2 I/O FT PE2 TRACECLK 2 - - - PE3 I/O FT PE3 TRACED0 3 - - - PE4 I/O FT PE4 TRACED1 4 - - - PE5 I/O FT PE5 TRACED2 5 - - - PE6 I/O FT PE6 TRACED3 6 1 B2 1 VBAT S VBAT 7 2 A2 2 PC13-TAMPERRTC(5) I/O PC13(6) TAMPER-RTC 8 3 A1 3 PC14OSC32_IN(5) I/O PC14(6) OSC32_IN 24/87 Doc ID 16455 Rev 6 Remap STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB STM32F100xx pin definitions (continued) Alternate functions(3)(4) LQFP48 OSC32_OUT TFBGA64 Default LQFP64 Main function(3) (after reset) LQFP100 Type(1) Pins I / O level(2) Table 4. Pinouts and pin description 9 4 B1 4 PC15OSC32_OUT(5) I/O PC15(6) 10 - - - VSS_5 S VSS_5 11 - - - VDD_5 S VDD_5 12 5 C1 5 OSC_IN I OSC_IN 13 6 D1 6 OSC_OUT O OSC_OUT 14 7 E1 7 NRST I/O NRST 15 8 E3 - PC0 I/O PC0 ADC1_IN10 16 9 E2 - PC1 I/O PC1 ADC1_IN11 17 10 F2 - PC2 I/O PC2 ADC1_IN12 18 11 -(7) - PC3 I/O PC3 ADC1_IN13 19 12 F1 8 VSSA S VSSA Pin name Remap 20 - - - VREF- S VREF- 21 - G1 - VREF+ S VREF+ 22 13 H1 9 VDDA S VDDA 23 14 G2 10 PA0-WKUP I/O PA0 WKUP / USART2_CTS(12)/ ADC1_IN0 / TIM2_CH1_ETR(12) 24 15 H2 11 PA1 I/O PA1 USART2_RTS(12)/ ADC1_IN1 / TIM2_CH2(12) 25 16 F3 12 PA2 I/O PA2 USART2_TX(12)/ ADC1_IN2 / TIM2_CH3(12)/ TIM15_CH1(12) 26 17 G3 13 PA3 I/O PA3 USART2_RX(12)/ ADC1_IN3 / TIM2_CH4(12) / TIM15_CH2(12) 27 18 C2 - VSS_4 S VSS_4 28 19 D2 - VDD_4 S VDD_4 29 20 H3 14 PA4 I/O PA4 SPI1_NSS(12)/ADC1_IN4 USART2_CK(12) / DAC1_OUT 30 21 F4 15 PA5 I/O PA5 SPI1_SCK(12)/ADC1_IN5 / DAC2_OUT 31 22 G4 16 PA6 I/O PA6 SPI1_MISO(12)/ADC1_IN6 / TIM3_CH1(12) TIM1_BKIN / TIM16_CH1 32 23 H4 17 PA7 I/O PA7 SPI1_MOSI(12)/ADC1_IN7 / TIM3_CH2(12) TIM1_CH1N / TIM17_CH1 33 24 H5 - PC4 I/O PC4 ADC1_IN14 34 25 H6 - PC5 I/O PC5 ADC1_IN15 Doc ID 16455 Rev 6 25/87 Pinouts and pin description STM32F100xx pin definitions (continued) 26 F5 18 Pin name PB0 Type(1) LQFP64 35 LQFP48 LQFP100 TFBGA64 Pins Alternate functions(3)(4) I / O level(2) Table 4. STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB I/O Main function(3) (after reset) Default Remap PB0 ADC1_IN8/TIM3_CH3(12) TIM1_CH2N PB1 ADC1_IN9/TIM3_CH4(12) TIM1_CH3N 36 27 G5 19 PB1 I/O 37 28 G6 20 PB2 I/O FT PB2/BOOT1 38 - - - PE7 I/O FT PE7 TIM1_ETR 39 - - - PE8 I/O FT PE8 TIM1_CH1N 40 - - - PE9 I/O FT PE9 TIM1_CH1 41 - - - PE10 I/O FT PE10 TIM1_CH2N 42 - - - PE11 I/O FT PE11 TIM1_CH2 43 - - - PE12 I/O FT PE12 TIM1_CH3N 44 - - - PE13 I/O FT PE13 TIM1_CH3 45 - - - PE14 I/O FT PE14 TIM1_CH4 46 - - - PE15 I/O FT PE15 TIM1_BKIN 47 29 G7 21 PB10 I/O FT PB10 I2C2_SCL(8)/USART3_TX (12) TIM2_CH3 / CEC 48 30 H7 22 PB11 I/O FT PB11 I2C2_SDA(8)/USART3_RX(12) TIM2_CH4 49 31 D6 23 VSS_1 S VSS_1 50 32 E6 24 VDD_1 S VDD_1 51 33 H8 25 PB12 I/O FT PB12 SPI2_NSS(9)/ I2C2_SMBA(8)/ TIM1_BKIN(12)/USART3_CK(12) 52 34 G8 26 PB13 I/O FT PB13 SPI2_SCK(9) /TIM1_CH1N(12) USART3_CTS(12) 53 35 F8 27 PB14 I/O FT PB14 SPI2_MISO(9)/ TIM1_CH2N(12) / USART3_RTS(12) TIM15_CH1 54 36 F7 28 PB15 I/O FT PB15 SPI2_MOSI(9) / TIM1_CH3N / TIM15_CH1N(12) TIM15_CH2 55 - - - PD8 I/O FT PD8 USART3_TX 56 - - - PD9 I/O FT PD9 USART3_RX 57 - - - PD10 I/O FT PD10 USART3_CK 58 - - - PD11 I/O FT PD11 USART3_CTS 59 - - - PD12 I/O FT PD12 TIM4_CH1(10) / USART3_RTS 60 - - - PD13 I/O FT PD13 TIM4_CH2(10) 61 - - - PD14 I/O FT PD14 TIM4_CH3(10) 62 - - - PD15 I/O FT PD15 TIM4_CH4(10) 26/87 Doc ID 16455 Rev 6 STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB STM32F100xx pin definitions (continued) 37 F6 64 Type(1) LQFP64 63 Alternate functions(3)(4) Main function(3) (after reset) LQFP48 LQFP100 TFBGA64 Pins I / O level(2) Table 4. Pinouts and pin description Pin name - PC6 I/O FT PC6 TIM3_CH1 38 E7 PC7 I/O FT PC7 TIM3_CH2 65 39 E8 PC8 I/O FT PC8 TIM3_CH3 66 40 D8 PC9 I/O FT PC9 TIM3_CH4 67 41 D7 29 PA8 I/O FT PA8 USART1_CK / MCO / TIM1_CH1 68 42 C7 30 PA9 I/O FT PA9 USART1_TX(12) / TIM1_CH2 / TIM15_BKIN 69 43 C6 31 PA10 I/O FT PA10 USART1_RX(12) / TIM1_CH3 / TIM17_BKIN 70 44 C8 32 PA11 I/O FT PA11 USART1_CTS / TIM1_CH4 71 45 B8 33 PA12 I/O FT PA12 USART1_RTS / TIM1_ETR 72 46 A8 34 PA13 I/O FT JTMS-SWDIO 73 - - - - Default Remap PA13 Not connected 74 47 D5 35 VSS_2 S VSS_2 75 48 E5 36 VDD_2 S VDD_2 76 49 A7 37 PA14 I/O FT JTCK/SWCLK 77 50 A6 38 PA15 I/O FT JTDI TIM2_CH1_ETR / PA15/ SPI1_NSS 78 51 B7 - PC10 I/O FT PC10 USART3_TX 79 52 B6 - PC11 I/O FT PC11 USART3_RX 80 53 C5 - PC12 I/O FT PC12 USART3_CK OSC_IN PA14 (11) 81 5 C1 5 PD0 I/O FT 82 6 D1 6 PD1 I/O FT OSC_OUT(11) 83 54 B5 PD2 I/O FT PD2 TIM3_ETR 84 - - - PD3 I/O FT PD3 USART2_CTS 85 - - - PD4 I/O FT PD4 USART2_RTS 86 - - - PD5 I/O FT PD5 USART2_TX 87 - - - PD6 I/O FT PD6 USART2_RX 88 - - - PD7 I/O FT PD7 USART2_CK PB3 I/O FT JTDO TIM2_CH2 / PB3 TRACESWO SPI1_SCK 89 55 A5 39 Doc ID 16455 Rev 6 27/87 Pinouts and pin description STM32F100xx pin definitions (continued) 90 56 A4 40 PB4 I/O FT 91 57 C4 41 PB5 I/O PB5 I2C1_SMBA / TIM16_BKIN TIM3_CH2 / SPI1_MOSI 92 58 D3 42 PB6 I/O FT PB6 I2C1_SCL(12)/ TIM4_CH1(10)(12) TIM16_CH1N USART1_TX 93 59 C3 43 PB7 I/O FT PB7 I2C1_SDA(12)/ TIM17_CH1N TIM4_CH2(10)(12) USART1_RX 94 60 B4 44 BOOT0 95 61 B3 45 PB8 I/O FT PB8 TIM4_CH3(10)(12) / TIM16_CH1(12) / CEC(12) I2C1_SCL 96 62 A3 46 PB9 I/O FT PB9 TIM4_CH4(10)(12) / TIM17_CH1(12) I2C1_SDA TIM4_ETR(10) LQFP48 LQFP64 Type(1) Alternate functions(3)(4) Main function(3) (after reset) LQFP100 TFBGA64 Pins I / O level(2) Table 4. STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB Pin name I Remap PB4 / TIM3_CH1 SPI1_MISO NJTRST BOOT0 97 - - - PE0 I/O FT PE0 98 - - - PE1 I/O FT PE1 99 Default 63 D4 47 VSS_3 S VSS_3 100 64 E4 48 VDD_3 S VDD_3 1. I = input, O = output, S = supply, HiZ= high impedance. 2. FT= 5 V tolerant. 3. Function availability depends on the chosen device. For devices having reduced peripheral counts, it is always the lower number of peripherals that is included. For example, if a device has only one SPI, two USARTs and two timers, they will be called SPI1, USART1 & USART2 and TIM2 & TIM 3, respectively. Refer to Table 2 on page 11. 4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register). 5. PC13, PC14 and PC15 are supplied through the power switch and since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is restricted: the speed should not exceed 2 MHz with a maximum load of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED). 6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com. 7. Unlike in the LQFP64 package, there is no PC3 in the TFBGA64 package. The VREF+ functionality is provided instead. 8. I2C2 is not present on low-density value line devices. 9. SPI2 is not present on low-density value line devices. 10. TIM4 is not present on low-density value line devices. 11. The pins number 2 and 3 in the VFQFPN36 package, 5 and 6 in the LQFP48 and LQFP64 packages and C1 and C2 in the TFBGA64 package are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by software on these pins. For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual. 12. This alternate function can be remapped by software to some other port pins (if available on the used package). For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com. 28/87 Doc ID 16455 Rev 6 STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB 4 Memory mapping Memory mapping The memory map is shown in Figure 7. Figure 7. Memory map APB memory space 0xFFFF FFFF 0x4002 3400 0x4002 3000 0x4002 2400 0xFFFF FFFF 7 0xE010 0000 0xE000 0000 Flash interface 0x4002 1400 reserved 0x4002 1000 RCC 0x4002 0400 reserved 0x4001 4C00 0x4001 4800 0x4001 4400 6 CRC reserved 0x4002 2000 0x4002 0000 Cortex-M3 internal peripherals reserved 0x4001 4000 DMA reserved TIM17 TIM16 TIM15 reserved 0x4001 3C00 0xC000 0000 0x4001 3800 0x4001 3400 0x4001 3000 5 0x4001 2C00 0xA000 0000 0x4001 2800 0x4001 2400 4 0x1FFF FFFF 0x4001 1C00 0x4001 1800 reserved 0x1FFF F80F 0x8000 0000 Option Bytes 0x1FFF F800 System memory 3 0x1FFF F000 0x6000 0000 0x4000 0000 Peripherals Port C Port B 0x4001 0800 Port A 0x4001 0400 EXTI 0x4001 0000 AFIO 0x4000 7C00 reserved 0x4000 7800 CEC 0x4000 6C00 0x4000 5400 0x4000 4C00 0x4000 4800 SRAM 0x0801 FFFF 0x4000 4400 0x4000 3C00 Flash memory 0 0x0800 0000 0x0000 0000 Reserved Aliased to Flash or system memory depending on 0x0000 0000 BOOT pins 0x4000 3800 0x4000 3400 DAC PWR BKP I2C2 reserved I2C1 reserved USART3 USART2 reserved SPI2 reserved 0x4000 3000 IWDG 0x4000 2C00 WWDG 0x4000 2800 0x4000 1800 0x4000 1400 0x4000 1000 0x4000 0C00 Doc ID 16455 Rev 6 Port E 0x4001 0C00 0x4000 5800 0x2000 0000 ADC1 reserved 0x4001 1000 0x4000 5C00 1 TIM1 reserved Port D 0x4000 7000 reserved SPI1 0x4001 1400 0x4000 7400 2 USART1 reserved RTC reserved TIM7 TIM6 reserved 0x4000 0800 TIM4 0x4000 0400 TIM3 0x4000 0000 TIM2 ai17156 29/87 Electrical characteristics STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB 5 Electrical characteristics 5.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 5.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3). 5.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 C, VDD = 3.3 V (for the 2 V VDD 3.6 V voltage range). They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2). 5.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 5.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 8. 5.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 9. 30/87 Doc ID 16455 Rev 6 STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB Figure 8. Pin loading conditions Electrical characteristics Figure 9. Pin input voltage STM32F10xxx pin STM32F10xxx pin C = 50 pF VIN ai14124b ai14123b 5.1.6 Power supply scheme Figure 10. Power supply scheme 6"!4 "ACKUP CIRCUITRY /3#+ 24# 7AKE UP LOGIC "ACKUP REGISTERS /54 '0 )/S ). ,EVEL SHIFTER 0O WER SWI TCH 6 )/ ,OGIC +ERNEL LOGIC #05 $IGITAL -EMORIES 6$$ 6$$ N& & 6$$ 6$$! 62%& N& & 2EGULATOR 633 N& & 62%& 62%& !$#$!# !NALOG 2#S 0,, 633! AIE Caution: In Figure 10, the 4.7 F capacitor must be connected to VDD3. Doc ID 16455 Rev 6 31/87 Electrical characteristics 5.1.7 STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB Current consumption measurement Figure 11. Current consumption measurement scheme IDD_VBAT VBAT IDD VDD VDDA ai14126 5.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 5: Voltage characteristics, Table 6: Current characteristics, and Table 7: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 5. Symbol VDD - VSS VIN(2) |VDDx| |VSSX - VSS| VESD(HBM) Voltage characteristics Ratings Min Max -0.3 4.0 Input voltage on five volt tolerant pin VSS - 0.3 VDD + 4.0 Input voltage on any other pin VSS - 0.3 4.0 External main supply voltage (including VDDA and VDD)(1) Variations between different VDD power pins 50 Variations between all the different ground pins 50 Electrostatic discharge voltage (human body model) Unit V mV see Section 5.3.11: Absolute maximum ratings (electrical sensitivity) 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. VIN maximum must always be respected. Refer to Table 6: Current characteristics for the maximum allowed injected current values. 32/87 Doc ID 16455 Rev 6 STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB Table 6. Electrical characteristics Current characteristics Symbol Ratings Max. Total current into VDD/VDDA power lines (source)(1) IVDD Total current out of VSS ground lines (sink) IVSS IIO 150 (1) 150 Output current sunk by any I/O and control pin 25 Output current source by any I/Os and control pin -25 (3) Injected current on five volt tolerant pins IINJ(PIN)(2) Injected current on any other pin IINJ(PIN) Unit mA +5 / -0 (4) 5 Total injected current (sum of all I/O and control pins) (5) 25 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. Negative injection disturbs the analog performance of the device. SeeNote: on page 69. 3. Positive injection is not possible on these I/Os. A negative injection is induced by VIN<VSS. IINJ(PIN) must never be exceeded. Refer to Table 5: Voltage characteristics for the maximum allowed input voltage values. 4. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. IINJ(PIN) must never be exceeded. Refer to Table 5: Voltage characteristics for the maximum allowed input voltage values. 5. When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). Table 7. Thermal characteristics Symbol TSTG TJ Ratings Storage temperature range Maximum junction temperature 5.3 Operating conditions 5.3.1 General operating conditions Table 8. Value Unit -65 to +150 C 150 C General operating conditions Symbol Parameter fHCLK Min Max Internal AHB clock frequency 0 24 fPCLK1 Internal APB1 clock frequency 0 24 fPCLK2 Internal APB2 clock frequency 0 24 Standard operating voltage 2 3.6 2 3.6 2.4 3.6 1.8 3.6 VDD VDDA (1) VBAT Analog operating voltage (ADC not used) Analog operating voltage (ADC used) Conditions Must be the same potential as VDD Backup operating voltage Doc ID 16455 Rev 6 Unit MHz V V V 33/87 Electrical characteristics Table 8. Symbol PD STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB General operating conditions (continued) Parameter Power dissipation at TA = 85 C for suffix 6 or TA = 105 C for suffix 7(2) Conditions Min Max LQFP100 434 LQFP64 444 TFBGA64 308 LQFP48 363 Unit mW Ambient temperature for 6 suffix version Maximum power dissipation -40 85 Low power dissipation(3) -40 105 Ambient temperature for 7 suffix version Maximum power dissipation -40 105 Low power dissipation -40 125 6 suffix version -40 105 7 suffix version -40 125 C TA TJ (3) C Junction temperature range C 1. When the ADC is used, refer to Table 42: ADC characteristics. 2. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Table 6.2: Thermal characteristics on page 81). 3. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Table 6.2: Thermal characteristics on page 81). 5.3.2 Operating conditions at power-up / power-down Subject to general operating conditions for TA. Table 9. Symbol tVDD 5.3.3 Operating conditions at power-up / power-down Parameter Min Max VDD rise time rate 0 VDD fall time rate 20 Unit s/V Embedded reset and power control block characteristics The parameters given in Table 10 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 8. 34/87 Doc ID 16455 Rev 6 STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB . Table 10. Embedded reset and power control block characteristics Symbol Parameter Conditions Programmable voltage detector level selection VPVD VPVDhyst Electrical characteristics (2) VPOR/PDR VPDRhyst (2) Min Typ Max Unit PLS[2:0]=000 (rising edge) 2.1 2.18 2.26 V PLS[2:0]=000 (falling edge) 2 2.08 2.16 V PLS[2:0]=001 (rising edge) 2.19 2.28 2.37 V PLS[2:0]=001 (falling edge) 2.09 2.18 2.27 V PLS[2:0]=010 (rising edge) 2.28 2.38 2.48 V PLS[2:0]=010 (falling edge) 2.18 2.28 2.38 V PLS[2:0]=011 (rising edge) 2.38 2.48 2.58 V PLS[2:0]=011 (falling edge) 2.28 2.38 2.48 V PLS[2:0]=100 (rising edge) 2.47 2.58 2.69 V PLS[2:0]=100 (falling edge) 2.37 2.48 2.59 V PLS[2:0]=101 (rising edge) 2.57 2.68 2.79 V PLS[2:0]=101 (falling edge) 2.47 2.58 2.69 V PLS[2:0]=110 (rising edge) 2.66 2.78 2.9 V PLS[2:0]=110 (falling edge) 2.56 2.68 2.8 V PLS[2:0]=111 (rising edge) 2.76 2.88 3 V PLS[2:0]=111 (falling edge) 2.66 2.78 2.9 V PVD hysteresis 100 Power on/power down reset threshold mV Falling edge 1.8(1) 1.88 1.96 V Rising edge 1.84 1.92 2.0 V PDR hysteresis 40 tRSTTEMPO(2) Reset temporization 1.5 2.5 mV 4.5 ms 1. The product behavior is guaranteed by design down to the minimum VPOR/PDR value. 2. Guaranteed by design, not tested in production. Doc ID 16455 Rev 6 35/87 Electrical characteristics 5.3.4 STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB Embedded reference voltage The parameters given in Table 11 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 8. Table 11. Symbol VREFINT Embedded internal reference voltage Parameter Internal reference voltage Conditions Min Typ Max Unit -40 C < TA < +105 C 1.16 1.20 1.26 V -40 C < TA < +85 C 1.16 1.20 1.24 V 5.1 17.1(2) s 10 mV 100 ppm/C ADC sampling time when TS_vrefint(1) reading the internal reference voltage Internal reference voltage VRERINT(2) spread over the temperature range TCoeff(2) VDD = 3 V 10 mV Temperature coefficient 1. Shortest sampling time can be determined in the application by multiple iterations. 2. Guaranteed by design, not tested in production. 5.3.5 Supply current characteristics The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in Figure 11: Current consumption measurement scheme. All Run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to Dhrystone 2.1 code. Maximum current consumption The MCU is placed under the following conditions: All I/O pins are in input mode with a static value at VDD or VSS (no load) All peripherals are disabled except if it is explicitly mentioned Prefetch in on (reminder: this bit must be set before clock setting and bus prescaling) When the peripherals are enabled fPCLK1 = fHCLK/2, fPCLK2 = fHCLK The parameters given in Table 12 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 8. 36/87 Doc ID 16455 Rev 6 STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB Table 12. Electrical characteristics Maximum current consumption in Run mode, code with data processing running from Flash Max(1) Symbol Parameter Conditions External clock (2), all peripherals enabled IDD Supply current in Run mode fHCLK Unit TA = 85 C TA = 105 C 24 MHz 15.4 15.7 16 MHz 11 11.5 8 MHz 6.7 6.9 24 MHz 10.3 10.5 16 MHz 7.8 8.1 8 MHz 5.1 5.3 mA External clock(2), all peripherals disabled 1. Based on characterization, not tested in production. 2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. Table 13. Maximum current consumption in Run mode, code with data processing running from RAM Max(1) Symbol Parameter Conditions External clock (2), all peripherals enabled IDD Supply current in Run mode fHCLK Unit TA = 85 C TA = 105 C 24 MHz 14.5 15 16 MHz 10 10.5 8 MHz 6 6.3 24MHz 9.3 9.7 16 MHz 6.8 7.2 8 MHz 4.4 4.7 mA External clock(2) all peripherals disabled 1. Based on characterization, tested in production at VDD max, fHCLK max. 2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. Doc ID 16455 Rev 6 37/87 Electrical characteristics STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB Figure 12. Maximum current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals enabled #ONSUMPTION M! -(Z -(Z -(Z n # # # # 4EMPERATURE # AI Figure 13. Maximum current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals disabled #ONSUMPTION M! -(Z -(Z -(Z n # # # # 4EMPERATURE # Table 14. AI STM32F100xxB maximum current consumption in Sleep mode, code running from Flash or RAM Max(1) Symbol Parameter Conditions External clock(2) all peripherals enabled IDD Supply current in Sleep mode fHCLK Unit TA = 85 C TA = 105 C 24 MHz 9.6 10 16 MHz 7.1 7.5 8 MHz 4.5 4.8 24 MHz 3.8 4 16 MHz 3.3 3.5 8 MHz 2.7 3 mA External clock(2), all peripherals disabled 1. Based on characterization, tested in production at VDD max and fHCLK max with peripherals enabled. 2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. 38/87 Doc ID 16455 Rev 6 STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB Table 15. Electrical characteristics Typical and maximum current consumptions in Stop and Standby modes Typ(1) Symbol Parameter Conditions VDD/VBAT VDD/ VBAT VDD/VBAT TA = TA = = 2.0 V = 2.4 V = 3.3 V 85 C 105 C Regulator in Run mode, Low-speed and high-speed internal RC oscillators and highspeed oscillator OFF (no Supply current independent watchdog) in Stop mode Regulator in Low-Power mode, Low-speed and high-speed internal RC oscillators and highspeed oscillator OFF (no independent watchdog) IDD Max Low-speed internal RC oscillator and independent watchdog ON Low-speed internal RC oscillator Supply current ON, independent watchdog OFF in Standby mode Low-speed internal RC oscillator and independent watchdog OFF, low-speed oscillator and RTC OFF Backup Low-speed oscillator and RTC IDD_VBAT domain supply ON current 0.9 23.5 24 190 350 13.5 14 170 330 2.6 3.4 - - 2.4 3.2 - - 1.7 2 4 5 1.1 1.4 1.9 2.2 Unit A 1. Typical values are measured at TA = 25 C. Figure 14. Typical current consumption on VBAT with RTC on vs. temperature at different VBAT values 2.00 IDD_VBAT (A) 1.50 3.6 V 3.3 V 1.00 2.4 V 2V 0.50 0.00 -45C 25C 85C Temperature (C) Doc ID 16455 Rev 6 105C ai15792 39/87 Electrical characteristics STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB Figure 15. Typical current consumption in Stop mode with regulator in Run mode versus temperature at VDD = 3.3 V and 3.6 V #ONSUMPTION ! 6 6 n # # # 4EMPERATURE # # AI Figure 16. Typical current consumption in Stop mode with regulator in Low-power mode versus temperature at VDD = 3.3 V and 3.6 V #ONSUMPTION ! 6 6 n # # # 4EMPERATURE # 40/87 Doc ID 16455 Rev 6 # AI STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB Electrical characteristics Figure 17. Typical current consumption in Standby mode versus temperature at VDD = 3.3 V and 3.6 V #ONSUMPTION ! 6 6 n # # # # 4EMPERATURE # AI Typical current consumption The MCU is placed under the following conditions: All I/O pins are in input mode with a static value at VDD or VSS (no load) All peripherals are disabled except if it is explicitly mentioned When the peripherals are enabled fPCLK1 = fHCLK/4, fPCLK2 = fHCLK/2, fADCCLK = fPCLK2/4 The parameters given in Table 16 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 8. Doc ID 16455 Rev 6 41/87 Electrical characteristics Table 16. STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB Typical current consumption in Run mode, code with data processing running from Flash Typical values(1) Symbol Parameter Conditions Running on high-speed external clock with an 8 MHz crystal(3) IDD Supply current in Run mode fHCLK All peripherals All peripherals enabled(2) disabled 24 MHz 12.8 9.3 16 MHz 9.3 6.6 8 MHz 5.1 3.9 4 MHz 3.2 2.5 2 MHz 2.1 1.75 1 MHz 1.55 1.4 500 kHz 1.3 1.2 125 kHz 1.1 1.05 24 MHz 12.2 8.6 16 MHz 8.5 6 8 MHz 4.6 3.3 4 MHz 2.6 1.9 2 MHz 1.5 1.15 1 MHz 0.9 0.8 500 kHz 0.65 0.6 125 kHz 0.45 0.43 Unit mA Running on high-speed internal RC (HSI) 1. Typical values are measures at TA = 25 C, VDD = 3.3 V. 2. Add an additional power consumption of 0.8 mA for the ADC and of 0.5 mA for the DAC analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register). 3. An 8 MHz crystal is used as the external clock source. The AHB prescaler is used to reduce the frequency when fHCLK < 8 MHz, the PLL is used when fHCLK > 8 MHz. 42/87 Doc ID 16455 Rev 6 STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB Table 17. Electrical characteristics Typical current consumption in Sleep mode, code running from Flash or RAM Typical values(1) Symbol Parameter Conditions Running on high-speed external clock with an 8 MHz crystal(3) Supply current in Sleep mode IDD fHCLK All peripherals All peripherals enabled(2) disabled 24 MHz 7.3 2.6 16 MHz 5.2 2 8 MHz 2.8 1.3 4 MHz 2 1.1 2 MHz 1.5 1.1 1 MHz 1.25 1 500 kHz 1.1 1 125 kHz 1.05 0.95 24 MHz 6.65 1.9 16 MHz 4.5 1.4 8 MHz 2.2 0.7 4 MHz 1.35 0.55 2 MHz 0.85 0.45 1 MHz 0.6 0.41 500 kHz 0.5 0.39 125 kHz 0.4 0.37 Unit mA Running on high-speed internal RC (HSI) 1. Typical values are measures at TA = 25 C, VDD = 3.3 V. 2. Add an additional power consumption of 0.8 mA for the ADC and of 0.5 mA for the DAC analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register). 3. An 8 MHz crystal is used as the external clock source. The AHB prescaler is used to reduce the frequency when fHCLK > 8 MHz, the PLL is used when fHCLK > 8 MHz. On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in Table 18. The MCU is placed under the following conditions: all I/O pins are in input mode with a static value at VDD or VSS (no load) all peripherals are disabled unless otherwise mentioned the given value is calculated by measuring the current consumption - with all peripherals clocked off - with only one peripheral clocked on ambient operating temperature and VDD supply voltage conditions summarized in Table 5. Doc ID 16455 Rev 6 43/87 Electrical characteristics Table 18. STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB Peripheral current consumption Peripheral APB1 Typical consumption at 25 C(1) TIM2 0.52 TIM3 0.46 TIM4 0.5 TIM6 0.125 TIM7 0.19 DAC 0.5(2) WWDG 0.13 SPI2 0.2 USART2 0.38 USART3 0.32 I2C1 0.27 I2C2 0.28 HDMI CEC 0.16 GPIO A 0.25 GPIO B 0.12 GPIO C 0.18 GPIO D 0.15 GPIO E 0.15 (3) 1.15 ADC1 Unit mA APB2 SPI1 0.12 USART1 0.27 TIM1 0.63 TIM15 0.33 TIM16 0.26 TIM17 0.25 1. fHCLK = fAPB1 = fAPB2 = 24 MHz, default prescaler value for each peripheral. 2. Specific conditions for DAC: EN1 bit in DAC_CR register set to 1. 3. Specific conditions for ADC: fHCLK = 24 MHz, fAPB1 = fAPB2 = fHCLK, fADCCLK = fAPB2/2, ADON bit in the ADC_CR2 register is set to 1. 5.3.6 External clock source characteristics High-speed external user clock generated from an external source The characteristics given in Table 19 result from tests performed using an high-speed external clock source, and under the ambient temperature and supply voltage conditions summarized in Table 8. 44/87 Doc ID 16455 Rev 6 STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB Table 19. Electrical characteristics High-speed external user clock characteristics Symbol Parameter Conditions Min Typ Max Unit 8 24 MHz fHSE_ext User external clock source frequency(1) 1 VHSEH OSC_IN input pin high level voltage(1) 0.7VDD VDD VHSEL OSC_IN input pin low level voltage(1) VSS 0.3VDD tw(HSE) tw(HSE) OSC_IN high or low time(1) 5 tr(HSE) tf(HSE) OSC_IN rise or fall time(1) V Cin(HSE) ns OSC_IN input capacitance(1) DuCy(HSE) Duty IL 20 5 cycle(1) pF 45 OSC_IN Input leakage current VSS VIN VDD 55 % 1 A 1. Guaranteed by design, not tested in production. Low-speed external user clock generated from an external source The characteristics given in Table 20 result from tests performed using an low-speed external clock source, and under the ambient temperature and supply voltage conditions summarized in Table 8. Table 20. Low-speed external user clock characteristics Symbol Parameter Conditions Min fLSE_ext User external clock source frequency(1) VLSEH OSC32_IN input pin high level voltage(1) VLSEL OSC32_IN input pin low level voltage(1) VSS tw(LSE) tw(LSE) OSC32_IN high or low time(1) 450 Typ Max Unit 32.768 1000 kHz 0.7VDD VDD V tr(LSE) tf(LSE) Cin(LSE) ns OSC32_IN rise or fall time(1) 50 OSC32_IN input capacitance(1) DuCy(LSE) Duty IL 0.3VDD 5 cycle(1) 30 OSC32_IN Input leakage current VSS VIN VDD pF 70 % 1 A 1. Guaranteed by design, not tested in production. Doc ID 16455 Rev 6 45/87 Electrical characteristics STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB Figure 18. High-speed external clock source AC timing diagram VHSEH 90% VHSEL 10% tr(HSE) tf(HSE) tW(HSE) tW(HSE) t THSE External clock source fHSE_ext OSC _IN IL STM32F10xxx ai14127b Figure 19. Low-speed external clock source AC timing diagram VLSEH 90% VLSEL 10% tr(LSE) tf(LSE) tW(LSE) OSC32_IN IL tW(LSE) t TLSE External clock source fLSE_ext STM32F10xxx ai14140c High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 24 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 21. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). 46/87 Doc ID 16455 Rev 6 STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB Table 21. HSE 4-24 MHz oscillator characteristics(1)(2) Symbol fOSC_IN RF Parameter Conditions Oscillator frequency RS = 30 i2 HSE driving current VDD = 3.3 V VIN = VSS with 30 pF load gm Oscillator transconductance Startup Startup time VDD is stabilized tSU(HSE) (5) Min Typ Max Unit 4 8 24 MHz Feedback resistor Recommended load capacitance versus equivalent serial resistance of the crystal (RS)(4) CL1 CL2(3) Electrical characteristics 200 k 30 pF 1 25 mA mA/V 2 ms 1. Resonator characteristics given by the crystal/ceramic resonator manufacturer. 2. Based on characterization, not tested in production. 3. It is recommended to use high-quality external ceramic capacitors in the 5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator. CL1 and CL2, are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2. 4. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a humid environment, due to the induced leakage and the bias condition change. However, it is recommended to take this point into account if the MCU is used in tough humidity conditions. 5. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer Figure 20. Typical application with an 8 MHz crystal Resonator with integrated capacitors CL1 fHSE OSC_IN 8 MH z resonator CL2 REXT(1) RF OSC_OU T Bias controlled gain STM32F10xxx ai14128b 1. REXT value depends on the crystal characteristics. Doc ID 16455 Rev 6 47/87 Electrical characteristics STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB Low-speed external clock generated from a crystal/ceramic resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 22. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Note: For CL1 and CL2 it is recommended to use high-quality ceramic capacitors in the 5 pF to 15 pF range selected to match the requirements of the crystal or resonator. CL1 and CL2, are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. Load capacitance CL has the following formula: CL = CL1 x CL2 / (CL1 + CL2) + Cstray where Cstray is the pin capacitance and board or trace PCB-related capacitance. Typically, it is between 2 pF and 7 pF. Caution: To avoid exceeding the maximum value of CL1 and CL2 (15 pF) it is strongly recommended to use a resonator with a load capacitance CL 7 pF. Never use a resonator with a load capacitance of 12.5 pF. Example: if you choose a resonator with a load capacitance of CL = 6 pF, and Cstray = 2 pF, then CL1 = CL2 = 8 pF. Table 22. LSE oscillator characteristics (fLSE = 32.768 kHz)(1) Symbol RF Parameter Conditions Min Feedback resistor Typ Max 5 Unit M Recommended load capacitance versus equivalent serial resistance of the crystal (RS)(3) RS = 30 K 15 pF I2 LSE driving current VDD = 3.3 V VIN = VSS 1.4 A gm Oscillator transconductance CL1 CL2(2) tSU(LSE)(4) 5 VDD is stabilized Startup time A/V TA = 50 C 1.5 TA = 25 C 2.5 TA = 10 C 4 TA = 0 C 6 TA = -10 C 10 TA = -20 C 17 TA = -30 C 32 TA = -40 C 60 s 1. Based on characterization, not tested in production. 2. Refer to the note and caution paragraphs above the table. 3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small RS value for example MSIV-TIN32.768 kHz. Refer to crystal manufacturer for more details 4. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer 48/87 Doc ID 16455 Rev 6 STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB Electrical characteristics Figure 21. Typical application with a 32.768 kHz crystal Resonator with integrated capacitors CL1 fLSE OSC32_IN 32.768 KH z resonator RF Bias controlled gain STM32F10xxx OSC32_OU T CL2 ai14129b 5.3.7 Internal clock source characteristics The parameters given in Table 23 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 8. High-speed internal (HSI) RC oscillator Table 23. HSI oscillator characteristics(1) Symbol fHSI Parameter Conditions Frequency TA = -40 to 105 ACCHSI Accuracy of HSI oscillator TA = -10 to 85 TA = 0 to 70 TA = 25 C (3) IDD(HSI)(3) Typ Max 8 DuCy(HSI) Duty cycle tsu(HSI) Min HSI oscillator startup time HSI oscillator power consumption C(2) C(2) C(2) Unit MHz 45 55 % -2.4 2.5 % -2.2 1.3 % -1.9 1.3 % -1 1 % 1 2 s 100 A 80 1. VDD = 3.3 V, TA = -40 to 105 C C unless otherwise specified. 2. Based on characterization, not tested in production. 3. Guaranteed by design. Not tested in production Doc ID 16455 Rev 6 49/87 Electrical characteristics STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB Low-speed internal (LSI) RC oscillator Table 24. LSI oscillator characteristics (1) Symbol fLSI Frequency fLSI(T) tsu(LSI) Parameter (2) Temperature-related frequency drift (3) LSI oscillator startup time (3) LSI oscillator power consumption IDD(LSI) Min Typ Max Unit 30 40 60 kHz 9 % 85 s 1.2 A -9 0.65 1. VDD = 3 V, TA = -40 to 105 C C unless otherwise specified. 2. Based on characterization, not tested in production. 3. Guaranteed by design, not tested in production. Wakeup time from low-power mode The wakeup times given in Table 25 are measured on a wakeup phase with an 8-MHz HSI RC oscillator. The clock source used to wake up the device depends from the current operating mode: Stop or Standby mode: the clock source is the RC oscillator Sleep mode: the clock source is the clock that was set before entering Sleep mode. All timings are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 8. Table 25. Low-power mode wakeup timings Symbol tWUSLEEP(1) tWUSTOP(1) tWUSTDBY(1) Parameter Typ Unit Wakeup from Sleep mode 1.8 s Wakeup from Stop mode (regulator in run mode) 3.6 Wakeup from Stop mode (regulator in low-power mode) 5.4 Wakeup from Standby mode 50 s s 1. The wakeup times are measured from the wakeup event to the point at which the user application code reads the first instruction. 50/87 Doc ID 16455 Rev 6 STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB 5.3.8 Electrical characteristics PLL characteristics The parameters given in Table 26 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 8. Table 26. PLL characteristics Value Symbol Parameter Unit Min(1) Typ Max(1) PLL input clock(2) 1 8.0 24 MHz PLL input clock duty cycle 40 60 % fPLL_OUT PLL multiplier output clock 16 24 MHz tLOCK PLL lock time 200 s Jitter Cycle-to-cycle jitter 300 ps fPLL_IN 1. Based on device characterization, not tested in production. 2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with the range defined by fPLL_OUT. Doc ID 16455 Rev 6 51/87 Electrical characteristics 5.3.9 STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB Memory characteristics Flash memory The characteristics are given at TA = -40 to 105 C unless otherwise specified. Table 27. Flash memory characteristics Symbol Parameter Conditions Min(1) Typ Max(1) Unit tprog 16-bit programming time TA = -40 to +105 C 40 52.5 70 s tERASE Page (1 KB) erase time TA = -40 to +105 C 20 40 ms Mass erase time TA = -40 to +105 C 20 40 ms Read mode fHCLK = 24 MHz, VDD = 3.3 V 20 mA Write / Erase modes fHCLK = 24 MHz, VDD = 3.3 V 5 mA Power-down mode / Halt, VDD = 3.0 to 3.6 V 50 A 3.6 V tME IDD Vprog Supply current Programming voltage 2 1. Guaranteed by design, not tested in production. Table 28. Flash memory endurance and data retention Value Symbol NEND tRET Parameter Endurance Conditions TA = -40 to +85 C (6 suffix versions) TA = -40 to +105 C (7 suffix versions) 10 1 kcycle(2) at TA = 85 C 30 Data retention 1 kcycle(2) at TA = 105 C 10 kcycles(2) at TA = 55 C 1. Based on characterization not tested in production. 2. Cycling performed over the whole temperature range. 52/87 Min(1) Doc ID 16455 Rev 6 10 20 Unit Typ Max kcycles Years STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB 5.3.10 Electrical characteristics EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (Electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs: Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard. FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in Table 29. They are based on the EMS levels and classes defined in application note AN1709. Table 29. EMS characteristics Symbol Parameter Conditions Level/Class VFESD Voltage limits to be applied on any I/O pin to induce a functional disturbance VDD = 3.3 V, TA = +25 C, fHCLK = 24 MHz, LQFP100 package, conforms to IEC 61000-4-2 2B VEFTB VDD = 3.3 V, TA = +25 C, Fast transient voltage burst limits to be fHCLK = 24 MHz, LQFP100 applied through 100 pF on VDD and VSS pins package, conforms to to induce a functional disturbance IEC 61000-4-4 4A Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and pre qualification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as: Corrupted program counter Unexpected reset Critical Data corruption (control registers...) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Doc ID 16455 Rev 6 53/87 Electrical characteristics STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB Electromagnetic Interference (EMI) The electromagnetic field emitted by the device is monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with IEC 61967-2 standard which specifies the test board and the pin loading. Table 30. EMI characteristics Symbol Parameter SEMI 5.3.11 Peak level Monitored frequency band Conditions VDD = 3.6 V, TA = 25C, LQFP100 package compliant with SAE J1752/3 Max vs. [fHSE/fHCLK] Unit 8/24 MHz 0.1 MHz to 30 MHz 9 30 MHz to 130 MHz 16 130 MHz to 1GHz 19 SAE EMI Level 4 dBV - Absolute maximum ratings (electrical sensitivity) Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts x (n+1) supply pins). This test conforms to the JESD22-A114/C101 standard. Table 31. ESD absolute maximum ratings Symbol Ratings Conditions Class Maximum Unit value(1) VESD(HBM) Electrostatic discharge voltage (human body model) TA = +25 C conforming to JESD22-A114 2 2000 VESD(CDM) Electrostatic discharge TA = +25 C voltage (charge device model) conforming to JESD22-C101 II 500 V 1. Based on characterization results, not tested in production. Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance: A supply overvoltage is applied to each power supply pin A current injection is applied to each input, output and configurable I/O pin These tests are compliant with EIA/JESD78 IC latch-up standard. Table 32. Symbol LU 54/87 Electrical sensitivities Parameter Static latch-up class Conditions TA = +105 C conforming to JESD78 Doc ID 16455 Rev 6 Class II level A STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB 5.3.12 Electrical characteristics I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDD (for standard, 3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization. Functional susceptibilty to I/O current injection While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures. The failure is indicated by an out of range parameter: ADC error above a certain limit (>5 LSB TUE), out of spec current injection on adjacent pins or other functional failure (for example reset, oscillator frequency deviation). The test results are given in Table 33 Table 33. I/O current injection susceptibility Functional susceptibility Symbol IINJ Description Negative injection Positive injection Injected current on OSC_IN32, OSC_OUT32, PA4, PA5, PC13 -0 +0 Injected current on all FT pins -5 +0 Injected current on any other pin -5 +5 Doc ID 16455 Rev 6 Unit mA 55/87 Electrical characteristics 5.3.13 STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 34 are derived from tests performed under the conditions summarized in Table 8. All I/Os are CMOS and TTL compliant. Table 34. Symbol VIL VIH Vhys Ilkg I/O static characteristics Parameter Conditions Min Typ Max Standard I/O input low level voltage -0.3 0.28*(VDD-2 V)+0.8 V I/O FT(1) input low level voltage -0.3 0.32*(VDD-2 V)+0.75 V Standard I/O input high level voltage 0.41*(VDD-2 V) +1.3 V VDD+0.3 I/O FT(1) input high level voltage Unit V VDD > 2 V 5.5 0.42*(VDD-2)+1 V VDD 2 V 5.2 Standard I/O Schmitt trigger voltage hysteresis(2) 200 mV I/O FT Schmitt trigger voltage hysteresis(2) 5% VDD(3) mV Input leakage current(4) VSS VIN VDD Standard I/Os 1 A VIN = 5 V I/O FT 3 RPU Weak pull-up equivalent resistor(5) VIN = VSS 30 40 50 k RPD Weak pull-down equivalent resistor(5) VIN = VDD 30 40 50 k CIO I/O pin capacitance 5 pF 1. FT = 5V tolerant. To sustain a voltage higher than VDD+0.3 the internal pull-up/pull-down resistors must be disabled. 2. Hysteresis voltage between Schmitt trigger switching levels. Guaranteed by design, not tested in production. 3. With a minimum of 100 mV. 4. Leakage could be higher than max. if negative current is injected on adjacent pins. 5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This PMOS/NMOS contribution to the series resistance is minimum (~10% order). All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements is shown in Figure 22 and Figure 23 for standard I/Os, and in Figure 24 and Figure 25 for 5 V tolerant I/Os. 56/87 Doc ID 16455 Rev 6 STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB Electrical characteristics Figure 22. Standard I/O input characteristics - CMOS port 6)(6), 6 6 $$ ENT 6 )( #-/3 7)(MIN 7),MAX 6 6 )( $$ QUIREM NDARD RE 6 6), $$ 6 $$ IREMENT 6 ), RD REQU #-/3 STANDA )NPUT RANGE NOT GUARANTEED STA 6$$ 6 AIB Figure 23. Standard I/O input characteristics - TTL port 6)(6), 6 7)(MIN 44, REQUIREMENTS 6)( 6 6 6 )( $$ )NPUT RANGE NOT GUARANTEED 7),MAX 6 ),6 $$ 44, REQUIREMENTS 6),6 6$$ 6 AI Doc ID 16455 Rev 6 57/87 Electrical characteristics STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB Figure 24. 5 V tolerant I/O input characteristics - CMOS port 6)(6), 6 6 $$ TS 6 )( UIREMEN ARD REQ 3 STAND #-/ 6 ),6 $$ T 6 ),6 $$ REQUIRMEN /3 STANDARD #- 6 )(6 $$ )NPUT RANGE NOT GUARANTEED 6$$ 6 6$$ AIB Figure 25. 5 V tolerant I/O input characteristics - TTL port 6)(6), 6 44, REQUIREMENT 6 )(6 6 6 )( $$ 7)(MIN 7),MAX )NPUT RANGE NOT GUARANTEED 6 ), 6 $$ 44, REQUIREMENTS 6 ),6 6$$ 6 AI Output driving current The GPIOs (general-purpose inputs/outputs) can sink or source up to 8 mA, and sink or source up to 20 mA (with a relaxed VOL/VOH). In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 5.2: 58/87 The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating IVDD (see Table 6). The sum of the currents sunk by all the I/Os on VSS plus the maximum Run consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating IVSS (see Table 6). Doc ID 16455 Rev 6 STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB Electrical characteristics Output voltage levels Unless otherwise specified, the parameters given in Table 35 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 8. All I/Os are CMOS and TTL compliant. Table 35. Output voltage characteristics Symbol Parameter VOL(1) VOH (3) VOL(1) VOH (3) VOL(1) VOH (3) VOL(1) VOH (3) Output Low level voltage for an I/O pin when 8 pins are sunk at the same time Output High level voltage for an I/O pin when 8 pins are sourced at the same time Output low level voltage for an I/O pin when 8 pins are sunk at the same time Output high level voltage for an I/O pin when 8 pins are sourced at the same time Output low level voltage for an I/O pin when 8 pins are sunk at the same time Output high level voltage for an I/O pin when 8 pins are sourced at the same time Output low level voltage for an I/O pin when 8 pins are sunk at the same time Output high level voltage for an I/O pin when 8 pins are sourced at the same time Conditions CMOS port(2) IIO = +8 mA, 2.7 V < VDD < 3.6 V TTL port(2) IIO = +8 mA 2.7 V < VDD < 3.6 V IIO = +20 mA(4) 2.7 V < VDD < 3.6 V IIO = +6 mA(4) 2 V < VDD < 2.7 V Min Max Unit 0.4 V VDD-0.4 0.4 V 2.4 1.3 V VDD-1.3 0.4 V VDD-0.4 1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 6 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52. 3. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 6 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. 4. Based on characterization data, not tested in production. Doc ID 16455 Rev 6 59/87 Electrical characteristics STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 26 and Table 36, respectively. Unless otherwise specified, the parameters given in Table 36 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 8. Table 36. MODEx [1:0] bit value(1) I/O AC characteristics(1) Symbol Parameter fmax(IO)out Maximum frequency(2) 10 tf(IO)out Output high to low level fall time tr(IO)out Output low to high level rise time fmax(IO)out Maximum frequency(2) 01 tf(IO)out Output high to low level fall time tr(IO)out Output low to high level rise time fmax(IO)out Maximum frequency(2) tf(IO)out Output high to low level fall time 11 tr(IO)out - tEXTIpw Output low to high level rise time Conditions CL = 50 pF, VDD = 2 V to 3.6 V Max Unit 2(3) MHz 125(3) CL = 50 pF, VDD = 2 V to 3.6 V ns (3) 125 CL= 50 pF, VDD = 2 V to 3.6 V 10(3) MHz 25(3) CL= 50 pF, VDD = 2 V to 3.6 V ns 25(3) CL = 50 pF, VDD = 2 V to 3.6 V 24 CL = 30 pF, VDD = 2.7 V to 3.6 V 5(3) CL = 50 pF, VDD = 2.7 V to 3.6 V 8(3) CL = 50 pF, VDD = 2 V to 2.7 V 12(3) CL = 30 pF, VDD = 2.7 V to 3.6 V 5(3) CL = 50 pF, VDD = 2.7 V to 3.6 V 8(3) CL = 50 pF, VDD = 2 V to 2.7 V 12(3) Pulse width of external signals detected by the EXTI controller 10(3) MHz ns ns 1. The I/O speed is configured using the MODEx[1:0] bits. Refer to the STM32F10xxx reference manual for a description of GPIO Port configuration register. 2. The maximum frequency is defined in Figure 26. 3. Guaranteed by design, not tested in production. 60/87 Doc ID 16455 Rev 6 STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB Electrical characteristics Figure 26. I/O AC characteristics definition 90% 10% 50% 50% 90% 10% tr(I O)out EXT ERNAL OUTPUT ON 50pF tr(I O)out T Maximum frequency is achieved if (tr + tf) 2/3)T and if the duty cycle is (45-55%) when loaded by 50pF ai14131 5.3.14 NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 34). Unless otherwise specified, the parameters given in Table 37 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 8. Table 37. NRST pin characteristics Symbol Parameter VIL(NRST)(1) VIH(NRST) (1) Conditions Min -0.5 0.8 NRST Input high level voltage 2 VDD+0.5 Unit V Weak pull-up equivalent resistor(2) RPU Max NRST Input low level voltage NRST Schmitt trigger voltage hysteresis Vhys(NRST) Typ VF(NRST)(1) NRST Input filtered pulse VNF(NRST)(1) NRST Input not filtered pulse 200 VIN = VSS 30 40 mV 50 k 100 ns 300 ns 1. Guaranteed by design, not tested in production. 2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10% order). Figure 27. Recommended NRST pin protection 6$$ %XTERNAL RESET CIRCUIT .234 205 )NTERNAL RESET &ILTER & 34-&X AID 1. The reset network protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 37. Otherwise the reset will not be taken into account by the device. Doc ID 16455 Rev 6 61/87 Electrical characteristics 5.3.15 STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB TIMx characteristics The parameters given in Table 38 are guaranteed by design. Refer to Section 5.3.12: I/O current injection characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 38. Symbol TIMx characteristics Conditions(1) Parameter tres(TIM) Timer resolution time fEXT Timer external clock frequency on CHx(2) ResTIM tCOUNTER fTIMxCLK = 24 MHz fTIMxCLK = 24 MHz Min tTIMxCLK 41.7 ns 0 fTIMxCLK/2 MHz 0 12 MHz 16 bit 65536 tTIMxCLK 2730 s tMAX_COUNT Maximum possible count 65536 x 65536 tTIMxCLK 178 s 1 fTIMxCLK = 24 MHz fTIMxCLK = 24 MHz Unit 1 Timer resolution 16-bit counter clock period when the internal clock is selected Max 1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3, TIM4, TIM15, TIM16 and TIM17 timers. 2. CHx is used as a general term to refer to CH1 to CH4 for TIM1, TIM2, TIM3 and TIM4, to the CH1 to CH2 for TIM15, and to CH1 for TIM16 and TIM17. 5.3.16 Communications interfaces I2C interface characteristics Unless otherwise specified, the parameters given in Table 39 are derived from tests performed under the ambient temperature, fPCLK1 frequency and VDD supply voltage conditions summarized in Table 8. The STM32F100xx value line I2C interface meets the requirements of the standard I2C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not "true" open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present. The I2C characteristics are described in Table 39. Refer also to Section 5.3.12: I/O current injection characteristics for more details on the input/output alternate function characteristics (SDA and SCL). 62/87 Doc ID 16455 Rev 6 STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB Table 39. Electrical characteristics I2C characteristics Standard mode I2C(1) Fast mode I2C(1)(2) Symbol Parameter Unit Min Max Min tw(SCLL) SCL clock low time 4.7 1.3 tw(SCLH) SCL clock high time 4.0 0.6 tsu(SDA) SDA setup time 250 100 (3) 0(4) Max s 900(3) th(SDA) SDA data hold time tr(SDA) tr(SCL) SDA and SCL rise time 1000 300 tf(SDA) tf(SCL) SDA and SCL fall time 300 300 th(STA) Start condition hold time 4.0 0.6 tsu(STA) Repeated Start condition setup time 4.7 0.6 tsu(STO) Stop condition setup time 4.0 0.6 s tw(STO:STA) Stop to Start condition time (bus free) 4.7 1.3 s Cb Capacitive load for each bus line 0 ns s 400 400 pF 1. Guaranteed by design, not tested in production. 2. fPCLK1 must be higher than 2 MHz to achieve standard mode I2C frequencies. It must be higher than 4 MHz to achieve fast mode I2C frequencies. It must be a multiple of 10 MHz to reach the 400 kHz maximum I2C fast mode clock. 3. The maximum hold time of the Start condition only has to be met if the interface does not stretch the low period of SCL signal. 4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL. Doc ID 16455 Rev 6 63/87 Electrical characteristics STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB Figure 28. I2C bus AC waveforms and measurement circuit(1) 6$$ K 6$$ K )# BUS 34-&X 3$! 3#, 3TART REPEATED 3TART 3TART TSU34! 3$! TF3$! TR3$! TH34! TSU3$! TW3#,, TSU34/34! 3TOP TH3$! 3#, TW3#,( TR3#, TSU34/ TF3#, AID 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. Table 40. SCL frequency (fPCLK1= 24 MHz, VDD = 3.3 V)(1)(2) I2C_CCR value fSCL (kHz)(3) RP = 4.7 k 400 0x8011 300 0x8016 200 0x8021 100 0x0064 50 0x00C8 20 0x01F4 1. RP = External pull-up resistance, fSCL = I2C speed, 2. For speeds around 400 kHz, the tolerance on the achieved speed is of 2%. For other speed ranges, the tolerance on the achieved speed 1%. These variations depend on the accuracy of the external components used to design the application. 3. Guaranteed by design, not tested in production. 64/87 Doc ID 16455 Rev 6 STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB Electrical characteristics SPI interface characteristics Unless otherwise specified, the parameters given in Table 41 are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 8. Refer to Section 5.3.12: I/O current injection characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 41. Symbol fSCK 1/tc(SCK) SPI characteristics Parameter Conditions Min 12 Slave mode 12 8 ns 70 % MHz SPI clock rise and fall time Capacitive load: C = 30 pF DuCy(SCK) SPI slave input clock duty cycle Slave mode 30 tsu(NSS)(1) NSS setup time Slave mode 4tPCLK th(NSS)(1) NSS hold time Slave mode 2tPCLK SCK high and low time Master mode, fPCLK = 24 MHz, presc = 4 50 Master mode 5 Slave mode 5 Master mode 5 Slave mode 4 tsu(MI) (1) tsu(SI)(1) th(MI) ta(SO) (1)(2) 60 Data input setup time (1) th(SI)(1) Data input hold time Data output access time Slave mode, fPCLK = 24 MHz tdis(SO)(1)(3) Data output disable time Slave mode ns 0 3tPCLK 2 10 (1) Data output valid time Slave mode (after enable edge) 25 tv(MO)(1) Data output valid time Master mode (after enable edge) 5 tv(SO) th(SO)(1) th(MO)(1) Unit Master mode SPI clock frequency tr(SCK) tf(SCK) tw(SCKH)(1) tw(SCKL)(1) Max Data output hold time Slave mode (after enable edge) 15 Master mode (after enable edge) 2 1. Based on characterization, not tested in production. 2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z Doc ID 16455 Rev 6 65/87 Electrical characteristics STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB Figure 29. SPI timing diagram - slave mode and CPHA = 0 NSS input tc(SCK) th(NSS) SCK Input tSU(NSS) CPHA= 0 CPOL=0 tw(SCKH) tw(SCKL) CPHA= 0 CPOL=1 tv(SO) ta(SO) MISO OUT P UT tr(SCK) tf(SCK) th(SO) MS B O UT BI T6 OUT tdis(SO) LSB OUT tsu(SI) MOSI I NPUT B I T1 IN M SB IN LSB IN th(SI) ai14134c Figure 30. SPI timing diagram - slave mode and CPHA = 1(1) NSS input SCK Input tSU(NSS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 tc(SCK) tw(SCKH) tw(SCKL) tv(SO) ta(SO) MISO OUT P UT MS B O UT tsu(SI) MOSI I NPUT th(NSS) th(SO) BI T6 OUT tr(SCK) tf(SCK) tdis(SO) LSB OUT th(SI) B I T1 IN M SB IN LSB IN ai14135 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. 66/87 Doc ID 16455 Rev 6 STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB Electrical characteristics Figure 31. SPI timing diagram - master mode(1) High NSS input SCK Input SCK Input tc(SCK) CPHA= 0 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=0 CPHA=1 CPOL=1 tsu(MI) MISO INP UT tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) MS BIN BI T6 IN LSB IN th(MI) MOSI OUTUT M SB OUT B I T1 OUT tv(MO) LSB OUT th(MO) ai14136 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. HDMI consumer electronics control (CEC) Refer to Section 5.3.12: I/O current injection characteristics for more details on the input/output alternate function characteristics. 5.3.17 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 42 are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 8. Note: It is recommended to perform a calibration after each power-up. Doc ID 16455 Rev 6 67/87 Electrical characteristics Table 42. ADC characteristics Symbol Parameter STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB Conditions Min Typ Max Unit VDDA Power supply 2.4 3.6 V VREF+ Positive reference voltage 2.4 VDDA V IVREF Current on the VREF input pin 220(1) A fADC ADC clock frequency 0.6 12 MHz fS(2) Sampling rate 0.05 1 MHz 823 kHz 17 1/fADC VREF+ V 50 k 160(1) fADC = 12 MHz fTRIG(2) External trigger frequency VAIN(3) Conversion voltage range RAIN(2) External input impedance RADC(2) Sampling switch resistance 1 k CADC(2) Internal sample and hold capacitor 8 pF tCAL(2) Calibration time 0 (VSSA tied to ground) See Equation 1 and Table 43 for details fADC = 12 MHz tlat(2) Injection trigger conversion latency fADC = 12 MHz tlatr(2) Regular trigger conversion latency fADC = 12 MHz tS(2) Sampling time fADC = 12 MHz tSTAB(2) Power-up time tCONV(2) Total conversion time (including sampling time) 5.9 s 83 1/fADC 0.214 (4) 3 1/fADC 0.143 s 2(4) 1/fADC 0.125 17.1 s 1.5 239.5 1/fADC 1 s 21 s 0 fADC = 12 MHz s 1.17 0 14 to 252 (tS for sampling +12.5 for successive approximation) 1/fADC 1. Based on characterization results, not tested in production. 2. Guaranteed by design, not tested in production. 3. In devices delivered in LQFP packages, VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA. Devices that come in the TFBGA64 package have a VREF+ pin but no VREF- pin (VREF- is internally connected to VSSA), see Table 4: STM32F100xx pin definitions and Figure 6. 4. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 42. Equation 1: RAIN max formula: TS R AIN < ------------------------------------------------------------- - R ADC N+2 f ADC x C ADC x ln ( 2 ) 68/87 Doc ID 16455 Rev 6 STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB Electrical characteristics The above formula (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution). Table 43. RAIN max for fADC = 12 MHz(1) Ts (cycles) tS (s) RAIN max (k) 1.5 0.125 0.4 7.5 0.625 5.9 13.5 1.125 11.4 28.5 2.375 25.2 41.5 3.45 37.2 55.5 4.625 50 71.5 5.96 NA 239.5 20 NA 1. Guaranteed by design, not tested in production. Table 44. Symbol ADC accuracy - limited test conditions(1)(2) Parameter ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error Test conditions Typ Max fPCLK2 = 24 MHz, fADC = 12 MHz, RAIN < 10 k, VDDA = 3 V to 3.6 V VREF+ = VDDA TA = 25 C Measurements made after ADC calibration 1.3 2.2 1 1.5 0.5 1.5 0.7 1 0.8 1.5 Test conditions Typ Max fPCLK2 = 24 MHz, fADC = 12 MHz, RAIN < 10 k, VDDA = 2.4 V to 3.6 V TA = Full operating range Measurements made after ADC calibration 2 5 1.5 2.5 1.5 3 1 2 1.5 3 Unit LSB 1. ADC DC accuracy values are measured after internal calibration. 2. Based on characterization, not tested in production. Table 45. Symbol ADC accuracy(1) (2) (3) Parameter ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error Unit LSB 1. ADC DC accuracy values are measured after internal calibration. 2. Better performance could be achieved in restricted VDD, frequency, VREF and temperature ranges. 3. Based on characterization, not tested in production. Note: ADC accuracy vs. negative injection current: Injecting a negative current on any of the standard (non-robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to Doc ID 16455 Rev 6 69/87 Electrical characteristics STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative currents. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 5.3.12 does not affect the ADC accuracy. Figure 32. ADC accuracy characteristics V V [1LSBIDEAL = REF+ (or DDA depending on package)] 4096 4096 EG (1) Example of an actual transfer curve (2) The ideal transfer curve (3) End point correlation line 4095 4094 4093 (2) ET 7 (1) 6 5 4 ET=Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO=Offset Error: deviation between the first actual transition and the first ideal one. EG=Gain Error: deviation between the last ideal transition and the last actual one. ED=Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL=Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line. (3) EO EL 3 ED 2 1 LSBIDEAL 1 0 1 VSSA 2 3 4 5 6 7 4093 4094 4095 4096 VDDA ai14395b Figure 33. Typical connection diagram using the ADC STM32F10xxx VDD RAIN(1) Sample and hold ADC converter VT 0.6 V RADC(1) AINx VT 0.6 V VAIN Cparasitic IL1 A 12-bit converter CADC(1) ai14139d 1. Refer to Table 42 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced. General PCB design guidelines Power supply decoupling should be performed as shown in Figure 34 or Figure 35, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. 70/87 Doc ID 16455 Rev 6 STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB Electrical characteristics Figure 34. Power supply and reference decoupling (VREF+ not connected to VDDA) STM32F10xxx V REF+ 1 F // 10 nF V DDA 1 F // 10 nF V SSA/V REF- ai14380b 1. VREF+ is available on 100-pin packages and on TFBGA64 packages. VREF- is available on 100-pin packages only. Figure 35. Power supply and reference decoupling (VREF+ connected to VDDA) STM32F10xxx VREF+/VDDA 1 F // 10 nF VREF-/VSSA ai14381b 1. VREF+ and VREF- inputs are available only on 100-pin packages. Doc ID 16455 Rev 6 71/87 Electrical characteristics STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB 5.3.18 DAC electrical specifications Table 46. DAC characteristics Symbol Parameter Min Typ Max(1) Unit VDDA Analog supply voltage 2.4 3.6 V VREF+ Reference supply voltage 2.4 3.6 V Ground 0 0 V Resistive load with buffer ON 5 VSSA RLOAD (2) Comments VREF+ must always be below VDDA k RO(1) Impedance output with buffer OFF 15 k When the buffer is OFF, the Minimum resistive load between DAC_OUT and VSS to have a 1% accuracy is 1.5 M CLOAD(1) Capacitive load 50 pF Maximum capacitive load at DAC_OUT pin (when the buffer is ON). DAC_OUT Lower DAC_OUT voltage with buffer min(1) ON 0.2 V DAC_OUT Higher DAC_OUT voltage with buffer ON max(1) DAC_OUT Lower DAC_OUT voltage with buffer min(1) OFF DAC_OUT Higher DAC_OUT voltage with buffer max(1) OFF IDDVREF+ IDDA DNL(3) INL(3) 72/87 DAC DC current consumption in quiescent mode (Standby mode) VDDA - V 0.2 0.5 mV VREF+ V - 1LSB It gives the maximum output excursion of the DAC. 220 A With no load, worst code (0xF1C) at VREF+ = 3.6 V in terms of DC consumption on the inputs 380 A With no load, middle code (0x800) on the inputs 480 A With no load, worst code (0xF1C) at VREF+ = 3.6 V in terms of DC consumption on the inputs 0.5 LSB Given for the DAC in 10-bit configuration 2 LSB Given for the DAC in 12-bit configuration 1 LSB Given for the DAC in 10-bit configuration 4 LSB Given for the DAC in 12-bit configuration DAC DC current consumption in quiescent mode (Standby mode) Differential non linearity Difference between two consecutive code-1LSB) Integral non linearity (difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 1023) It gives the maximum output excursion of the DAC. It corresponds to 12-bit input code (0x0E0) to (0xF1C) at VREF+ = 3.6 V and (0x155) and (0xEAB) at VREF+ = 2.4 V Doc ID 16455 Rev 6 STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB Table 46. DAC characteristics (continued) Symbol Offset(3) Gain error(3) Parameter Min Unit 10 mV Given for the DAC in 12-bit configuration 3 LSB Given for the DAC in 10-bit at VREF+ = 3.6 V 12 LSB Given for the DAC in 12-bit at VREF+ = 3.6 V 0.5 % Given for the DAC in 12bit configuration 4 s CLOAD 50 pF, RLOAD 5 k 1 MS/s CLOAD 50 pF, RLOAD 5 k 6.5 10 s CLOAD 50 pF, RLOAD 5 k input code between lowest and highest possible ones. -67 -40 dB No RLOAD, CLOAD = 50 pF Gain error 3 Max frequency for a correct DAC_OUT change when small variation in the input code (from code i to i+1LSB) Wakeup time from off state (Setting tWAKEUP(3) the ENx bit in the DAC Control register) PSRR+ (1) Max(1) Typ Offset error (difference between measured value at Code (0x800) and the ideal value = VREF+/2) Settling time (full scale: for a 10-bit input code transition between the tSETTLING( lowest and the highest input codes 3) when DAC_OUT reaches final value 1LSB Update rate(3) Electrical characteristics Power supply rejection ratio (to VDDA) (static DC measurement Comments 1. Guaranteed by characterization, not tested in production. 2. Guaranteed by design, not tested in production. 3. Guaranteed by characterization, not tested in production. Figure 36. 12-bit buffered /non-buffered DAC Buffered/Non-buffered DAC Buffer(1) R LOAD 12-bit digital to analog converter DACx_OUT C LOAD ai17157 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register. Doc ID 16455 Rev 6 73/87 Electrical characteristics STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB 5.3.19 Temperature sensor characteristics Table 47. TS characteristics Symbol TL(1) Parameter Min VSENSE linearity with temperature (1) Typ Max Unit 1 2 C Average slope 4.0 4.3 4.6 mV/C V25(1) Voltage at 25C 1.32 1.41 1.50 V tSTART(2) Startup time 10 s TS_temp(3)(2) ADC sampling time when reading the temperature 17.1 s Avg_Slope 4 1. Guaranteed by characterization, not tested in production. 2. Guaranteed by design, not tested in production. 3. Shortest sampling time can be determined in the application by multiple iterations. 74/87 Doc ID 16455 Rev 6 STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB 6 Package characteristics 6.1 Package mechanical data Package characteristics In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. Doc ID 16455 Rev 6 75/87 Package characteristics STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB Figure 37. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package outline(1) Figure 38. Recommended footprint(1)(2) 0.25 mm 0.10 inch GAGE PLANE 75 k 51 D L D1 76 50 0.5 L1 D3 51 75 C 0.3 76 50 16.7 14.3 b E3 E1 E 100 26 1.2 1 100 26 Pin 1 1 identification 25 12.3 25 ccc C 16.7 e A1 ai14906 A2 A SEATING PLANE C 1L_ME 1. Drawing is not to scale. 2. Dimensions are in millimeters. Table 48. LQPF100 - 14 x 14 mm, 100-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ A Max Typ 1.60 A1 0.05 A2 1.35 b 0.17 c 0.09 D 15.80 D1 13.80 D3 Max 0.063 0.15 0.002 1.40 1.45 0.0531 0.0551 0.0571 0.22 0.27 0.0067 0.0087 0.0106 0.2 0.0035 16.00 16.2 0.622 0.6299 0.6378 14.00 14.2 0.5433 0.5512 0.5591 12.00 0.0059 0.0079 0.4724 E 15.80 16.00 16.2 0.622 0.6299 0.6378 E1 13.80 14.00 14.2 0.5433 0.5512 0.5591 E3 12.00 e L k ccc 0.4724 0.50 0.45 L1 0.60 0.0197 0.75 0.0177 1.00 0 3.5 0.0236 0.0295 0.0394 7 0.08 0.0 3.5 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. 76/87 Min Doc ID 16455 Rev 6 7.0 STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB Figure 39. LQFP64 - 10 x 10 mm, 64 pin low-profile quad flat package outline(1) Package characteristics Figure 40. Recommended footprint(1)(2) D 48 33 ccc C D1 33 48 0.3 A A2 D3 49 32 0.5 32 49 12.7 10.3 b L1 10.3 E3 E1 E 64 1.2 L A1 17 K 1 16 64 7.8 17 Pin 1 identification 16 1 c 12.7 5W_ME ai14909 1. Drawing is not to scale. 2. Dimensions are in millimeters. Table 49. LQFP64 - 10 x 10 mm, 64-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ A Max Min Typ 1.60 A1 0.05 A2 1.35 b 0.17 c 0.09 Max 0.0630 0.15 0.0020 0.0059 1.40 1.45 0.0531 0.0551 0.0571 0.22 0.27 0.0067 0.0087 0.0106 0.20 0.0035 0.0079 D 12.00 0.4724 D1 10.00 0.3937 E 12.00 0.4724 E1 10.00 0.3937 e 0.50 0.0197 0 3.5 7 0 3.5 7 L 0.45 0.60 0.75 0.0177 0.0236 0.0295 L1 1.00 0.0394 Number of pins N 64 1. Values in inches are converted from mm and rounded to 4 decimal digits. Doc ID 16455 Rev 6 77/87 Package characteristics STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB Figure 41. TFBGA64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package outline B D D1 A A e A1 F H F G F E E1 E D C B A e 1 2 3 A1 ball pad corner A3 4 5 6 7 8 Ob (64 balls) A4 A2 Seating C plane Bottom view ME_R8 1. Drawing is not to scale. Table 50. TFBGA64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package mechanical data inches(1) millimeters Symbol Min Typ A A1 Max Min 1.200 0.150 Max 0.0472 0.0059 A2 0.785 0.0309 A3 0.200 0.0079 A4 0.600 0.0236 b 0.250 0.300 0.350 0.0098 0.0118 0.0138 D 4.850 5.000 5.150 0.1909 0.1969 0.2028 D1 E 3.500 4.850 5.000 0.1378 5.150 0.1909 0.1969 E1 3.500 0.1378 e 0.500 0.0197 F 0.750 0.0295 ddd 0.080 0.0031 eee 0.150 0.0059 fff 0.050 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. 78/87 Typ Doc ID 16455 Rev 6 0.2028 STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB Package characteristics Figure 42. Recommended PCB design rules for pads (0.5 mm pitch BGA) Pitch 0.5 mm D pad 0.27 mm Dsm 0.35 mm typ (depends on the soldermask registration tolerance) Solder paste 0.27 mm aperture diameter Dpad Dsm ai15495 1. Non solder mask defined (NSMD) pads are recommended 2. 4 to 6 mils solder paste screen printing process Doc ID 16455 Rev 6 79/87 Package characteristics STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB Figure 43. LQFP48 - 7 x 7 mm, 48-pin low-profile quad flat package outline(1) Figure 44. Recommended footprint(1)(2) Seating plane C A A2 A1 c b ccc 0.50 1.20 0.25 mm Gage plane C 36 D 0.30 25 37 24 D1 k D3 A1 L 25 36 9.70 0.20 7.30 5.80 L1 7.30 24 37 48 13 12 1 1.20 E3 E1 5.80 E 9.70 ai14911b 48 Pin 1 identification 13 1 12 5B_ME 1. Drawing is not to scale. 2. Dimensions are in millimeters. Table 51. LQFP48 - 7 x 7 mm, 48-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ A Max Typ 1.600 Max 0.0630 A1 0.050 0.150 0.0020 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 0.200 0.0035 D 8.800 9.000 9.200 0.3465 0.3543 0.3622 D1 6.800 7.000 7.200 0.2677 0.2756 0.2835 D3 5.500 0.0059 0.0079 0.2165 E 8.800 9.000 9.200 0.3465 0.3543 0.3622 E1 6.800 7.000 7.200 0.2677 0.2756 0.2835 E3 5.500 e L k ccc 0.2165 0.500 0.450 L1 0.600 0.0197 0.750 0.0177 1.000 0 3.5 0.0236 0.0295 0.0394 7 0.080 0 3.5 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. 80/87 Min Doc ID 16455 Rev 6 7 STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB 6.2 Package characteristics Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 8: General operating conditions on page 33. The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max x JA) Where: TA max is the maximum ambient temperature in C, JA is the package junction-to-ambient thermal resistance, in C/W, PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax), PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. PI/O max represents the maximum power dissipation on output pins where: PI/O max = (VOL x IOL) + ((VDD - VOH) x IOH), taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application. Table 52. Package thermal characteristics Symbol JA 6.2.1 Parameter Value Thermal resistance junction-ambient LQFP 100 - 14 x 14 mm / 0.5 mm pitch 46 Thermal resistance junction-ambient LQFP 64 - 10 x 10 mm / 0.5 mm pitch 45 Unit C/W Thermal resistance junction-ambient TFBGA64 - 5 x 5 mm / 0.5 mm pitch 65 Thermal resistance junction-ambient LQFP 48 - 7 x 7 mm / 0.5 mm pitch 55 Reference document JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org. Doc ID 16455 Rev 6 81/87 Package characteristics 6.2.2 STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in Table 53: Ordering information scheme. Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature. As applications do not commonly use the STM32F10xxx at maximum dissipation, it is useful to calculate the exact power consumption and junction temperature to determine which temperature range will be best suited to the application. The following examples show how to calculate the temperature range needed for a given application. Example: high-performance application Assuming the following application conditions: Maximum ambient temperature TAmax = 82 C (measured according to JESD51-2), IDDmax = 50 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low level with IOL = 8 mA, VOL= 0.4 V and maximum 8 I/Os used at the same time in output mode at low level with IOL = 20 mA, VOL= 1.3 V PINTmax = 50 mA x 3.5 V= 175 mW PIOmax = 20 x 8 mA x 0.4 V + 8 x 20 mA x 1.3 V = 272 mW This gives: PINTmax = 175 mW and PIOmax = 272 mW PDmax = 175 + 272 = 447 mW Thus: PDmax = 447 mW Using the values obtained in Table 52 TJmax is calculated as follows: - For LQFP64, 45 C/W TJmax = 82 C + (45 C/W x 447 mW) = 82 C + 20.1 C = 102.1 C This is within the range of the suffix 6 version parts (-40 < TJ < 105 C). In this case, parts must be ordered at least with the temperature range suffix 6 (see Table 53: Ordering information scheme). Example 2: High-temperature application Using the same rules, it is possible to address applications that run at high ambient temperatures with a low dissipation, as long as junction temperature TJ remains within the specified range. Assuming the following application conditions: Maximum ambient temperature TAmax = 115 C (measured according to JESD51-2), IDDmax = 20 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low level with IOL = 8 mA, VOL= 0.4 V PINTmax = 20 mA x 3.5 V= 70 mW PIOmax = 20 x 8 mA x 0.4 V = 64 mW This gives: PINTmax = 70 mW and PIOmax = 64 mW: PDmax = 70 + 64 = 134 mW Thus: PDmax = 134 mW 82/87 Doc ID 16455 Rev 6 STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB Package characteristics Using the values obtained in Table 52 TJmax is calculated as follows: - For LQFP100, 46 C/W TJmax = 115 C + (46 C/W x 134 mW) = 115 C + 6.2 C = 121.2 C This is within the range of the suffix 7 version parts (-40 < TJ < 125 C). In this case, parts must be ordered at least with the temperature range suffix 7 (see Table 53: Ordering information scheme). Figure 45. LQFP100 PD max vs. TA 700 PD (mW) 600 500 Suffix 6 400 Suffix 7 300 200 100 0 65 75 85 95 105 115 125 135 TA (C) Doc ID 16455 Rev 6 83/87 Ordering information scheme 7 STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB Ordering information scheme Table 53. Ordering information scheme Example: STM32 F 100 C 6 T 6 B xxx Device family STM32 = ARM-based 32-bit microcontroller Product type F = General-purpose Device subfamily 100 = value line Pin count C = 48 pins R = 64 pins V = 100 pins Flash memory size 4 = 16 Kbytes of Flash memory 6 = 32 Kbytes of Flash memory 8 = 64 Kbytes of Flash memory B = 128 Kbytes of Flash memory Package T = LQFP H = BGA Temperature range 6 = Industrial temperature range, -40 to 85 C 7 = Industrial temperature range, -40 to 105 C Internal code B Options xxx = programmed parts TR = tape and real For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office. 84/87 Doc ID 16455 Rev 6 STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB 8 Revision history Revision history Table 54. Document revision history Date Revision 12-Oct-2009 1 Initial release. 2 TFBGA64 package added (see Table 50 and Table 41). Note 5 modified in Table 4: STM32F100xx pin definitions. IINJ(PIN) modified in Table 6: Current characteristics. Conditions removed from Table 25: Low-power mode wakeup timings. Notes modified in Table 34: I/O static characteristics. Figure 27: Recommended NRST pin protection modified. Note modified in Table 39: I2C characteristics. Figure 28: I2C bus AC waveforms and measurement circuit(1) modified. Table 46: DAC characteristics modified. Figure 36: 12-bit buffered /non-buffered DAC added. TIM2, TIM3, TIM4 and TIM15, TIM16 and TIM17 updated. HDMI-CEC electrical characteristics added. Values added to: - Table 12: Maximum current consumption in Run mode, code with data processing running from Flash - Table 13: Maximum current consumption in Run mode, code with data processing running from RAM - Table 14: STM32F100xxB maximum current consumption in Sleep mode, code running from Flash or RAM - Table 15: Typical and maximum current consumptions in Stop and Standby modes - Table 18: Peripheral current consumption - Table 29: EMS characteristics - Table 30: EMI characteristics - Table 47: TS characteristics Section 5.3.12: I/O current injection characteristics modified. Added figures: - Figure 12: Maximum current consumption in Run mode versus frequency (at 3.6 V) - code with data processing running from RAM, peripherals enabled - Figure 13: Maximum current consumption in Run mode versus frequency (at 3.6 V) - code with data processing running from RAM, peripherals disabled - Figure 15: Typical current consumption in Stop mode with regulator in Run mode versus temperature at VDD = 3.3 V and 3.6 V - Figure 16: Typical current consumption in Stop mode with regulator in Low-power mode versus temperature at VDD = 3.3 V and 3.6 V - Figure 17: Typical current consumption in Standby mode versus temperature at VDD = 3.3 V and 3.6 V 26-Feb-2010 Changes Doc ID 16455 Rev 6 85/87 Revision history STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB Table 54. Document revision history (continued) Date Revision Changes 3 Revision history corrected. Updated Table 6: Current characteristics Values and note updated in Table 16: Typical current consumption in Run mode, code with data processing running from Flash and Table 17: Typical current consumption in Sleep mode, code running from Flash or RAM. Updated Table 15: Typical and maximum current consumptions in Stop and Standby modes Added Figure 14: Typical current consumption on VBAT with RTC on vs. temperature at different VBAT values Typical consumption for ADC1 corrected in Table 18: Peripheral current consumption. Maximum current consumption and Typical current consumption: frequency conditions corrected. Output driving current corrected. Updated Table 30: EMI characteristics fADC max corrected in Table 42: ADC characteristics. Small text changes. 06-May-2010 4 Updated Table 31: ESD absolute maximum ratings on page 54 and Table 32: Electrical sensitivities on page 54 Updated Table 44: ADC accuracy - limited test conditions on page 69 and Table 45: ADC accuracy on page 69 12-Jul-2010 5 Updated Table 24: LSI oscillator characteristics on page 50 Updated Table 44: ADC accuracy - limited test conditions on page 69 and Table 45: ADC accuracy on page 69 6 Updated Figure 2: Clock tree to add FLITF clock Updated footnotes below Table 5: Voltage characteristics on page 32 and Table 6: Current characteristics on page 33 Updated tw min in Table 19: High-speed external user clock characteristics on page 45 Updated startup time in Table 22: LSE oscillator characteristics (fLSE = 32.768 kHz) on page 48 Updated Table 23: HSI oscillator characteristics on page 49 Added Section 5.3.12: I/O current injection characteristics on page 55 Updated Table 34: I/O static characteristics on page 56 Corrected TTL and CMOS designations in Table 35: Output voltage characteristics on page 59 Removed note on remapped characteristics from Table 41: SPI characteristics on page 65 30-Mar-2010 04-Apr-2011 86/87 Doc ID 16455 Rev 6 STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB Please Read Carefully: Information in this document is provided solely in connection with ST products. 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The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. (c) 2011 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com Doc ID 16455 Rev 6 87/87