MC74HC4016DR2 - ON Semiconductor



SEMICONDUCTOR TECHNICAL DATA

1REV 6

 Motorola, Inc. 1995

10/95

"  #!

"!$ "!$

High–Performance Silicon–Gate CMOS

The MC54/74HC4016 utilizes silicon–gate CMOS technology to achieve

fast propagation delays, low ON resistances, and low OFF–channel leakage

current. This bilateral switch/multiplexer/demultiplexer controls analog and

digital voltages that may vary across the full power–supply range (from VCC

to GND).

The HC4016 is identical in pinout to the metal–gate CMOS MC14016 and

MC14066. Each device has four independent switches. The device has

been designed so that the ON resistances (RON) are much more linear over

input voltage than RON of metal–gate CMOS analog switches.

This device is identical in both function and pinout to the HC4066. The

ON/OFF Control inputs are compatible with standard CMOS outputs; with

pullup resistors, they are compatible with LSTTL outputs. For analog

switches with voltage–level translators, see the HC4316. For analog

switches with lower RON characteristics, use the HC4066.

•Fast Switching and Propagation Speeds

•High ON/OFF Output Voltage Ratio

•Low Crosstalk Between Switches

•Diode Protection on All Inputs/Outputs

•Wide Power–Supply Voltage Range (VCC – GND) = 2.0 to 12.0 Volts

•Analog Input Voltage Range (VCC – GND) = 2.0 to 12.0 Volts

•Improved Linearity and Lower ON Resistance over Input Voltage than

the MC14016 or MC14066

•Low Noise

•Chip Complexity: 32 FETs or 8 Equivalent Gates

LOGIC DIAGRAM

A ON/OFF CONTROL

B ON/OFF CONTROL

C ON/OFF CONTROL

D ON/OFF CONTROL

ANALOG

OUTPUTS/INPUTS

ANALOG INPUTS/OUTPUTS = XA, XB, XC, XD

PIN 14 = VCC

PIN 7 = GND



FUNCTION TABLE

PIN ASSIGNMENT

GND

C ON/OFF

CONTROL

B ON/OFF

CONTROL

105

D ON/OFF

CONTROL

A ON/OFF

CONTROL

VCC

On/Off Control State of

Input Analog Switch

L Off

H On

D SUFFIX

SOIC PACKAGE

CASE 751A–03

N SUFFIX

PLASTIC PACKAGE

CASE 646–06

ORDERING INFORMATION

MC54HCXXXXJ

MC74HCXXXXN

MC74HCXXXXD

Ceramic

Plastic

SOIC

J SUFFIX

CERAMIC PACKAGE

CASE 632–08

MC54/74HC4016

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MAXIMUM RATINGS*

ÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎ

Value

ÎÎÎ

Unit

ÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Positive DC Supply Voltage (Referenced to GND)

ÎÎÎÎÎÎ

– 0.5 to + 14.0

ÎÎÎ

VIS

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Analog Input Voltage (Referenced to GND)

ÎÎÎÎÎÎ

– 0.5 to VCC + 0.5

ÎÎÎ

Vin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Digital Input Voltage (Referenced to GND)

ÎÎÎÎÎÎ

– 1.5 to VCC + 1.5

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Current Into or Out of Any Pin

ÎÎÎÎÎÎ

± 25

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Power Dissipation in Still Air,Plastic or Ceramic DIP†

SOIC Package†

ÎÎÎÎÎÎ

750

500

ÎÎÎ

Tstg

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Storage Temperature

ÎÎÎÎÎÎ

– 65 to + 150

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Lead Temperature, 1 mm from Case for 10 Seconds

(Plastic DIP or SOIC Package)

(Ceramic DIP)

ÎÎÎÎÎÎ

260

300

ÎÎÎ

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/

C from 65

to 125

Ceramic DIP: – 10 mW/

C from 100

to 125

SOIC Package: – 7 mW/

C from 65

to 125

For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎ

Unit

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Positive DC Supply Voltage (Referenced to GND)

ÎÎÎ

2.0

ÎÎÎ

12.0

ÎÎÎ

ÎÎÎÎ

VIS

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Analog Input Voltage (Referenced to GND)

ÎÎÎ

GND

ÎÎÎ

VCC

ÎÎÎ

ÎÎÎÎ

Vin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Digital Input Voltage (Referenced to GND)

ÎÎÎ

GND

ÎÎÎ

VCC

ÎÎÎ

ÎÎÎÎ

VIO*

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Static or Dynamic Voltage Across Switch

ÎÎÎ

—

ÎÎÎ

1.2

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Operating Temperature, All Package Types

ÎÎÎ

– 55

ÎÎÎ

+ 125

ÎÎÎ

ÎÎÎÎ

tr, tf

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Input Rise and Fall Time, ON/OFF VCC = 2.0 V

Control Inputs (Figure 10) VCC = 4.5 V

VCC = 9.0 V

VCC = 12.0 V

ÎÎÎ

1000

500

400

250

ÎÎÎ

*For voltage drops across the switch greater than 1.2 V (switch on), excessive VCC current may

be drawn; i.e., the current out of the switch may contain both VCC and switch input components.

The reliability of the device will be unaffected unless the Maximum Ratings are exceeded.

DC ELECTRICAL CHARACTERISTICS Digital Section (Voltages Referenced to GND)

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎ

Guaranteed Limit

ÎÎÎ

Unit

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎÎ

VCC

ÎÎÎ

– 55 to

ÎÎÎÎ

125

ÎÎÎ

Unit

ÎÎÎÎ

VIH

ÎÎÎÎÎÎÎÎÎ

Minimum High–Level Voltage

ON/OFF Control Inputs

ÎÎÎÎÎÎÎÎÎ

Ron = per spec

ÎÎÎÎ

2.0

4.5

9.0

12.0

ÎÎÎ

1.5

3.15

6.3

8.4

ÎÎÎÎ

1.5

3.15

6.3

8.4

ÎÎÎÎ

1.5

3.15

6.3

8.4

ÎÎÎ

ÎÎÎÎ

VIL

ÎÎÎÎÎÎÎÎÎ

Maximum Low–Level Voltage

ON/OFF Control Inputs

ÎÎÎÎÎÎÎÎÎ

Ron = per spec

ÎÎÎÎ

2.0

4.5

9.0

12.0

ÎÎÎ

0.3

0.9

1.8

2.4

ÎÎÎÎ

0.3

0.9

1.8

2.4

ÎÎÎÎ

0.3

0.9

1.8

2.4

ÎÎÎ

ÎÎÎÎ

Iin

ÎÎÎÎÎÎÎÎÎ

Maximum Input Leakage Current,

ON/OFF Control Inputs

ÎÎÎÎÎÎÎÎÎ

Vin = VCC or GND

ÎÎÎÎ

12.0

ÎÎÎ

±0.1

ÎÎÎÎ

±1.0

ÎÎÎÎ

±1.0

ÎÎÎ

µA

ÎÎÎÎ

ICC

ÎÎÎÎÎÎÎÎÎ

Maximum Quiescent Supply

Current (per Package)

ÎÎÎÎÎÎÎÎÎ

Vin = VCC or GND

VIO = 0 V

ÎÎÎÎ

6.0

12.0

ÎÎÎ

ÎÎÎÎ

160

ÎÎÎ

µA

NOTE:Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

This device contains protection

circuitry to guard against damage

due to high static voltages or electric

fields. However, precautions must

be taken to avoid applications of any

voltage higher than maximum rated

voltages to this high–impedance cir-

cuit. For proper operation, Vin and

Vout should be constrained to the

range GND

(Vin or V out)

VCC.

Unused inputs must always be

tied to an appropriate logic voltage

level (e.g., either GND or VCC).

Unused outputs must be left open.

I/O pins must be connected to a

properly terminated line or bus.

MC54/74HC4016

High–Speed CMOS Logic Data

DL129 — Rev 6 3 MOTOROLA

DC ELECTRICAL CHARACTERISTICS Analog Section (Voltages Referenced to GND)

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎ

Guaranteed Limit

ÎÎÎ

Unit

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎÎ

VCC

ÎÎÎ

– 55 to

ÎÎÎÎ

125

ÎÎÎ

Unit

ÎÎÎÎ

Ron

ÎÎÎÎÎÎÎÎÎ

Maximum “ON” Resistance

ÎÎÎÎÎÎÎÎÎ

Vin = VIH

VIS = VCC to GND

2.0 mA (Figures 1, 2)

ÎÎÎÎ

2.0†

4.5

9.0

12.0

ÎÎÎ

—

320

170

ÎÎÎÎ

—

400

215

ÎÎÎÎ

—

480

255

ÎÎÎ

Ω

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

Vin = VIH

VIS = VCC or GND (Endpoints)

2.0 mA (Figures 1, 2)

ÎÎÎÎ

2.0

4.5

9.0

12.0

ÎÎÎ

—

180

135

ÎÎÎÎ

—

225

170

ÎÎÎÎ

—

270

205

ÎÎÎ

ÎÎÎÎ

∆Ron

ÎÎÎÎÎÎÎÎÎ

Maximum Difference in “ON”

Resistance Between Any Two

Channels in the Same Package

ÎÎÎÎÎÎÎÎÎ

Vin VIH

VIS = 1/2 (VCC – GND)

2.0 mA

ÎÎÎÎ

2.0

4.5

9.0

12.0

ÎÎÎ

—

ÎÎÎÎ

—

ÎÎÎÎ

—

ÎÎÎ

Ω

ÎÎÎÎ

Ioff

ÎÎÎÎÎÎÎÎÎ

Maximum Off–Channel Leakage

Current, Any One Channel

ÎÎÎÎÎÎÎÎÎ

Vin = VIL

VIO = VCC or GND

Switch Off (Figure 3)

ÎÎÎÎ

12.0

ÎÎÎ

0.1

ÎÎÎÎ

0.5

ÎÎÎÎ

1.0

ÎÎÎ

µA

ÎÎÎÎ

Ion

ÎÎÎÎÎÎÎÎÎ

Maximum On–Channel Leakage

Current, Any One Channel

ÎÎÎÎÎÎÎÎÎ

Vin = VIH

VIS = VCC or GND

(Figure 4)

ÎÎÎÎ

12.0

ÎÎÎ

0.1

ÎÎÎÎ

0.5

ÎÎÎÎ

1.0

ÎÎÎ

µA

†At supply voltage (VCC – GND) approaching 2 V the analog switch–on resistance becomes extremely non–linear. Therefore, for low–voltage

operation, it is recommended that these devices only be used to control digital signals.

NOTE:Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, ON/OFF Control Inputs: tr = tf = 6 ns)

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎ

Guaranteed Limit

ÎÎÎ

Unit

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎ

VCC

ÎÎÎ

– 55 to

ÎÎÎÎ

125

ÎÎÎ

Unit

ÎÎÎÎ

tPLH,

tPHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, Analog Input to Analog Output

(Figures 8 and 9)

ÎÎÎÎ

2.0

4.5

9.0

12.0

ÎÎÎ

ÎÎÎÎ

ÎÎÎ

ÎÎÎÎ

tPLZ,

tPHZ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, ON/OFF Control to Analog Output

(Figures 10 and 11)

ÎÎÎÎ

2.0

4.5

9.0

12.0

ÎÎÎ

150

ÎÎÎÎ

190

ÎÎÎÎ

225

ÎÎÎ

ÎÎÎÎ

tPZL,

tPZH

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, ON/OFF Control to Analog Output

(Figures 10 and 11)

ÎÎÎÎ

2.0

4.5

9.0

12.0

ÎÎÎ

125

ÎÎÎÎ

160

ÎÎÎÎ

185

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Capacitance ON/OFF Control Input

ÎÎÎÎ

—

ÎÎÎ

ÎÎÎÎ

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Control Input = GND

Analog I/O

Feedthrough

ÎÎÎÎ

—

ÎÎÎ

1.0

ÎÎÎÎ

1.0

ÎÎÎÎ

1.0

ÎÎÎ

NOTES:

1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

CPD

Power Dissipation Capacitance (Per Switch)* (Figure 13)

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Switch)* (Figure 13)

*Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the

Motorola High–Speed CMOS Data Book (DL129/D).

MC54/74HC4016

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

ADDITIONAL APPLICATION CHARACTERISTICS (Voltages Referenced to GND unless noted)

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎ

VCC

ÎÎÎÎ

Limit*

54/74HC

ÎÎÎ

Unit

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎ

Maximum On–Channel Bandwidth or

Minimum Frequency Response

(Figure 5)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

fin = 1 MHz Sine Wave

Adjust fin Voltage to Obtain 0 dBm at VOS

Increase fin Frequency Until dB Meter Reads – 3 dB

RL = 50 Ω, CL = 10 pF

ÎÎÎ

4.5

9.0

12.0

ÎÎÎÎ

150

160

ÎÎÎ

MHz

ÎÎÎÎ

—

ÎÎÎÎÎÎÎÎÎÎ

Off–Channel Feedthrough Isolation

(Figure 6)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

fin



Sine Wave

Adjust fin Voltage to Obtain 0 dBm at VIS

fin = 10 kHz, RL = 600 Ω, CL = 50 pF

ÎÎÎ

4.5

9.0

12.0

ÎÎÎÎ

– 50

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

fin = 1.0 MHz, RL = 50 Ω, CL = 10 pF

ÎÎÎ

4.5

9.0

12.0

ÎÎÎÎ

– 40

ÎÎÎ

ÎÎÎÎ

—

ÎÎÎÎÎÎÎÎÎÎ

Feedthrough Noise, Control to Switch

(Figure 7)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Vin

1 MHz Square Wave (tr = tf = 6 ns)

Adjust RL at Setup so that IS = 0 A

RL = 600 Ω, CL = 50 pF

ÎÎÎ

4.5

9.0

12.0

ÎÎÎÎ

130

200

ÎÎÎ

mVPP

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

RL = 10 kΩ, CL = 10 pF

ÎÎÎ

4.5

9.0

12.0

ÎÎÎÎ

100

ÎÎÎ

ÎÎÎÎ

—

ÎÎÎÎÎÎÎÎÎÎ

Crosstalk Between Any Two Switches

(Figure 12)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

fin



Sine Wave

Adjust fin Voltage to Obtain 0 dBm at VIS

fin = 10 kHz, RL = 600 Ω, CL = 50 pF

ÎÎÎ

4.5

9.0

12.0

ÎÎÎÎ

– 70

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

fin = 1.0 MHz, RL = 50 Ω, CL = 10 pF

ÎÎÎ

4.5

9.0

12.0

ÎÎÎÎ

– 80

ÎÎÎ

ÎÎÎÎ

THD

ÎÎÎÎÎÎÎÎÎÎ

Total Harmonic Distortion

(Figure 14)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

fin = 1 kHz, RL = 10 kΩ, CL = 50 pF

THD = THDMeasured – THDSource

VIS = 4.0 VPP sine wave

VIS = 8.0 VPP sine wave

VIS = 11.0 VPP sine wave

ÎÎÎ

4.5

9.0

12.0

ÎÎÎÎ

0.10

0.06

0.04

ÎÎÎ

*Guaranteed limits not tested. Determined by design and verified by qualification.

MC54/74HC4016

High–Speed CMOS Logic Data

DL129 — Rev 6 5 MOTOROLA

160

140

120

100

00 .5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

120

100

00 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0

00 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0

Vin, INPUT VOLTAGE (VOLTS), REFERENCED TO GND Vin, INPUT VOLTAGE (VOLTS), REFERENCED TO GND

Vin, INPUT VOLTAGE (VOLTS), REFERENCED TO GND

Figure 1b. Typical On Resistance, VCC = 4.5 V

Figure 1d. Typical On Resistance, VCC = 9.0 VFigure 1c. Typical On Resistance, VCC = 6.0 V

Figure 1e. Typical On Resistance, VCC = 12.0 V

3000

2500

2000

1500

1000

500

00 .25 .50 .75 1.00 1.25 1.5 1.75 2.00

300

250

200

150

100

00 .5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

Vin, INPUT VOLTAGE (VOLTS), REFERENCED TO GND Vin, INPUT VOLTAGE (VOLTS), REFERENCED TO GND

Ron

Figure 1a. Typical On Resistance, VCC = 2.0 V

125

–55

125

–55

125

–55

125

–55

125

–55

Figure 2. On Resistance Test Set–Up

PLOTTER

MINI COMPUTER

PROGRAMMABLE

POWER

SUPPLY DC ANALYZER

VCC

+–

ANALOG IN COMMON OUT

GND

DEVICE

UNDER TEST

, ON RESISTANCE (OHMS)

Ron, ON RESISTANCE (OHMS)

Ron, ON RESISTANCE (OHMS)Ron, ON RESISTANCE (OHMS)

MC54/74HC4016

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

Figure 3. Maximum Off Channel Leakage Current,

Any One Channel, Test Set–Up

OFF

14 VCC

VCC

GND

VCC

SELECTED

CONTROL

INPUT

VIL

Figure 4. Maximum On Channel Leakage Current,

Channel to Channel, Test Set–Up

14 VCC

N/C

GND

VCC

SELECTED

CONTROL

INPUT

VIH

Figure 5. Maximum On–Channel Bandwidth

Test Set–Up

VCC

0.1

FCL*

fin dB

METER

*Includes all probe and jig capacitance.

VOS

SELECTED

CONTROL

INPUT

VCC

Figure 6. Off–Channel Feedthrough Isolation,

Test Set–Up

OFF

VCC

0.1

FCL*

fin dB

METER

*Includes all probe and jig capacitance.

VOS

VIS

SELECTED

CONTROL

INPUT

Figure 7. Feedthrough Noise, ON/OFF Control to

Analog Out, Test Set–Up

VCC

CL*

*Includes all probe and jig capacitance.

OFF/ON

VCC

GND

Vin

≤

1 MHz

tr = tf = 6 ns

CONTROL

VCC/2

RLIS

RLVOS

SELECTED

CONTROL

INPUT

VCC/2

VCC

GND

ANALOG IN

ANALOG OUT 50%

tPLH tPHL

50%

Figure 8. Propagation Delays, Analog In to

Analog Out

MC54/74HC4016

High–Speed CMOS Logic Data

DL129 — Rev 6 7 MOTOROLA

Figure 9. Propagation Delay Test Set–Up

14 VCC

*Includes all probe and jig capacitance.

TEST

POINT

ANALOG OUTANALOG IN

CL*

SELECTED

CONTROL

INPUT

VCC

trtfVCC

GND

HIGH

IMPEDANCE

VOL

VOH

HIGH

IMPEDANCE

CONTROL

ANALOG

OUT

90%

50%

10%

50%

10%

90%

tPZH tPHZ

tPZL tPLZ

Figure 10. Propagation Delay, ON/OFF Control

to Analog Out

ON/OFF

VCC

TEST

POINT

VCC 1 k

Ω

POSITION WHEN TESTING tPHZ AND tPZH

CL*

Figure 11. Propagation Delay Test Set–Up

POSITION WHEN TESTING tPLZ AND tPZL

SELECTED

CONTROL

INPUT

Figure 12. Crosstalk Between Any Two Switches,

Test Set–Up

VCC OR GND CL*

*Includes all probe and jig capacitance

OFF

VIS

RLCL*

VOS

fin 0.1

VCC/2 VCC/2

SELECTED

CONTROL

INPUT

VCC/2

Figure 13. Power Dissipation Capacitance

Test Set–Up

VCC

OFF/ON

7SELECTED

CONTROL

INPUT

ON/OFF CONTROL

VCC

0.1

CL*

fin RL

DISTORTION

METER

*Includes all probe and jig capacitance.

VOS

VIS

7SELECTED

CONTROL

INPUT

VCC

Figure 14. Total Harmonic Distortion, Test Set–Up

*Includes all probe and jig capacitance.

VCC

VCC/2

MC54/74HC4016

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

–10

–20

–30

–40

–50

–100 1.0 2.0

FREQUENCY (kHz)

dBm

–60

–70

–80

–90

FUNDAMENTAL FREQUENCY

DEVICE

SOURCE

Figure 15. Plot, Harmonic Distortion

3.0

APPLICATION INFORMATION

The ON/OFF Control pins should be at VCC or GND logic

levels, VCC being recognized as logic high and GND being

recognized as a logic low. Unused analog inputs/outputs

may be left floating (not connected). However, it is advisable

to tie unused analog inputs and outputs to VCC or GND

through a low value resistor. This minimizes crosstalk and

feedthrough noise that may be picked up by the unused I/O

pins.

The maximum analog voltage swings are determined by

the supply voltages VCC and GND. The positive peak analog

voltage should not exceed VCC. Similarly, the negative peak

analog voltage should not go below GND. In the example

below, the difference between VCC and GND is twelve volts.

Therefore, using the configuration in Figure 16, a maximum

analog signal of twelve volts peak–to–peak can be con-

trolled.

When voltage transients above VCC and/or below GND

are anticipated on the analog channels, external diodes (Dx)

are recommended as shown in Figure 17. These diodes

should be small signal, fast turn–on types able to absorb the

maximum anticipated current surges during clipping. An al-

ternate method would be to replace the Dx diodes with



sorbs (Motorola high current surge protectors).



sorbs are fast turn–on devices ideally suited for precise

DC protection with no inherent wear–out mechanism.

ANALOG O/I

VCC = 12 V

ANALOG I/O

+ 12 V

0 V

+ 12 V

0 V

OTHER CONTROL

INPUTS

(VCC OR GND)

VCC

Figure 16. 12 V Application

Figure 17. Transient Suppressor Application

SELECTED

CONTROL

INPUT

OTHER CONTROL

INPUTS

(VCC OR GND)

SELECTED

CONTROL

INPUT

+ 12 V

VCC

MC54/74HC4016

High–Speed CMOS Logic Data

DL129 — Rev 6 9 MOTOROLA

+5 V

HC4016

CONTROL

INPUTS

LSTTL/

NMOS

ANALOG

SIGNALS

R* R* R* R*

ANALOG

SIGNALS

HCT

BUFFER

R* = 2 TO 10 k

Ω

VDD = 5 V VCC = 5 TO 12 V

ANALOG

SIGNALS

ANALOG

SIGNALS

1 16 14

HC4016

CONTROL

INPUTS

MC14504

CHANNEL 4

CHANNEL 3

CHANNEL 2

CHANNEL 1

1 OF 4

SWITCHES

COMMON I/O

1 2 3 4

CONTROL INPUTS

INPUT OUTPUT

0.01

LF356 OR

EQUIVALENT

a. Using Pull-Up Resistors b. Using HCT Buffer

Figure 18. LSTTL/NMOS to HCMOS Interface

Figure 19. TTL/NMOS–to–CMOS Level Converter

Analog Signal Peak–to–Peak Greater than 5 V

(Also see HC4316)

Figure 20. 4–Input Multiplexer Figure 21. Sample/Hold Amplifier

–

1 OF 4

SWITCHES

+5 V

HC4016

CONTROL

INPUTS

LSTTL/

NMOS

ANALOG

SIGNALS ANALOG

SIGNALS

1 OF 4

SWITCHES

1 OF 4

SWITCHES

1 OF 4

SWITCHES

MC54/74HC4016

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

OUTLINE DIMENSIONS

J SUFFIX

CERAMIC DIP PACKAGE

CASE 632–08

ISSUE Y

MIN MINMAX MAX

INCHES MILLIMETERS

DIM

0.785

0.280

0.200

0.020

0.065

0.015

0.170

0.040

0.750

0.245

0.155

0.015

0.055

0.008

0.125

0.020

19.94

7.11

5.08

0.50

1.65

0.38

4.31

1.01

19.05

6.23

3.94

0.39

1.40

0.21

3.18

0.51

0.100 BSC

0.300 BSC

2.54 BSC

7.62 BSC

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEAD WHEN

FORMED PARALLEL.

4. DIMESNION F MAY NARROW TO 0.76 (0.030)

WHERE THE LEAD ENTERS THE CERAMIC

BODY.

14 8

1 7

-A-

-B-

-T-

SEATING

PLANE

F G N

0.25 (0.010) T A

MS0.25 (0.010) T B

J 14 PL

D 14 PL

N SUFFIX

PLASTIC DIP PACKAGE

CASE 646–06

ISSUE L

NOTES:

1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE

POSITION AT SEATING PLANE AT MAXIMUM

MATERIAL CONDITION.

2. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.

3. DIMENSION B DOES NOT INCLUDE MOLD

FLASH.

4. ROUNDED CORNERS OPTIONAL.

1 7

14 8

H G D K

SEATING

PLANE

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.715 0.770 18.16 19.56

B0.240 0.260 6.10 6.60

C0.145 0.185 3.69 4.69

D0.015 0.021 0.38 0.53

F0.040 0.070 1.02 1.78

G0.100 BSC 2.54 BSC

H0.052 0.095 1.32 2.41

J0.008 0.015 0.20 0.38

K0.115 0.135 2.92 3.43

L0.300 BSC 7.62 BSC

M0 10 0 10

N0.015 0.039 0.39 1.01

_ _ _ _

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751A–03

ISSUE F

MIN MINMAX MAX

MILLIMETERS INCHES

DIM

8.55

3.80

1.35

0.35

0.40

0.19

0.10

5.80

0.25

8.75

4.00

1.75

0.49

1.25

0.25

6.20

0.50

0.337

0.150

0.054

0.014

0.016

0.008

0.004

0.228

0.010

0.344

0.157

0.068

0.019

0.049

0.009

0.244

0.019

1.27 BSC 0.050 BSC

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

–A–

–B– P 7 PL

SEATING

PLANE

D 14 PL MJ

R X 45°

814

0.25 (0.010) T B A

MS S

B0.25 (0.010) M M

MC54/74HC4016

High–Speed CMOS Logic Data

DL129 — Rev 6 11 MOTOROLA

How to reach us:

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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,

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MC54/74HC4016/D

*MC54/74HC4016/D*

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