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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

OPA170

OPA2170

OPA4170

SBOS557E –AUGUST 2011–REVISED APRIL 2018

OPAx170 36-V, Single-Supply, SOT553, Low-Power Operational Amplifiers Value Line

Series

1 Features

1• Supply Range: 2.7 V to 36 V, ±1.35 V to ±18 V

• Low Noise: 19 nV/√Hz

• RFI Filtered Inputs

• Input Range Includes the Negative Supply

• Input Range Operates to Positive Supply

• Rail-to-Rail Output

• Gain Bandwidth: 1.2 MHz

• Low Quiescent Current: 110 µA per Amplifier

• High Common-Mode Rejection: 120 dB

• Low Bias Current: 15 pA (Maximum)

• Industry-Standard Packages and micro Packages

Available

• Create a Custom Design Using the OPAx170 With

the WEBENCH®Power Designer

2 Applications

• Tracking Amplifier in Power Modules

• Merchant Power Supplies

• Transducer Amplifiers

• Bridge Amplifiers

• Temperature Measurements

• Strain Gauge Amplifiers

• Precision Integrators

• Battery-Powered Instruments

• Test Equipment

3 Description

The OPA170, OPA2170, and OPA4170 devices

(OPAx170) are a family of 36-V, single-supply, low-

noise operational amplifiers (op amps) that feature

micro packages with the ability to operate on supplies

ranging from 2.7 V (±1.35 V) to 36 V (±18 V). They

offer good offset, drift, and bandwidth with low

quiescent current. The single, dual, and quad

versions all have identical specifications for maximum

design flexibility.

Unlike most op amps, which are specified at only one

supply voltage, the OPAx170 family of op amps is

specified from 2.7 V to 36 V. Input signals beyond the

supply rails do not cause phase reversal. The

OPAx170 family is stable with capacitive loads up to

300 pF. The input can operate 100 mV below the

negative rail and within 2 V of the positive rail for

normal operation. Note that these devices can

operate with full rail-to-rail input 100 mV beyond the

positive rail, but with reduced performance within 2 V

of the positive rail. The OPAx170 op amps are

specified from –40°C to +125°C.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

OPA170

SOIC (8) 4.90 mm × 3.91 mm

SOT (5) 1.60 mm × 1.20 mm

SOT-23 (5) 2.90 mm × 1.60 mm

OPA2170

SOIC (8) 4.90 mm × 3.91 mm

VSSOP (8) 3.00 mm × 3.00 mm

VSSOP (8), micro size 2.30 mm × 2.00 mm

WSON (8) 2.00 mm × 2.00 mm

OPA4170 SOIC (14) 8.65 mm × 3.91 mm

TSSOP (14) 5.00 mm × 4.40 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Smallest Packaging for 36-V Operational Amplifiers

OPA170

OPA2170

OPA4170

SBOS557E –AUGUST 2011–REVISED APRIL 2018

www.ti.com

Product Folder Links: OPA170 OPA2170 OPA4170

Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description............................................................. 1

4 Revision History..................................................... 2

5 Device Comparison Table..................................... 3

6 Pin Configuration and Functions......................... 4

7 Specifications......................................................... 7

7.1 Absolute Maximum Ratings ...................................... 7

7.2 ESD Ratings.............................................................. 7

7.3 Recommended Operating Conditions....................... 7

7.4 Thermal Information: OPA170 .................................. 8

7.5 Thermal Information: OPA2170 ................................ 8

7.6 Thermal Information: OPA4170 ................................ 8

7.7 Electrical Characteristics........................................... 9

7.8 Typical Characteristics............................................ 11

8 Detailed Description............................................ 18

8.1 Overview................................................................. 18

8.2 Functional Block Diagram ...................................... 18

8.3 Feature Description................................................. 18

8.4 Device Functional Modes........................................ 22

9 Application and Implementation ........................ 23

9.1 Application Information............................................ 23

9.2 Typical Application.................................................. 23

10 Power Supply Recommendations ..................... 26

11 Layout................................................................... 26

11.1 Layout Guidelines ................................................. 26

11.2 Layout Example .................................................... 26

12 Device and Documentation Support................. 28

12.1 Device Support...................................................... 28

12.2 Documentation Support ........................................ 29

12.3 Related Links ........................................................ 29

12.4 Receiving Notification of Documentation Updates 29

12.5 Community Resources.......................................... 29

12.6 Trademarks........................................................... 30

12.7 Electrostatic Discharge Caution............................ 30

12.8 Glossary................................................................ 30

13 Mechanical, Packaging, and Orderable

Information........................................................... 30

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision D (December 2017) to Revision E Page

• Changed minimum supply voltage from –20 V to 0 V in Absolute Maximum Ratings table.................................................. 7

• Changed maximum supply voltage from 20 V to 40 V in Absolute Maximum Ratings table ................................................ 7

Changes from Revision C (March 2016) to Revision D Page

• Added WEBENCH links and sections and Receiving Notification of Documentation Updates.............................................. 1

• Added 8-Pin DSG (WSON) package...................................................................................................................................... 1

• Changed values in Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application from: 250 Ωto: 2.5 Ω........ 20

Changes from Revision B (September 2012) to Revision C Page

• Added current package designators to Features list and final paragraph of Description section.......................................... 1

• Added Pin Functions table, ESD Ratings table, Recommended Operating Conditions table, Detailed Description

section, Application and Implementation section, Power Supply Recommendations section, Layout section, Device

and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ............................... 1

Changes from Revision A (September 2011) to Revision B Page

• Added "Value Line Series" to document title.......................................................................................................................... 1

OPA170

OPA2170

OPA4170

www.ti.com

SBOS557E –AUGUST 2011–REVISED APRIL 2018

Product Folder Links: OPA170 OPA2170 OPA4170

5 Device Comparison Table

DEVICE NO OF

CHANNELS

PACKAGE-LEAD

SOT SOT23-5 D DSG VSSOP VSSOP

(micro size) TSSOP

OPA170 1 5 5 8 — — — —

OPA2170 2 — — 8 8 8 8 —

OPA4170 4 — — 14 — — — 14

NC(1)

V+

OUT

NC(1)

-IN

+IN

V-

V+

-IN

OUT

V-

+IN

V+

OUT

IN+

V-

IN-

OPA170

OPA2170

OPA4170

SBOS557E –AUGUST 2011–REVISED APRIL 2018

www.ti.com

Product Folder Links: OPA170 OPA2170 OPA4170

6 Pin Configuration and Functions

OPA170 DRL Package

5-Pin SOT

Top View OPA170 DBV Package

5-Pin SOT-23

Top View

OPA170 D Package

8-Pin SOIC

Top View

(1) NC indicates no internal connection.

Pin Functions: OPA170

PIN I/O DESCRIPTION

NAME SOT SOT-23 D

IN– (–IN) 3 4 2 I Negative (inverting) input

IN+ (+IN) 1 3 3 I Positive (noninverting) input

NC(1) — — 1, 5, 8 — No internal connection (can be left floating)

OUT 4 1 6 O Output

V+ 5 5 7 — Positive (highest) power supply

V– 2 2 4 — Negative (lowest) power supply

1OUT A 8 V+

2±IN A 7 OUT B

3+IN A 6 ±IN B

4V±5 +IN B

Thermal

Pad

V+

OUTB

-INB

+INB

OUTA

-INA

+INA

V-

OPA170

OPA2170

OPA4170

www.ti.com

SBOS557E –AUGUST 2011–REVISED APRIL 2018

Product Folder Links: OPA170 OPA2170 OPA4170

OPA2170 D, DGK, and DCU Packages

8-Pin VSSOP, SOIC, and VSSOP (micro size)

Top View

OPA2170 DSG Package

8-Pin WSON

Top View

Pin Functions: OPA2170

I/O DESCRIPTION

NAME SOIC VSSOP VSSOP

(micro

size) WSON

–IN A 2 2 2 2 I Inverting input, channel A

–IN B 6 6 6 6 I Inverting input, channel B

+IN A 3 3 3 3 I Noninverting input, channel A

+IN B 5 5 5 5 I Noninverting input, channel B

OUT A 1 1 1 1 O Output, channel A

OUT B 7 7 7 7 O Output, channel B

V– 4 4 4 4 — Negative (lowest) power supply

V+ 8 8 8 8 — Positive (highest) power supply

OUTD

-IND

+IND

V-

OUTA

-INA

+INA

V+

+INC

-INC

OUTC

+INB

-INB

OUTB

OPA170

OPA2170

OPA4170

SBOS557E –AUGUST 2011–REVISED APRIL 2018

www.ti.com

Product Folder Links: OPA170 OPA2170 OPA4170

OPA4170 D and PW Packages

14-Pin SOIC and TSSOP

Top View

Pin Functions: OPA4170

PIN I/O DESCRIPTION

NAME SOIC TSSOP

–IN A 2 2 I Inverting input, channel A

–IN B 6 6 I Inverting input, channel B

–IN C 9 9 I Inverting input, channel C

–IN D 13 13 I Inverting input, channel D

+IN A 3 3 I Noninverting input, channel A

+IN B 5 5 I Noninverting input, channel B

+IN C 10 10 I Noninverting input, channel C

+IN D 12 12 I Noninverting input, channel D

OUT A 1 1 O Output, channel A

OUT B 7 7 O Output, channel B

OUT C 8 8 O Output, channel C

OUT D 14 14 O Output, channel D

V– 11 11 — Negative (lowest) power supply

V+ 4 4 — Positive (highest) power supply

OPA170

OPA2170

OPA4170

www.ti.com

SBOS557E –AUGUST 2011–REVISED APRIL 2018

Product Folder Links: OPA170 OPA2170 OPA4170

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Short-circuit to ground, one amplifier per package.

7 Specifications

7.1 Absolute Maximum Ratings

Over operating free-air temperature range, unless otherwise noted.(1)

MIN MAX UNIT

Supply voltage 0 40 V

Single supply voltage 40 V

Signal input pin voltage (V–) – 0.5 (V+) + 0.5 V

Signal input pin current –10 10 mA

Output short-circuit current(2) Continuous

Operating ambient temperature, TA–55 150 °C

Junction temperature, TJ150 °C

Storage temperature, Tstg –65 150 °C

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.2 ESD Ratings VALUE UNIT

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000 V

Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±750

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT

VSSupply voltage (V+ – V–) 2.7 36 V

TAOperating temperature –40 125 °C

OPA170

OPA2170

OPA4170

SBOS557E –AUGUST 2011–REVISED APRIL 2018

www.ti.com

Product Folder Links: OPA170 OPA2170 OPA4170

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7.4 Thermal Information: OPA170

THERMAL METRIC(1)

OPA170

UNITD (SOIC) DBV (SOT-23) DRL (SOT)

8 PINS 5 PINS 5 PINS

RθJA Junction-to-ambient thermal resistance 149.5 245.8 208.1 °C/W

RθJC(top) Junction-to-case (top) thermal resistance 97.9 133.9 0.1 °C/W

RθJB Junction-to-board thermal resistance 87.7 83.6 42.4 °C/W

ψJT Junction-to-top characterization parameter 35.5 18.2 0.5 °C/W

ψJB Junction-to-board characterization parameter 89.5 83.1 42.2 °C/W

RθJC(bot) Junction-to-case (bottom) thermal resistance — — — °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7.5 Thermal Information: OPA2170

THERMAL METRIC(1)

OPA2170

UNITD (SOIC) DCU (VSSOP,

micro size) DGK (VSSOP) DSG (WSON)

8 PINS 8 PINS 8 PINS 8 PINS

RθJA Junction-to-ambient thermal resistance 134.3 175.2 180 71.5 °C/W

RθJC(top) Junction-to-case (top) thermal resistance 72.1 74.9 55 89.1 °C/W

RθJB Junction-to-board thermal resistance 60.6 22.2 130 38.8 °C/W

ψJT Junction-to-top characterization parameter 18.2 1.6 5.3 3.8 °C/W

ψJB Junction-to-board characterization parameter 53.8 22.8 120 38.9 °C/W

RθJC(bot) Junction-to-case (bottom) thermal resistance — — — 13 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7.6 Thermal Information: OPA4170

THERMAL METRIC(1)

OPA4170

UNITD (SOIC) PW (TSSOP)

14 PINS 14 PINS

RθJA Junction-to-ambient thermal resistance 93.2 106.9 °C/W

RθJC(top) Junction-to-case (top) thermal resistance 51.8 24.4 °C/W

RθJB Junction-to-board thermal resistance 49.4 59.3 °C/W

ψJT Junction-to-top characterization parameter 13.5 0.6 °C/W

ψJB Junction-to-board characterization parameter 42.2 54.3 °C/W

RθJC(bot) Junction-to-case (bottom) thermal resistance — — °C/W

OPA170

OPA2170

OPA4170

www.ti.com

SBOS557E –AUGUST 2011–REVISED APRIL 2018

Product Folder Links: OPA170 OPA2170 OPA4170

(1) The input range can be extended beyond (V+) – 2 V up to V+. See the Typical Characteristics and Application and Implementation

sections for additional information.

7.7 Electrical Characteristics

at TA= 25°C, VCM = VOUT = VS/ 2, and RL= 10 kΩconnected to VS/ 2 (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

OFFSET VOLTAGE

VOS Input offset voltage TA= 25°C 0.25 ±1.8 mV

TA= –40°C to +125°C ±2 mV

dVOS/dT Input offset voltage drift TA= –40°C to +125°C ±0.3 ±2 µV/°C

PSRR Input offset voltage vs power supply VS= 4 V to 36 V, TA= –40°C to +125°C 1 ±5 µV/V

Channel separation, dc 5 µV/V

INPUT BIAS CURRENT

IBInput bias current TA= 25°C ±8 ±15 pA

TA= –40°C to +125°C ±3.5 nA

IOS Input offset current TA= 25°C ±4 ±15 pA

TA= –40°C to +125°C ±3.5 nA

NOISE

Input voltage noise ƒ = 0.1 Hz to 10 Hz 2 µVPP

enInput voltage noise density ƒ = 100 Hz 22 nV/√Hz

ƒ = 1 kHz 19 nV/√Hz

INPUT VOLTAGE

VCM Common-mode voltage range(1) (V–) – 0.1 (V+) – 2 V

CMRR Common-mode rejection ratio

VS= ±2 V, (V–) - 0.1 V < VCM < (V+) - 2 V,

TA= –40°C to +125°C 90 104 dB

VS= ±18 V, (V–) - 0.1 V < VCM < (V+) - 2 V,

TA= –40°C to +125°C 104 120 dB

INPUT IMPEDANCE

Differential 100 || 3 MΩ|| pF

Common-mode 6 || 3 1012 Ω|| pF

OPEN-LOOP GAIN

AOL Open-loop voltage gain VS= 4 V to 36 V,

(V–) + 0.35 V < VO< (V+) - 0.35 V,

TA= –40°C to +125°C 110 130 dB

FREQUENCY RESPONSE

GBP Gain bandwidth product 1.2 MHz

SR Slew rate G = +1 0.4 V/µs

tSSettling time To 0.1%, VS= ±18 V, G = +1, 10-V step 20 µs

To 0.01% (12-bit), VS= ±18 V, G = +1,

10-V step 28 µs

Overload recovery time VIN × Gain > VS2 µs

THD+N Total harmonic distortion + noise G = +1, ƒ = 1 kHz, VO= 3 VRMS 0.0002%

OPA170

OPA2170

OPA4170

SBOS557E –AUGUST 2011–REVISED APRIL 2018

www.ti.com

Product Folder Links: OPA170 OPA2170 OPA4170

Electrical Characteristics (continued)

at TA= 25°C, VCM = VOUT = VS/ 2, and RL= 10 kΩconnected to VS/ 2 (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

OUTPUT

VOVoltage output swing from positive rail IL= 0 mA, VS= 4 V to 36 V 10 mV

ILsourcing 1 mA, VS= 4 V to 36 V 115 mV

VOVoltage output swing from negative rail IL= 0 mA, VS= 4 V to 36 V 8 mV

ILsinking 1 mA, VS= 4 V to 36 V 70 mV

VOVoltage output swing from rail VS= 5 V, RL= 10 kΩ; TA= –40°C to +125°C (V–) + 0.03 (V+) – 0.05 V

RL= 10 kΩ, AOL ≥110 dB,

TA= –40°C to +125°C (V–) + 0.35 (V+) – 0.35 V

ISC Short-circuit current –20 17 mA

CLOAD Capacitive load drive See Typical Characteristics pF

ROOpen-loop output resistance ƒ = 1 MHz, IO= 0 A 900 Ω

POWER SUPPLY

VSSpecified voltage range 2.7 36 V

IQQuiescent current per amplifier IO= 0 A; TA= 25°C 110 145 µA

IO= 0 A; TA= –40°C to +125°C 155 µA

TEMPERATURE

Specified range –40 125 °C

Operating range –55 150 °C

OPA170

OPA2170

OPA4170

www.ti.com

SBOS557E –AUGUST 2011–REVISED APRIL 2018

Product Folder Links: OPA170 OPA2170 OPA4170

7.8 Typical Characteristics

VS= ±18 V, VCM = VS/ 2, RLOAD = 10 kΩconnected to VS/ 2, and CL= 100 pF, (unless otherwise noted)

Table 1. Characteristic Performance Measurements

DESCRIPTION FIGURE

Offset Voltage Production Distribution Figure 1

Offset Voltage Drift Distribution Figure 2

Offset Voltage vs Temperature Figure 3

Offset Voltage vs Common-Mode Voltage Figure 4

Offset Voltage vs Common-Mode Voltage (Upper Stage) Figure 5

Offset Voltage vs Power Supply Figure 6

IBand IOS vs Common-Mode Voltage Figure 7

Input Bias Current vs Temperature Figure 8

Output Voltage Swing vs Output Current (Maximum Supply) Figure 9

CMRR and PSRR vs Frequency (Referred-to-Input) Figure 10

CMRR vs Temperature Figure 11

PSRR vs Temperature Figure 12

0.1-Hz to 10-Hz Noise Figure 13

Input Voltage Noise Spectral Density vs Frequency Figure 14

THD+N Ratio vs Frequency Figure 15

THD+N vs Output Amplitude Figure 16

Quiescent Current vs Temperature Figure 17

Quiescent Current vs Supply Voltage Figure 18

Open-Loop Gain and Phase vs Frequency Figure 19

Closed-Loop Gain vs Frequency Figure 20

Open-Loop Gain vs Temperature Figure 21

Open-Loop Output Impedance vs Frequency Figure 22

Small-Signal Overshoot vs Capacitive Load (100-mV Output Step) Figure 23,Figure 24

No Phase Reversal Figure 25

Positive Overload Recovery Figure 26

Negative Overload Recovery Figure 27

Small-Signal Step Response (100 mV) Figure 28,Figure 29

Large-Signal Step Response Figure 30,Figure 31

Large-Signal Settling Time (10-V Positive Step) Figure 32

Large-Signal Settling Time (10-V Negative Step) Figure 33

Short-Circuit Current vs Temperature Figure 34

Maximum Output Voltage vs Frequency Figure 35

EMIRR IN+ vs Frequency Figure 36

Offset Voltage ( V)m

Normal

Operation

Common-Mode Voltage (V)

5 Typical Units Shown

−500

−300

−100

100

300

500

0 2 4 6 8 10 12 14 16 18 20

VSUPPLY (V)

Offset Voltage (µV)

VSUPPLY = ±1.35V to ± 18V

5 Typical Units Shown

G006

V = 18.1V

CM -

Offset Voltage ( V)m

Common-Mode Voltage (V)

−1000

−800

−600

−400

−200

200

400

600

800

1000

−50 −25 0 25 50 75 100 125 150

Temperature (°C)

Offset Voltage (µV)

5 Typical Units Shown

G003

−1200

−1100

−1000

−900

−800

−700

−600

−500

−400

−300

−200

−100

100

200

300

400

500

600

700

800

900

1000

1100

1200

−1200

−1100

−1000

−900

−800

−700

−600

−500

−400

−300

−200

−100

100

200

300

400

500

600

700

800

900

1000

1100

1200

Offset Voltage (µV)

Percentage of Amplifiers (%)

Distribution Taken From 400 Amplifiers

G001

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

Offset Voltage Drift (µV/°C)

Percentage of Amplifiers (%)

Distribution Taken From 104 Amplifiers

G002

OPA170

OPA2170

OPA4170

SBOS557E –AUGUST 2011–REVISED APRIL 2018

www.ti.com

Product Folder Links: OPA170 OPA2170 OPA4170

Figure 1. Offset Voltage Production Distribution Figure 2. Offset Voltage Drift Distribution

Figure 3. Offset Voltage vs Temperature Figure 4. Offset Voltage vs Common-Mode Voltage

Figure 5. Offset Voltage vs Common-Mode Voltage

(Upper Stage) Figure 6. Offset Voltage vs Power Supply

−3

−2

−1

−75 −50 −25 0 25 50 75 100 125 150

Temperature (°C)

Power−Supply Rejection Ratio (µV/V)

VS = 2.7V to 36V

VS = 4V to 36V

G012

Common-ModeRejectionRatio( V/V)m

-75 -50 -25 0 25 150

Temperature( C)°

50 12510075

V = 1.35V±

V = 2V

S±

V = 18V

S±

OutputVoltage(V)

0 1 2 3 4 10

OutputCurrent(mA)

5 6 7

14.5

-14.5

-15

-16

-17

-18

8 9

- °40 C

+25 C°

+125 C°

140

120

100

Common-Mode Rejection Ratio (dB),

Power-Supply Rejection Ratio (dB)

1 10 100 1k 10k 1M

Frequency (Hz)

100k

+PSRR

-PSRR

CMRR

-20 20

V (V)

I and I (pA)

B OS

-15 -10 -5 0 5 10 15

IOS

+IB

-IB

V = 18.1V-

CM V = 16.1V

IB+

IB-

IOS

2000

1500

1000

500

1000

InputBiasCurrent(pA)

-75 -50 -25 0 25 150

Temperature( C)°

50 12510075

OPA170

OPA2170

OPA4170

www.ti.com

SBOS557E –AUGUST 2011–REVISED APRIL 2018

Product Folder Links: OPA170 OPA2170 OPA4170

Figure 7. IBand IOS vs Common-Mode Voltage Figure 8. Input Bias Current vs Temperature

Figure 9. Output Voltage Swing vs Output Current

(Maximum Supply) Figure 10. CMRR and PSRR vs Frequency

(Referred-to Input)

Figure 11. CMRR vs Temperature Figure 12. PSRR vs Temperature

Temperature (qC)

IQ (PA)

-50 -25 0 25 50 75 100 125 150

100

110

120

130

140

VS = ±18V

VS = ±1.35V

G017

I (µA)

0.01

0.001

0.0001

0.00001

TotalHarmonicDistortion+Noise(%)

10 100 1k 10k 100k

Frequency(Hz)

TotalHarmonicDistortion+Noise(dB)

V =3V

BW=80kHz

OUT RMS

G=+1

R =10k

-80

-100

-120

-140

0.1

0.01

0.001

0.0001

0.00001

TotalHarmonicDistortion+Noise(%)

0.01 0.1 1 10 20

OutputAmplitude(V )

RMS

-60

TotalHarmonicDistortion+Noise(dB)

BW=80kHz

G=+1

R =10k

-80

-100

-140

-120

100

1000

1 10 100 1k 10k 100k 1M

Frequency (Hz)

Voltage Noise Density (nV/ Hz)

G014

1 V/divm

OPA170

OPA2170

OPA4170

SBOS557E –AUGUST 2011–REVISED APRIL 2018

www.ti.com

Product Folder Links: OPA170 OPA2170 OPA4170

Figure 13. 0.1-Hz to 10-Hz Noise Figure 14. Input Voltage Noise Spectral Density vs

Frequency

Figure 15. THD+N Ratio vs Frequency Figure 16. THD+N vs Output Amplitude

Figure 17. Quiescent Current vs Temperature Figure 18. Quiescent Current vs Supply Voltage

+18V

-18V

ROUT

OPA170

G=+1

OPA170

R =

I10kW

ROUT

RF=10kW

+18V

-18V

G= 1-

2.5

1.5

0.5

A ( V/V)m

-75 -50 -25 0 25 150

Temperature( C)°

50 12510075

V =2.7V

V =4V

V =36V

10k

100

Z ( )W

1 10 100 1k 10k 10M

Frequency(Hz)

100k 1M

−20

−10

1k 10k 100k 1M 10M 100M

Frequency (Hz)

Gain (dB)

G = −1

G = 1

G = 100

G020

140

120

100

Gain(dB)

0.1 10 100 1k 10k 10M

Frequency(Hz)

1M100k

Phase

Gain

Phase( )°

135

180

225

270

OPA170

OPA2170

OPA4170

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Product Folder Links: OPA170 OPA2170 OPA4170

Figure 19. Open-Loop Gain and Phase vs Frequency Figure 20. Closed-Loop Gain vs Frequency

Figure 21. Open-Loop Gain vs Temperature Figure 22. Open-Loop Output Impedance vs Frequency

100-mV output step

Figure 23. Small-Signal Overshoot vs Capacitive Load

100-mV output step

Figure 24. Small-Signal Overshoot vs Capacitive Load

20mV/div

Time(5 s/div)m

R =10k

C =10pF

+18V

-18V

RF=2kWRI=2kW

OPA170

G= 1-

2V/div

Time(50 s/div)m

G=+1

R =10k

C =10pF

5V/div

Time(10 s/div)m

2kW

20kW

VIN

VOUT

OPA170

G= 10-

+18V

-18V

20mV/div

Time(5 s/div)m

+18V

-18V CL

OPA170

G=+1

R =10k

C =10pF

5V/div

Time(10 s/div)m

2kW

20kW

VIN

VOUT

OPA170

G= 10-

+18V

-18V

5V/div

Time(100 s/div)m

+18V

-18V

37VPP

SineWave

( 18.5V)±

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Figure 25. No Phase Reversal Figure 26. Positive Overload Recovery

Figure 27. Negative Overload Recovery Figure 28. Small-Signal Step Response (100 mV)

Figure 29. Small-Signal Step Response (100 mV) Figure 30. Large-Signal Step Response

2.5

7.5

12.5

1k 10k 100k 1M 10M

Frequency (Hz)

Output Voltage (VPP )

VS = ±5 V

VS = ±1.35 V

VS = ±15 V

Maximum output range without

slew−rate induced distortion

G035

140

120

100

EMIRRIN+(dB)

10M 10G

Frequency(Hz)

100M

P = 10dBm

V = 18V

V =0V

−30

−25

−20

−15

−10

−5

−50 −25 0 25 50 75 100 125 150

Temperature (°C)

ISC (mA)

ISC, Source

ISC, Sink

G034

DFrom Final Value (mV)

060

Time ( s)m

5040302010

12-Bit Settling

( 1/2LSB = 0.012%)± ±

G = 1-

2V/div

Time(50 s/div)m

G= 1

R =10k

C =10pF

DFrom Final Value (mV)

0100

Time ( s)m

12-Bit Settling

( 1/2LSB = 0.012%)± ±

908070605040302010

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Figure 31. Large-Signal Step Response

10-V positive step

Figure 32. Large-Signal Settling Time

10-V negative step

Figure 33. Large-Signal Settling Time Figure 34. Short-Circuit Current vs Temperature

Figure 35. Maximum Output Voltage vs Frequency Figure 36. EMIRR IN+ vs Frequency

NCH

Input Stage

PCH

Input Stage 2nd Stage Output

Stage

+IN

-IN

PCH

FF Stage

OUT

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8 Detailed Description

8.1 Overview

The OPAx170 family of operational amplifiers provides high overall performance, making them ideal for many

general-purpose applications. The excellent offset drift of only 2 μV/°C provides excellent stability over the entire

temperature range. In addition, the device offers very good overall performance with high CMRR, PSRR, and

AOL.

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Operating Characteristics

The OPAx170 family of amplifiers is specified for operation from 2.7 V to 36 V (±1.35 V to ±18 V). Many of the

specifications apply from –40°C to +125°C. Parameters that can exhibit significant variance with regard to

operating voltage or temperature are presented in the Typical Characteristics.

5V/div

Time(100 s/div)m

+18V

-18V

37VPP

SineWave

( 18.5V)±

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Feature Description (continued)

8.3.2 Phase-Reversal Protection

The OPAx170 family has an internal phase-reversal protection. Many operational amplifiers exhibit a phase

reversal when the input is driven beyond its linear common-mode range. This condition is most often

encountered in noninverting circuits when the input is driven beyond the specified common-mode voltage range,

causing the output to reverse into the opposite rail. The input of the OPAx170 prevents phase reversal with

excessive common-mode voltage. Instead, the output limits into the appropriate rail. This performance is shown

in Figure 37.

Figure 37. No Phase Reversal

8.3.3 Electrical Overstress

Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress.

These questions tend to focus on the device inputs, but can involve the supply voltage pins or even the output

pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown

characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.

Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from

accidental ESD events both before and during product assembly.

A good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is helpful.

Figure 38 illustrates the ESD circuits contained in the OPAx170 (indicated by the dashed line area). The ESD

protection circuitry involves several current-steering diodes connected from the input and output pins and routed

back to the internal power-supply lines, where the diodes meet at an absorption device internal to the operational

amplifier. This protection circuitry is intended to remain inactive during normal circuit operation.

Power-Supply

ESD Cell

2.5 NŸ

IN±

IN+

TVS

VIN

±VS

ID+

TVS

+VS

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Feature Description (continued)

Figure 38. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application

An ESD event produces a short-duration, high-voltage pulse that is transformed into a short-duration, high-

current pulse when discharging through a semiconductor device. The ESD protection circuits are designed to

provide a current path around the operational amplifier core to prevent damage. The energy absorbed by the

protection circuitry is then dissipated as heat.

When an ESD voltage develops across two or more amplifier device pins, current flows through one or more

steering diodes. Depending on the path that the current takes, the absorption device can activate. The absorption

device has a trigger, or threshold voltage, that is above the normal operating voltage of the OPAx170 but below

the device breakdown voltage level. When this threshold is exceeded, the absorption device quickly activates

and clamps the voltage across the supply rails to a safe level.

When the operational amplifier connects into a circuit (refer to Figure 38), the ESD protection components are

intended to remain inactive and do not become involved in the application circuit operation. However,

circumstances may arise where an applied voltage exceeds the operating voltage range of a given pin. If this

condition occurs, there is a risk that some internal ESD protection circuits can turn on and conduct current. Any

such current flow occurs through steering-diode paths and rarely involves the absorption device.

Figure 38 shows a specific example where the input voltage (VIN) exceeds the positive supply voltage (V+) by

500 mV or more. Much of what happens in the circuit depends on the supply characteristics. If V+ can sink the

current, one of the upper input steering diodes conducts and directs current to V+. Excessively high current

levels can flow with increasingly higher VIN. As a result, the data sheet specifications recommend that

applications limit the input current to 10 mA.

If the supply is not capable of sinking the current, VIN can begin sourcing current to the operational amplifier and

then take over as the source of positive supply voltage. The danger in this case is that the voltage can rise to

levels that exceed the operational amplifier absolute maximum ratings.

OPA170

R =

I10kW

ROUT

RF=10kW

+18V

-18V

G= 1-

+18V

-18V

ROUT

OPA170

G=+1

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Feature Description (continued)

Another common question involves what happens to the amplifier if an input signal is applied to the input when

the power supplies (V+ or V–) are at 0 V. Again, this question depends on the supply characteristic when at 0 V,

or at a level below the input signal amplitude. If the supplies appear as high impedance, then the input source

supplies the operational amplifier current through the current-steering diodes. This state is not a normal bias

condition; most likely, the amplifier does not operate normally. If the supplies are low impedance, then the current

through the steering diodes can become quite high. The current level depends on the ability of the input source

to deliver current, and any resistance in the input path.

If there is any uncertainty about the ability of the supply to absorb this current, add external Zener diodes to the

supply pins; see Figure 38. Select the Zener voltage so that the diode does not turn on during normal operation.

However, the Zener voltage must be low enough so that the Zener diode conducts if the supply pin begins to rise

above the safe-operating, supply-voltage level.

The OPAx170 input pins are protected from excessive differential voltage with back-to-back diodes; see

Figure 38. In most circuit applications, the input protection circuitry has no effect. However, in low-gain or G = 1

circuits, fast-ramping input signals can forward-bias these diodes because the output of the amplifier cannot

respond rapidly enough to the input ramp. If the input signal is fast enough to create this forward-bias condition,

limit the input signal current to 10 mA or less. If the input signal current is not inherently limited, an input series

resistor can be used to limit the input signal current. This input series resistor degrades the low-noise

performance of the OPAx170. Figure 38 illustrates an example configuration that implements a current-limiting

feedback resistor.

8.3.4 Capacitive Load and Stability

The dynamic characteristics of the OPAx170 have been optimized for common operating conditions. The

combination of low closed-loop gain and high capacitive loads decreases the phase margin of the amplifier and

can lead to gain peaking or oscillations. As a result, heavier capacitive loads must be isolated from the output.

The simplest way to achieve this isolation is to add a small resistor (for example, ROUT equal to 50 Ω) in series

with the output. Refer to Figure 39 and Figure 40 illustrate graphs of small-signal overshoot versus capacitive

load for several values of ROUT. Also, refer to applications bulletin AB-028, Feedback Plots Define Op Amp AC

Performance, for details of analysis techniques and application circuits.

100-mV Output Step G = 1

Figure 39. Small-Signal Overshoot vs Capacitive Load

100-mV Output Step G = –1

Figure 40. Small-Signal Overshoot vs Capacitive Load

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8.4 Device Functional Modes

8.4.1 Common-Mode Voltage Range

The input common-mode voltage range of the OPAx170 series extends 100 mV below the negative rail and

within 2 V of the top rail for normal operation.

This device can operate with full rail-to-rail input 100 mV beyond the top rail, but with reduced performance within

2 V of the top rail. The typical performance in this range is summarized in Table 2.

Table 2. Typical Performance for Common-Mode Voltages Within 2 V of the Positive Supply

PARAMETER MIN TYP MAX UNIT

Input common-mode voltage (V+) – 2 (V+) + 0.1 V

Offset voltage 7 mV

vs temperature 12 µV/°C

Common-mode rejection 65 dB

Open-loop gain 60 dB

Gain-bandwidth product 0.3 MHz

Slew rate 0.3 V/µs

8.4.2 Overload Recovery

Overload recovery is defined as the time required for the operational amplifier output to recover from the

saturated state to the linear state. The output devices of the operational amplifier enter the saturation region

when the output voltage exceeds the rated operating voltage, either resulting from the high input voltage or the

high gain. After the device enters the saturation region, the charge carriers in the output devices need time to

return back to the normal state. After the charge carriers return back to the equilibrium state, the device begins to

slew at the normal slew rate. Thus, the propagation delay in case of an overload condition is the sum of the

overload recovery time and the slew time. The overload recovery time for the OPAx170 is approximately 2 µs.

CLOAD

VIN

VOUT

+VS

RISO

-VS

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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The OPAx170 family of operational amplifiers provides high overall performance in a large number of general-

purpose applications. As with all amplifiers, applications with noisy or high-impedance power supplies require

decoupling capacitors placed close to the device pins. In most cases, 0.1-µF capacitors are adequate. Follow the

additional recommendations in Layout Guidelines in order to achieve the maximum performance from this device.

Many applications may introduce capacitive loading to the output of the amplifier (potentially causing instability).

One method of stabilizing the amplifier in such applications is to add an isolation resistor between the amplifier

output and the capacitive load. The design process for selecting this resistor is given in Typical Application.

9.2 Typical Application

This circuit can be used to drive capacitive loads such as cable shields, reference buffers, MOSFET gates, and

diodes. The circuit uses an isolation resistor (Riso) to stabilize the output of an operational amplifier. Riso

modifies the open-loop gain of the system to ensure the circuit has sufficient phase margin.

Figure 41. Unity-Gain Buffer With RISO Stability Compensation

9.2.1 Design Requirements

The design requirements are:

• Supply voltage: 30 V (±15 V)

• Capacitive loads: 100 pF, 1000 pF, 0.01 µF, 0.1 µF, and 1 µF

• Phase margin: 45° and 60°

9.2.2 Detailed Design Procedure

9.2.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the OPAx170 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance

Gain (dB)

AOL

1/

10 100 1k 10k 100k 1M

100

120

10M 100M

Frequency (Hz)

20 dB

ROC dec

40 dB

1 dec

zISO LOAD

f2 R CŒ

u u u

 

pISO o LOAD

f2 R R CŒ

u u  u

 

LOAD ISO

o ISO LOAD

1 + C × R × s

T(s) = 1 + R + R × C × s

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Typical Application (continued)

• Run thermal simulations to understand board thermal performance

• Export customized schematic and layout into popular CAD formats

• Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

9.2.2.2 Unity-Gain Buffer

Figure 41 shows a unity-gain buffer driving a capacitive load. Equation 1 shows the transfer function for the

circuit in Figure 41. Not shown in Figure 41 is the open-loop output resistance of the operational amplifier, Ro.

(1)

The transfer function in Equation 1 has a pole and a zero. The frequency of the pole (fp) is determined by (Ro+

RISO) and CLOAD. Components RISO and CLOAD determine the frequency of the zero (fz). A stable system is

obtained by selecting RISO such that the rate of closure (ROC) between the open-loop gain (AOL) and 1/βis 20

dB/decade. Figure 42 depicts the concept. The 1/βcurve for a unity-gain buffer is 0 dB.

Figure 42. Unity-Gain Amplifier With RISO Compensation

ROC stability analysis is typically simulated. The validity of the analysis depends on multiple factors, especially

the accurate modeling of Ro. In addition to simulating the ROC, a robust stability analysis includes a

measurement of overshoot percentage and ac gain peaking of the circuit using a function generator,

oscilloscope, and gain and phase analyzer. Phase margin is then calculated from these measurements. Table 3

shows the overshoot percentage and ac gain peaking that correspond to phase margins of 45° and 60°. For

more details on this design and other alternative devices that can be used in place of the OPA170, see the

Precision Design, Capacitive Load Drive Solution Using an Isolation Resistor.

Table 3. Phase Margin versus Overshoot and AC Gain

Peaking

PHASE

MARGIN OVERSHOOT AC GAIN PEAKING

45° 23.3% 2.35 dB

60° 8.8% 0.28 dB

100

1000

10000

0.1 1 10 100 1000

Isolation Resistor (RISO, )

Capacitive Load (nF)

45° Phase Margin

60° Phase Margin

C002

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9.2.3 Application Curve

Using the described methodology, the values of RISO that yield phase margins of 45º and 60º for various

capacitive loads were determined. The results are shown in Figure 43.

Figure 43. Isolation Resistor Required for Various Capacitive Loads to Achieve a Target Phase Margin

VIN

VOUT

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10 Power Supply Recommendations

The OPAx170 is specified for operation from 2.7 V to 36 V (±1.35 V to ±18 V); many specifications apply from

–40°C to 85°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature

are presented in the Typical Characteristics.

CAUTION

Supply voltages larger than 40 V can permanently damage the device; see the

Absolute Maximum Ratings.

Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-

impedance power supplies. For more detailed information on bypass capacitor placement, see the Layout

section.

11 Layout

11.1 Layout Guidelines

For best operational performance of the device, use good printed-circuit board (PCB) layout practices, including:

• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the

operational amplifier itself. Bypass capacitors are used to reduce the coupled noise by providing low-

impedance power sources local to the analog circuitry.

– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as

close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-

supply applications.

• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective

methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground

planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically

separate digital and analog grounds, paying attention to the flow of the ground current. For more detailed

information, see application report SLOA089,Circuit Board Layout Techniques.

• In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as

possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicularly is much

better than in parallel with the noisy trace.

• Place the external components as close to the device as possible. As illustrated in Figure 45, keeping RF

and RGclose to the inverting input minimizes parasitic capacitance.

• Keep the length of input traces as short as possible. Always remember that the input traces are the most

sensitive part of the circuit.

• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly

reduce leakage currents from nearby traces that are at different potentials.

11.2 Layout Example

Figure 44. Schematic Representation

±IN

+IN

V±

V+

OUTPUT

VS+

VS±GND

Ground (GND) plane on another layer

VOUT

VIN

GND

Run the input traces

as far away from

the supply lines

as possible RF

Place components close

to device and to each

other to reduce parasitic

errors

Use low-ESR,

ceramic bypass

capacitor

GND

Use a low-ESR,

ceramic bypass

capacitor

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Layout Example (continued)

Figure 45. Operational Amplifier Board Layout for a Noninverting Configuration

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12 Device and Documentation Support

12.1 Device Support

12.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

12.1.2 Development Support

12.1.2.1 TINA-TI™ (Free Software Download)

TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI™ is

a free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a

range of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency

domain analysis of SPICE, as well as additional design capabilities.

Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing

capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select

input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.

NOTE

These files require that either the TINA software (from DesignSoft™) or TINA-TI software

be installed. Download the free TINA-TI software from the TINA-TI folder.

12.1.2.2 DIP Adapter EVM

The DIP Adapter EVM tool provides an easy, low-cost way to prototype small surface mount ICs. The evaluation

tool these TI packages: D or U (SOIC-8), PW (TSSOP-8), DGK (MSOP-8), DBV (SOT23-6, SOT23-5 and

SOT23-3), DCK (SC70-6 and SC70-5), and DRL (SOT563-6). The DIP Adapter EVM may also be used with

terminal strips or may be wired directly to existing circuits.

12.1.2.3 Universal Operational Amplifier EVM

The Universal Op Amp EVM is a series of general-purpose, blank circuit boards that simplify prototyping circuits

for a variety of IC package types. The evaluation module board design allows many different circuits to be

constructed easily and quickly. Five models are offered, with each model intended for a specific package type.

PDIP, SOIC, MSOP, TSSOP and SOT23 packages are all supported.

NOTE

These boards are unpopulated, so users must provide their own ICs. TI recommends

requesting several op amp device samples when ordering the Universal Op Amp EVM.

12.1.2.4 TI Precision Designs

TI Precision Designs are analog solutions created by TI’s precision analog applications experts and offer the

theory of operation, component selection, simulation, complete PCB schematic and layout, bill of materials, and

measured performance of many useful circuits. TI Precision Designs are available online at

http://www.ti.com/ww/en/analog/precision-designs/.

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Device Support (continued)

12.1.2.5 WEBENCH®Filter Designer

WEBENCH® Filter Designer is a simple, powerful, and easy-to-use active filter design program. The WEBENCH

Filter Designer lets you create optimized filter designs using a selection of TI operational amplifiers and passive

components from TI's vendor partners.

Available as a web-based tool from the WEBENCH® Design Center, WEBENCH® Filter Designer allows you to

design, optimize, and simulate complete multistage active filter solutions within minutes.

12.1.2.6 Custom Design With WEBENCH® Tools

Click here to create a custom design using the OPAx170 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance

• Run thermal simulations to understand board thermal performance

• Export customized schematic and layout into popular CAD formats

• Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

12.2 Documentation Support

12.2.1 Related Documentation

For related documentation, see the following (available for download from www.ti.com):

•Feedback Plots Define Op Amp AC Performance

•Capacitive Load Drive Solution Using an Isolation Resistor

•Circuit Board Layout Techniques

12.3 Related Links

The table below lists quick access links. Categories include technical documents, support and community

resources, tools and software, and quick access to order now.

Table 4. Related Links

PARTS PRODUCT FOLDER ORDER NOW TECHNICAL

DOCUMENTS TOOLS &

SOFTWARE SUPPORT &

COMMUNITY

OPA170 Click here Click here Click here Click here Click here

OPA2170 Click here Click here Click here Click here Click here

OPA4170 Click here Click here Click here Click here Click here

12.4 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

12.5 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

OPA170

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Product Folder Links: OPA170 OPA2170 OPA4170

Community Resources (continued)

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

12.6 Trademarks

TINA-TI, E2E are trademarks of Texas Instruments.

WEBENCH is a registered trademark of Texas Instruments.

TINA, DesignSoft are trademarks of DesignSoft, Inc.

All other trademarks are the property of their respective owners.

12.7 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

12.8 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM

www.ti.com 11-Apr-2018

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

OPA170AID ACTIVE SOIC D 8 75 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 O170A

OPA170AIDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 OSVI

OPA170AIDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 OSVI

OPA170AIDR ACTIVE SOIC D 8 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 O170A

OPA170AIDRLR ACTIVE SOT-5X3 DRL 5 4000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 DAQ

OPA170AIDRLT ACTIVE SOT-5X3 DRL 5 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 DAQ

OPA2170AID ACTIVE SOIC D 8 75 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 2170A

OPA2170AIDCUR ACTIVE VSSOP DCU 8 3000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 OPQC

OPA2170AIDCUT ACTIVE VSSOP DCU 8 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 OPQC

OPA2170AIDGK ACTIVE VSSOP DGK 8 80 Green (RoHS

& no Sb/Br) CU NIPDAUAG Level-2-260C-1 YEAR -40 to 125 OPNI

OPA2170AIDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS

& no Sb/Br) CU NIPDAUAG Level-2-260C-1 YEAR -40 to 125 OPNI

OPA2170AIDR ACTIVE SOIC D 8 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 2170A

OPA2170AIDSGR ACTIVE WSON DSG 8 3000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 1D4U

OPA2170AIDSGT ACTIVE WSON DSG 8 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 1D4U

OPA4170AID ACTIVE SOIC D 14 50 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 OPA4170

OPA4170AIDR ACTIVE SOIC D 14 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 OPA4170

OPA4170AIPW ACTIVE TSSOP PW 14 90 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 OPA4170

PACKAGE OPTION ADDENDUM

www.ti.com 11-Apr-2018

Addendum-Page 2

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

OPA4170AIPWR ACTIVE TSSOP PW 14 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 OPA4170

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF OPA170, OPA2170, OPA4170 :

•Automotive: OPA170-Q1, OPA2170-Q1, OPA4170-Q1

PACKAGE OPTION ADDENDUM

www.ti.com 11-Apr-2018

Addendum-Page 3

•Enhanced Product: OPA170-EP

NOTE: Qualified Version Definitions:

•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

•Enhanced Product - Supports Defense, Aerospace and Medical Applications

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

OPA170AIDBVR SOT-23 DBV 5 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3

OPA170AIDBVR SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

OPA170AIDBVT SOT-23 DBV 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

OPA170AIDBVT SOT-23 DBV 5 250 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3

OPA170AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

OPA170AIDRLR SOT-5X3 DRL 5 4000 180.0 8.4 1.98 1.78 0.69 4.0 8.0 Q3

OPA170AIDRLT SOT-5X3 DRL 5 250 180.0 8.4 1.98 1.78 0.69 4.0 8.0 Q3

OPA2170AIDCUR VSSOP DCU 8 3000 180.0 8.4 2.25 3.35 1.05 4.0 8.0 Q3

OPA2170AIDCUT VSSOP DCU 8 250 180.0 8.4 2.25 3.35 1.05 4.0 8.0 Q3

OPA2170AIDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

OPA2170AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

OPA2170AIDSGR WSON DSG 8 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2

OPA2170AIDSGT WSON DSG 8 250 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2

OPA4170AIDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

OPA4170AIPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 30-Apr-2018

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

OPA170AIDBVR SOT-23 DBV 5 3000 223.0 270.0 35.0

OPA170AIDBVR SOT-23 DBV 5 3000 195.0 200.0 45.0

OPA170AIDBVT SOT-23 DBV 5 250 195.0 200.0 45.0

OPA170AIDBVT SOT-23 DBV 5 250 202.0 201.0 28.0

OPA170AIDR SOIC D 8 2500 367.0 367.0 35.0

OPA170AIDRLR SOT-5X3 DRL 5 4000 202.0 201.0 28.0

OPA170AIDRLT SOT-5X3 DRL 5 250 202.0 201.0 28.0

OPA2170AIDCUR VSSOP DCU 8 3000 202.0 201.0 28.0

OPA2170AIDCUT VSSOP DCU 8 250 202.0 201.0 28.0

OPA2170AIDGKR VSSOP DGK 8 2500 366.0 364.0 50.0

OPA2170AIDR SOIC D 8 2500 367.0 367.0 35.0

OPA2170AIDSGR WSON DSG 8 3000 210.0 185.0 35.0

OPA2170AIDSGT WSON DSG 8 250 210.0 185.0 35.0

OPA4170AIDR SOIC D 14 2500 367.0 367.0 38.0

OPA4170AIPWR TSSOP PW 14 2000 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 30-Apr-2018

Pack Materials-Page 2

www.ti.com

PACKAGE OUTLINE

SEE OPTIONAL

TERMINAL 8X 0.3

0.2

1.6 0.1

1.5

0.9 0.1

6X 0.5

8X 0.4

0.2

0.05

0.00

0.8 MAX

A2.1

1.9 B

2.1

1.9

0.3

0.2

0.4

0.2

(0.2) TYP

WSON - 0.8 mm max heightDSG0008A

PLASTIC SMALL OUTLINE - NO LEAD

4218900/B 09/2017

PIN 1 INDEX AREA

SEATING PLANE

0.08 C

PIN 1 ID 0.1 C A B

0.05 C

THERMAL PAD

EXPOSED

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

SCALE 5.500

OPTIONAL TERMINAL

TYPICAL

www.ti.com

EXAMPLE BOARD LAYOUT

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

8X (0.25)

(1.6)

(1.9)

6X (0.5)

(0.9) ( 0.2) VIA

TYP

(0.55)

8X (0.5)

(R0.05) TYP

WSON - 0.8 mm max heightDSG0008A

PLASTIC SMALL OUTLINE - NO LEAD

4218900/B 09/2017

SYMM

LAND PATTERN EXAMPLE

SCALE:20X

SYMM 9

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

SOLDER MASK

OPENING

SOLDER MASK

METAL UNDER

SOLDER MASK

DEFINED

METAL

SOLDER MASK

OPENING

SOLDER MASK DETAILS

NON SOLDER MASK

DEFINED

(PREFERRED)

www.ti.com

EXAMPLE STENCIL DESIGN

(R0.05) TYP

8X (0.25)

8X (0.5)

(0.9)

(0.7)

(1.9)

(0.45)

6X (0.5)

WSON - 0.8 mm max heightDSG0008A

PLASTIC SMALL OUTLINE - NO LEAD

4218900/B 09/2017

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 9:

87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:25X

SYMM

METAL

SYMM 9

www.ti.com

PACKAGE OUTLINE

TYP

0.22

0.08

0.25

3.0

2.6

2X 0.95

1.9

1.45 MAX

TYP

0.15

0.00

5X 0.5

0.3

TYP

0.6

0.3

TYP

1.9

3.05

2.75

1.75

1.45

(1.1)

SOT-23 - 1.45 mm max heightDBV0005A

SMALL OUTLINE TRANSISTOR

4214839/C 04/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. Refernce JEDEC MO-178.

0.2 C A B

INDEX AREA

PIN 1

GAGE PLANE

SEATING PLANE

0.1 C

SCALE 4.000

www.ti.com

EXAMPLE BOARD LAYOUT

0.07 MAX

ARROUND 0.07 MIN

ARROUND

5X (1.1)

5X (0.6)

(2.6)

(1.9)

2X (0.95)

(R0.05) TYP

4214839/C 04/2017

SOT-23 - 1.45 mm max heightDBV0005A

SMALL OUTLINE TRANSISTOR

NOTES: (continued)

4. Publication IPC-7351 may have alternate designs.

5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:15X

PKG

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

DEFINED

EXPOSED METAL

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

EXPOSED METAL

www.ti.com

EXAMPLE STENCIL DESIGN

(2.6)

(1.9)

2X(0.95)

5X (1.1)

5X (0.6)

(R0.05) TYP

SOT-23 - 1.45 mm max heightDBV0005A

SMALL OUTLINE TRANSISTOR

4214839/C 04/2017

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

7. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:15X

SYMM

PKG

www.ti.com

PACKAGE OUTLINE

TYP

0.22

0.08

0.25

3.0

2.6

2X 0.95

1.9

1.45 MAX

TYP

0.15

0.00

5X 0.5

0.3

TYP

0.6

0.3

TYP

1.9

3.05

2.75

1.75

1.45

(1.1)

SOT-23 - 1.45 mm max heightDBV0005A

SMALL OUTLINE TRANSISTOR

4214839/C 04/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. Refernce JEDEC MO-178.

0.2 C A B

INDEX AREA

PIN 1

GAGE PLANE

SEATING PLANE

0.1 C

SCALE 4.000

www.ti.com

EXAMPLE BOARD LAYOUT

0.07 MAX

ARROUND 0.07 MIN

ARROUND

5X (1.1)

5X (0.6)

(2.6)

(1.9)

2X (0.95)

(R0.05) TYP

4214839/C 04/2017

SOT-23 - 1.45 mm max heightDBV0005A

SMALL OUTLINE TRANSISTOR

NOTES: (continued)

4. Publication IPC-7351 may have alternate designs.

5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:15X

PKG

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

DEFINED

EXPOSED METAL

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

EXPOSED METAL

www.ti.com

EXAMPLE STENCIL DESIGN

(2.6)

(1.9)

2X(0.95)

5X (1.1)

5X (0.6)

(R0.05) TYP

SOT-23 - 1.45 mm max heightDBV0005A

SMALL OUTLINE TRANSISTOR

4214839/C 04/2017

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

7. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:15X

SYMM

PKG

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Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

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OPA2170AIDGK OPA2170AIDGKR OPA2170AID OPA2170AIDR OPA2170AIDCUR OPA2170AIDCUT