250 MHz Bandwidth DPD Observation Receiver AD6641 FEATURES GENERAL DESCRIPTION SNR = 65.8 dBFS at fIN up to 250 MHz at 500 MSPS ENOB of 10.5 bits at fIN up to 250 MHz at 500 MSPS (-1.0 dBFS) SFDR = 80 dBc at fIN up to 250 MHz at 500 MSPS (-1.0 dBFS) Excellent linearity DNL = 0.5 LSB typical, INL = 0.6 LSB typical Integrated 16k x 12 FIFO FIFO readback options 12-bit parallel CMOS at 62.5 MHz 6-bit DDR LVDS interface SPORT at 62.5 MHz SPI at 25 MHz High speed synchronization capability 1 GHz full power analog bandwidth Integrated input buffer On-chip reference, no external decoupling required Low power dissipation 695 mW at 500 MSPS Programmable input voltage range 1.18 V to 1.6 V, 1.5 V nominal 1.9 V analog and digital supply operation 1.9 V or 3.3 V SPI and SPORT operation Clock duty cycle stabilizer Integrated data clock output with programmable clock and data alignment The AD6641 is a 250 MHz bandwidth digital predistortion (DPD) observation receiver that integrates a 12-bit 500 MSPS ADC, a 16k x 12 FIFO, and a multimode back end that allows users to retrieve the data through a serial port (SPORT), the SPI interface, a 12-bit parallel CMOS port, or a 6-bit DDR LVDS port after being stored in the integrated FIFO memory. It is optimized for outstanding dynamic performance and low power consumption and is suitable for use in telecommunications applications such as a digital predistortion observation path where wider bandwidths are desired. All necessary functions, including the sample-and-hold and voltage reference, are included on the chip to provide a complete signal conversion solution. The on-chip FIFO allows small snapshots of time to be captured via the ADC and read back at a lower rate. This reduces the constraints of signal processing by transferring the captured data at an arbitrary time and at a much lower sample rate. The FIFO can be operated in several user-programmable modes. In the single capture mode, the ADC data is captured when signaled via the SPI port or the use of the external FILL pins. In the continuous capture mode, the data is loaded continuously into the FIFO and the FILL pins are used to stop this operation. APPLICATIONS Wireless and wired broadband communications Communications test equipment Power amplifier linearization FUNCTIONAL BLOCK DIAGRAM FILL+ CLK- DUMP CLOCK AND CONTROL VIN+ ADC VIN- REFERENCE FIFO 16k x 12 PARALLEL AND SPORT OUTPUTS SPI CONTROL AND DATA PCLK+ PCLK- PD[5:0] IN DDR LVDS MODE OR PD[11:0] IN CMOS MODE SP_SCLK SP_SDFS SP_SDO FULL EMPTY VREF SCLK, SDIO, AND CSB 09813-001 CLK+ FILL- Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2011 Analog Devices, Inc. All rights reserved. AD6641 TABLE OF CONTENTS Features .............................................................................................. 1 Thermal Resistance .................................................................... 10 Applications....................................................................................... 1 ESD Caution................................................................................ 10 General Description ......................................................................... 1 Pin Configurations and Function Descriptions ......................... 11 Functional Block Diagram .............................................................. 1 Typical Performance Characteristics ........................................... 15 Revision History ............................................................................... 2 Equivalent Circuits......................................................................... 18 Product Highlights ........................................................................... 3 SPI Register Map ............................................................................ 20 Specifications..................................................................................... 4 Theory of Operation ...................................................................... 23 DC Specifications ......................................................................... 4 FIFO Operation.......................................................................... 23 AC Specifications.......................................................................... 5 FIFO Output Interfaces ............................................................. 26 Digital Specifications ................................................................... 6 Configuration Using the SPI..................................................... 27 Switching Specifications .............................................................. 7 Outline Dimensions ....................................................................... 28 SPI Timing Requirements ........................................................... 8 Ordering Guide .......................................................................... 28 Absolute Maximum Ratings.......................................................... 10 REVISION HISTORY 4/11--Revision 0: Initial Version Rev. 0 | Page 2 of 28 AD6641 The data stored in the FIFO can be read back based on several user-selectable output modes. The DUMP pin can be asserted to output the FIFO data. The data stored in the FIFO can be accessed via a SPORT, SPI, 12-bit parallel CMOS port, or 6-bit DDR LVDS interface. The maximum output throughput supported by the AD6641 is in the 12-bit CMOS or 6-bit DDR LVDS mode and is internally limited to 1/8th of the maximum input sample rate. This corresponds to the maximum output data rate of 62.5 MHz at an input clock rate of 500 MSPS. The ADC requires a 1.9 V analog voltage supply and a differential clock for full performance operation. Output format options include twos complement, offset binary format, or Gray code. A data clock output is available for proper output data timing. Fabricated on an advanced SiGe BiCMOS process, the device is available in a 56-lead LFCSP and is specified over the industrial temperature range (-40C to +85C). This product is protected by a U.S. patent. PRODUCT HIGHLIGHTS 1. 2. 3. 4. 5. Rev. 0 | Page 3 of 28 High Performance ADC Core. Maintains 65.8 dBFS SNR at 500 MSPS with a 250 MHz input. Low Power. Consumes only 695 mW at 500 MSPS. Ease of Use. On-chip 16k FIFO allows the user to target the high performance ADC to the time period of interest and reduce the constraints of processing the data by transferring it at an arbitrary time and a lower sample rate. The on-chip reference and sample-and-hold provide flexibility in system design. Use of a single 1.9 V supply simplifies system power supply design. Serial Port Control. Standard serial port interface supports configuration of the device and customization for the user's needs. 1.9 V or 3.3 V SPI and Serial Data Port Operation. AD6641 SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.9 V, DRVDD = 1.9 V, TMIN = -40C, TMAX = +85C, fIN = -1.0 dBFS, full scale = 1.5 V, unless otherwise noted. Table 1. Parameter1 RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error Gain Error ANALOG INPUTS (VIN) Differential Input Voltage Range2 Input Common-Mode Voltage Input Resistance (Differential) Input Capacitance (Differential) POWER SUPPLY AVDD DRVDD SPI_VDDIO Supply Currents IAVDD3 IDRVDD3 Power Dissipation3 Power-Down Dissipation Standby Dissipation Standby to Power-Up Time Temp Full Full Full Full Full Min -2.6 -6.8 Full Full AD6641-500 Typ Max 12 Unit Bits Guaranteed 0.0 +1.8 -2.3 +3.3 0.5 0.6 mV % FS LSB LSB 18 0.07 V/C %/C Full Full Full 25C 1.18 1.5 1.8 1 1.3 1.6 V p-p V k pF Full Full Full 1.8 1.8 1.8 1.9 1.9 1.9 2.0 2.0 3.3 V V V 300 66 695 15 72 10 330 80 779 mA mA mW mW mW s Full Full Full Full Full Full 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and information about how these tests were completed. 2 The input range is programmable through the SPI, and the range specified reflects the nominal values of each setting. See the SPI Register Map section for additional details. 3 IAVDD and IDRVDD are measured with a -1 dBFS, 30 MHz sine input at a rated sample rate. Rev. 0 | Page 4 of 28 AD6641 AC SPECIFICATIONS AVDD = 1.9 V, DRVDD = 1.9 V, TMIN = -40C, TMAX = +85C, fIN = -1.0 dBFS, full scale = 1.5 V, unless otherwise noted. Table 2. Parameter 1, 2 SNR fIN = 30 MHz fIN = 125 MHz Temp 25C 25C Full 25C 25C fIN = 250 MHz fIN = 450 MHz SINAD fIN = 30 MHz fIN = 125 MHz 25C 25C Full 25C 25C fIN = 250 MHz fIN = 450 MHz EFFECTIVE NUMBER OF BITS (ENOB) fIN = 30 MHz fIN = 125 MHz fIN = 250 MHz fIN = 450 MHz SFDR fIN = 30 MHz fIN = 125 MHz fIN = 250 MHz fIN = 450 MHz WORST HARMONIC (SECOND OR THIRD) fIN = 30 MHz fIN = 125 MHz fIN = 250 MHz fIN = 450 MHz WORST OTHER HARMONIC (SFDR EXCLUDING SECOND AND THIRD) fIN = 30 MHz fIN = 125 MHz fIN = 250 MHz fIN = 450 MHz TWO-TONE IMD fIN1 = 119.8 MHz, fIN2 = 125.8 MHz (-7 dBFS, Each Tone) ANALOG INPUT BANDWIDTH 1 2 Min AD6641-500 Typ Max 66.0 65.9 Unit dBFS dBFS dBFS dBFS dBFS 65.0 65.8 65.1 66.0 65.7 65.3 64.6 dBFS dBFS dBFS dBFS dBFS 25C 25C 25C 25C 10.7 10.6 10.5 10.4 Bits Bits Bits Bits 25C 25C Full 25C 25C 88 83 dBc dBc dBc dBc dBc 63.8 77 80 72 25C 25C Full 25C 25C -92 25C 25C Full 25C 25C -90 -90 -85 -78 dBc dBc dBc dBc dBc 25C 25C -82 1 dBc GHz -77 -84 -80 -72 -77 dBc dBc dBc dBc dBc All ac specifications tested by driving CLK+ and CLK- differentially. See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and information about how these tests were completed. Rev. 0 | Page 5 of 28 AD6641 DIGITAL SPECIFICATIONS AVDD = 1.9 V, DRVDD = 1.9 V, TMIN = -40C, TMAX = +85C, fIN = -1.0 dBFS, full scale = 1.5 V, unless otherwise noted. Table 3. Parameter 1 CLOCK INPUTS (CLK) Logic Compliance Internal Common-Mode Bias Differential Input Voltage High Level Input (VIH) Low Level Input (VIL) High Level Input Current (IIH) Low Level Input Current (IIL) Input Resistance (Differential) Input Capacitance LOGIC INPUTS (SPI, SPORT) Logic Compliance Logic 1 Voltage Logic 0 Voltage Logic 1 Input Current (SDIO) Logic 0 Input Current (SDIO) Logic 1 Input Current (SCLK) Logic 0 Input Current (SCLK) Input Capacitance LOGIC INPUTS (DUMP, CSB) Logic Compliance Logic 1 Voltage Logic 0 Voltage Logic 1 Input Current Logic 0 Input Current Input Capacitance LOGIC INPUTS (FILL) Logic Compliance Internal Common-Mode Bias Differential Input Voltage High Level Input (VIH) Low Level Input (VIL) High Level Input Current (IIH) Low Level Input Current (IIL) Input Resistance (Differential) Input Capacitance LOGIC OUTPUTS 2 (FULL, EMPTY) Logic Compliance High Level Output Voltage Low Level Output Voltage LOGIC OUTPUTS2 (SPI, SPORT) Logic Compliance High Level Output Voltage Low Level Output Voltage Temp Min Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full 25C Full Full Full Full Full 25C CMOS/LVDS/LVPECL 0.9 0.2 -1.8 -10 -10 8 10 4 1.8 -0.2 +10 +10 12 Unit V V p-p V p-p A A k pF CMOS 0.8 x SPI_VDDIO 0.2 x SPI_VDDIO 0 -60 50 0 4 V V A A A A pF CMOS 0.8 x DRVDD 0.2 x DRVDD 0 -60 4 Full Full Full Full Full Full Full Full AD6641-500 Typ Max CMOS/LVDS/LVPECL 0.9 0.2 -1.8 -10 -10 8 Full Full Full DRVDD - 0.05 Full Full Full SPI_VDDIO - 0.05 10 4 1.8 -0.2 +10 +10 12 V V A A pF V V p-p V p-p A A k pF CMOS DRGND + 0.05 V V DRGND + 0.05 V V CMOS Rev. 0 | Page 6 of 28 AD6641 Parameter1 LOGIC OUTPUTS DDR LVDS Mode (PCLK, PD[5:0], PDOR) Logic Compliance VOD Differential Output Voltage VOS Output Offset Voltage Parallel CMOS Mode (PCLK, PD[11:0]) Logic Compliance High Level Output Voltage Low Level Output Voltage Output Coding Temp Min Full Full Full 247 1.125 Full Full Full AD6641-500 Typ Max Unit LVDS 454 1.375 mV V CMOS DRVDD - 0.05 DRGND + 0.05 Twos complement, Gray code, or offset binary (default) V V 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and information about how these tests were completed. 2 5 pF loading. SWITCHING SPECIFICATIONS AVDD = 1.9 V, DRVDD = 1.9 V, TMIN = -40C, TMAX = +85C, fIN = -1.0 dBFS, full scale = 1.5 V, unless otherwise noted. Table 4. Parameter1 OUTPUT DATA RATE Maximum Output Data Rate (Decimate by 8 at 500 MSPS Sample Rate, Parallel CMOS or DDR LVDS Mode Interface) Maximum Output Data Rate (Decimate by 8 at 500 MSPS Sample Rate, SPORT Mode) PULSE WIDTH/PERIOD (CLK) CLK Pulse Width High (tCH) CLK Pulse Width Low (tCL) Rise Time (tR) (20% to 80%) Fall Time (tF) (20% to 80%) PULSE WIDTH/PERIOD (PCLK, DDR LVDS MODE) PCLK Pulse Width High (tPCLK_CH) PCLK Period (tPCLK) Propagation Delay (tCPD, CLK to PCLK) Rise Time (tR) (20% to 80%) Fall Time (tF) (20% to 80%) Data to PCLK Skew (tSKEW) SERIAL PORT OUTPUT TIMING2 SP_SDFS Propagation Delay (tDSDFS) SP_SDO Propagation Delay (tDSDO) SERIAL PORT INPUT TIMING SP_SDFS Setup Time (tSSF) SP_SDFS Hold Time (tHSF) FILL INPUT TIMING FILL Setup Time (tSfill) FILL Hold Time (tHfill) APERTURE DELAY (tA) APERTURE UNCERTAINTY (JITTER, tJ) 1 2 AD6641-500 Typ Max Temp Min Unit Full 62.5 MHz Full 62.5 MHz Full Full 25C 25C 1 1 0.2 0.2 ns ns ns ns Full Full Full 25C 25C Full 8 16 0.1 0.2 0.2 0.2 ns ns ns ns ns ns Full Full 3 3 ns ns Full Full 2 2 ns ns Full Full 25C 25C 0.5 0.7 0.85 80 ns ns ns fs rms See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and information about how these tests were completed. 5 pF loading. Rev. 0 | Page 7 of 28 AD6641 SPI TIMING REQUIREMENTS Table 5. Parameter tDS tDH tCLK tS tH tHIGH tLOW tEN_SDIO tDIS_SDIO Description Setup time between the data and the rising edge of SCLK Hold time between the data and the rising edge of SCLK Period of the SCLK Setup time between CSB and SCLK Hold time between CSB and SCLK SCLK pulse width high SCLK pulse width low Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge Limit 2 2 40 2 2 10 10 10 10 Unit ns min ns min ns min ns min ns min ns min ns min ns min ns min Timing Diagrams N-1 tA N+4 N+5 N N+3 VIN N+1 tCL 09813-002 tCH N+2 CLK+ CLK- Figure 2. Input Interface Timing CLK+ CLK- tCPD tPCLK_CH PCLK+ PCLK- 09813-003 tSKEW OUTPUT DATA BUS Figure 3. Parallel CMOS Mode Output Interface Timing SP_SCLK tDSDFS 09813-004 PD[11:0] tPCLK SP_SDFS Figure 4. SP_SDFS Propagation Delay Rev. 0 | Page 8 of 28 AD6641 tDSDO SP_SDO D11 D10 09813-005 SP_SCLK Figure 5. SP_SDO Propagation Delay SP_SCLK tHSF 09813-006 tSSF SP_SDFS Figure 6. Slave Mode SP_SDFS Setup/Hold Time CLK tHfill 09813-007 tSfill FILL Figure 7. FILL Setup and Hold Times Rev. 0 | Page 9 of 28 AD6641 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Electrical AVDD to AGND DRVDD to DRGND AGND to DRGND AVDD to DRVDD SPI_VDDIO to AVDD SPI_VDDIO to DRVDD PD[5:0] to DRGND PCLK to DRGND PDOR to DRGND FULL to DRGND CLK to AGND FILL to AGND DUMP to AGND EMPTY to AGND VIN to AGND VREF to AGND CML to AGND CSB to DRGND SP_SCLK, SP_SDFS to AGND SDIO to DRGND SP_SDO to DRGND Environmental Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering, 10 sec) Junction Temperature Rating -0.3 V to +2.0 V -0.3 V to +2.0 V -0.3 V to +0.3 V -2.0 V to +2.0 V -2.0 V to +2.0 V -2.0 V to +2.0 V -0.3 V to DRVDD + 0.2 V -0.3 V to DRVDD + 0.2 V -0.3 V to DRVDD + 0.2 V -0.3 V to DRVDD + 0.2 V -0.3 V to AVDD + 0.2 V -0.3 V to DRVDD + 0.2 V -0.3 V to DRVDD + 0.2 V -0.3 V to DRVDD + 0.2 V -0.3 V to AVDD + 0.2 V -0.3 V to AVDD + 0.2 V -0.3 V to AVDD + 0.2 V -0.3 V to SPI_VDDIO + 0.3 V -0.3 V to SPI_VDDIO + 0.3 V -0.3 V to SPI_VDDIO + 0.3 V -0.3 V to SPI_VDDIO + 0.3 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE The exposed pad must be soldered to the ground plane for the LFCSP package. Soldering the exposed pad to the PCB increases the reliability of the solder joints, maximizing the thermal capability of the package. Table 7. Package Type 56-Lead LFCSP_VQ (CP-56-1) JA 23.7 JC 1.7 Unit C/W Typical JA and JC are specified for a 4-layer board in still air. Airflow increases heat dissipation, effectively reducing JA. In addition, metal in direct contact with the package leads from metal traces, through holes, ground, and power planes reduces the JA. ESD CAUTION -65C to +125C -40C to +85C 300C 150C Rev. 0 | Page 10 of 28 AD6641 56 55 54 53 52 51 50 49 48 47 46 45 44 43 PCLK+ PCLK- DNC DUMP EMPTY FULL FILL- FILL+ DRGND DRVDD AVDD CLK- CLK+ AVDD PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PIN 1 INDICATOR AD6641 TOP VIEW (Not to Scale) 42 41 40 39 38 37 36 35 34 33 32 31 30 29 AVDD AVDD CML AVDD AVDD AVDD VIN- VIN+ AVDD AVDD AVDD VREF AVDD SPI_VDDIO NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN. 2. THE EXPOSED PAD IS THE ONLY ANALOG GROUND CONNECTION FOR THE CHIP. IT MUST BE CONNECTED TO PCB AGND. 09813-008 PDOR- PDOR+ SP_SDO DNC DNC DNC SP_SDFS SP_SCLK DRGND DRVDD SDIO SCLK CSB DNC 15 16 17 18 19 20 21 22 23 24 25 26 27 28 PD0- PD0+ PD1- PD1+ PD2- PD2+ DRVDD DRGND PD3- PD3+ PD4- PD4+ PD5- PD5+ Figure 8. Pin Configuration for DDR LVDS Mode Table 8. DDR LVDS Mode Pin Function Descriptions Pin No. 0 Mnemonic EPAD 1 2 3 4 5 6 7, 24, 47 8, 23, 48 9 10 11 12 13 14 15 16 17 18, 19, 20, 28, 54 21 22 25 26 27 29 30, 32, 33, 34, 37, 38, 39, 41, 42, 43, 46 31 35 36 PD0- PD0+ PD1- PD1+ PD2- PD2+ DRVDD DRGND PD3- PD3+ PD4- PD4+ PD5- PD5+ PDOR- PDOR+ SP_SDO DNC SP_SDFS SP_SCLK SDIO SCLK CSB SPI_VDDIO AVDD Description Exposed Pad. The exposed pad is the only ground connection for the chip. The pad must be connected to PCB AGND. PD0 Data Output (LSB)--Complement. PD0 Data Output (LSB)--True. PD1 Data Output--Complement. PD1 Data Output--True. PD2 Data Output--Complement. PD2 Data Output--True. 1.9 V Digital Output Supply. Digital Output Ground. PD3 Data Output--Complement. PD3 Data Output--True. PD4 Data Output--Complement. PD4 Data Output--True. PD5 Data Output (MSB)--Complement. PD5 Data Output (MSB)--True. Overrange Output--Complement. Overrange Output--True. SPORT Output. Do Not Connect. Do not connect to this pin. SPORT Frame Sync Input (Slave Mode)/Output (Master Mode). SPORT Clock Input (Slave Mode)/Output (Master Mode). Serial Port Interface (SPI) Data Input/Output (Serial Port Mode). Serial Port Interface Clock (Serial Port Mode). Serial Port Chip Select (Active Low). 1.9 V or 3.3 V SPI I/O Supply. 1.9 V Analog Supply. VREF VIN+ VIN- Voltage Reference Input/Output. Nominally 0.75 V. Analog Input--True. Analog Input--Complement. Rev. 0 | Page 11 of 28 AD6641 Pin No. 40 Mnemonic CML 44 45 49 50 51 52 53 55 56 CLK+ CLK- FILL+ FILL- FULL EMPTY DUMP PCLK- PCLK+ Description Common-Mode Output. Enabled through the SPI, this pin provides a reference for the optimized internal bias voltage for VIN+ and VIN-. Clock Input--True. Clock Input--Complement. FIFO Fill Input (LVDS)--True. FIFO Fill Input (LVDS)--Complement. FIFO Full Output Indicator. FIFO Empty Output Indicator. FIFO Readback Input. Data Clock Output--Complement. Data Clock Output--True. Rev. 0 | Page 12 of 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 PCLK+ PCLK- DNC DUMP EMPTY FULL FILL- FILL+ DRGND DRVDD AVDD CLK- CLK+ AVDD AD6641 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PIN 1 INDICATOR AD6641 TOP VIEW (Not to Scale) 42 41 40 39 38 37 36 35 34 33 32 31 30 29 AVDD AVDD CML AVDD AVDD AVDD VIN- VIN+ AVDD AVDD AVDD VREF AVDD SPI_VDDIO 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN. 2. THE EXPOSED PAD IS THE ONLY ANALOG GROUND CONNECTION FOR THE CHIP. IT MUST BE CONNECTED TO PCB AGND. 09813-009 PD10 PD11 SP_SDO DNC DNC DNC SP_SDFS SP_SCLK DRGND DRVDD SDIO SCLK CSB DNC 15 16 17 18 19 20 21 22 23 24 25 26 27 28 DNC DNC PD0 PD1 PD2 PD3 DRVDD DRGND PD4 PD5 PD6 PD7 PD8 PD9 Figure 9. Pin Configuration for Parallel CMOS Mode Table 9. Parallel CMOS Mode Pin Function Descriptions Pin No. 0 Mnemonic EPAD 1, 2, 18, 19, 20, 28, 54 3 4 5 6 7, 24, 47 8, 23, 48 9 10 11 12 13 14 15 16 17 21 22 25 26 27 29 30, 32, 33, 34, 37, 38, 39, 41, 42, 43, 46 31 35 36 40 DNC PD0 PD1 PD2 PD3 DRVDD DRGND PD4 PD5 PD6 PD7 PD8 PD9 PD10 PD11 SP_SDO SP_SDFS SP_SCLK SDIO SCLK CSB SPI_VDDIO AVDD 44 CLK+ VREF VIN+ VIN- CML Description Exposed Pad. The exposed pad is the only ground connection for the chip. The pad must be connected to PCB AGND. Do Not Connect. Do not connect to this pin. PD0 Data Output. PD1 Data Output. PD2 Data Output. PD3 Data Output. 1.9 V Digital Output Supply. Digital Output Ground. PD4 Data Output. PD5 Data Output. PD6 Data Output. PD7 Data Output. PD8 Data Output. PD9 Data Output. PD10 Data Output. PD11 Data Output (MSB). SPORT Output. SPORT Frame Sync Input (Slave Mode)/Output (Master Mode). SPORT Clock Input (Slave Mode)/Output (Master Mode). Serial Port Interface (SPI) Data Input/Output (Serial Port Mode). Serial Port Interface Clock (Serial Port Mode). Serial Port Chip Select (Active Low). 1.9 V or 3.3 V SPI I/O Supply. 1.9 V Analog Supply. Voltage Reference Input/Output. Nominally 0.75 V. Analog Input--True. Analog Input--Complement. Common-Mode Output. Enabled through the SPI, this pin provides a reference for the optimized internal bias voltage for VIN+ and VIN-. Clock Input--True. Rev. 0 | Page 13 of 28 AD6641 Pin No. 45 49 50 51 52 53 55 56 Mnemonic CLK- FILL+ FILL- FULL EMPTY DUMP PCLK- PCLK+ Description Clock Input--Complement. FIFO Fill Input (LVDS)--True. FIFO Fill Input (LVDS)--Complement. FIFO Full Output Indicator. FIFO Empty Output Indicator. FIFO Readback Input. Data Clock Output--Complement. Data Clock Output--True. Rev. 0 | Page 14 of 28 AD6641 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 1.9 V, DRVDD = 1.9 V, rated sample rate, TA = 25C, 1.5 V p-p differential input, AIN = -1 dBFS, unless otherwise noted. 0 0 500MSPS 30.4MHz @ -1.0dBFS SNR: 64.9dB ENOB: 10.7 BITS SFDR: 87dBc -40 -60 -80 -60 -80 -100 0 20 40 60 80 100 120 140 160 180 200 220 240 FREQUENCY (MHz) -120 09813-010 -120 0 20 40 60 80 100 120 140 160 180 200 220 240 FREQUENCY (MHz) Figure 10. 16k Point Single-Tone FFT; 500 MSPS, 30.4 MHz Figure 13. 16k Point Single-Tone FFT; 491.52 MSPS, 368.0 MHz 0 0 500MSPS 100.4MHz @ -1.0dBFS SNR: 64.9dB ENOB: 10.6 BITS SFDR: 86dBc 491.52MSPS 450.1MHz @ -1.0dBFS SNR: 63.3dB ENOB: 10.4 BITS SFDR: 76dBc -20 AMPLITUDE (dBFS) -20 -40 -60 -80 -100 -40 -60 -80 0 20 40 60 80 100 120 140 160 180 200 220 240 FREQUENCY (MHz) -120 09813-011 -120 0 40 60 80 100 120 140 160 180 200 220 240 FREQUENCY (MHz) Figure 11. 16k Point Single-Tone FFT; 500 MSPS, 100.4 MHz Figure 14. 16k Point Single-Tone FFT; 491.52 MSPS, 450.1 MHz 95 0 500MSPS 140.4MHz @ -1.0dBFS SNR: 64.7dB ENOB: 10.6 BITS SFDR: 84dBc -20 20 09813-014 -100 SFDR (dBc), -40C 90 SFDR (dBc), +25C 85 SNR/SFDR (MHz) -40 -60 -80 80 75 SNR (dBFS), -40C 70 SFDR (dBc), +85C 65 60 SNR (dBFS), +85C SNR (dBFS), +25C -100 55 0 20 40 60 80 100 120 140 160 180 200 220 240 FREQUENCY (MHz) Figure 12. 16k Point Single-Tone FFT; 500 MSPS, 140.4 MHz 50 09813-012 -120 0 100 200 300 400 ANALOG INPUT FREQUENCY (MHz) 500 09813-015 AMPLITUDE (dBFS) -40 09813-013 -100 AMPLITUDE (dBFS) 491.52MSPS 368.0MHz @ -1.0dBFS SNR: 63.8dB ENOB: 10.5 BITS SFDR: 77dBc -20 AMPLITUDE (dBFS) AMPLITUDE (dBFS) -20 Figure 15. Single-Tone SNR/SFDR vs. Input Frequency (fIN) and Temperature; 500 MSPS Rev. 0 | Page 15 of 28 AD6641 95 0.5 0.4 90 SFDR (dBc) 0.3 0.2 75 70 SNR (dBFS) 65 55 50 250 300 350 400 450 SAMPLE RATE (MSPS) 0 -0.1 -0.2 SNRFS @ 30.3MHz, 1.8V SNRFS @ 30.3MHz, 1.9V SNRFS @ 100.3MHz, 1.8V SNRFS @ 100.3MHz, 1.9V 60 0.1 -0.3 -0.4 500 550 -0.5 -1 1023 4095 2.5 100 1.24 LSB rms 90 SFDR (dBFS) 2.0 80 NUMBER OF HITS (M) SNR (dBFS) 60 50 SFDR (dBc) SNRFS, 1.9V SNR, 1.9V SFDR, 1.9V SFDRFS, 1.9V SNRFS, 1.8V SNR, 1.8V SFDR, 1.8V SFDRFS, 1.8V 30 20 SNR (dB) 10 0 -90 -80 -70 -60 -50 -40 -30 -20 -10 1.0 0.5 0 AMPLITUDE (dB) 0 09813-117 40 1.5 N-3 N-2 N-1 N N+1 BINS N+2 N+3 MORE 09813-020 70 Figure 20. Grounded Input Histogram; 500 MSPS Figure 17. SNR/SFDR vs. Input Amplitude; 500 MSPS,140.3 MHz 1.0 491.52MSPS fIN1: 121.3MHz @ -7dBFS fIN2: 124.7MHz @ -7dBFS SFDR: 85dBc 0 0.8 -15 0.6 AMPLITUDE (dBFS) 0.4 0.2 0 -0.2 -0.4 -30 -45 -60 -75 -90 -0.6 -105 -0.8 -1 1023 2047 OUTPUT CODE 3071 4095 25 50 75 100 125 150 175 200 225 FREQUENCY (MHz) Figure 21. 16k Point Single-Tone FFT; 491.52 MSPS, fIN1 = 121.3 MHz, fIN2 = 124.7 MHz Figure 18. INL; 500 MSPS Rev. 0 | Page 16 of 28 09813-021 -120 -1.0 09813-018 INL (LSB) 3071 Figure 19. DNL; 500 MSPS Figure 16. SNR/SFDR vs. Sample Rate and Supply SNR/SFDR (dB) 2047 OUTPUT CODE 09813-019 80 DNL (LSB) SFDR @ 30.3MHz, 1.8V SFDR @ 30.3MHz, 1.9V SFDR @ 100.3MHz, 1.8V SFDR @ 100.3MHz, 1.9V 09813-116 SNR/SFDR (dB) 85 AD6641 120 90 IMD3 (dBFS) 85 100 SFDR (dBc) 80 60 SFDR, 1.9V SFDRFS, 1.9V IMD3FS, 1.9V SFDR, 1.8V SFDRFS, 1.8V IMD3FS, 1.8V 20 -80 -70 -60 -50 -40 -30 AMPLITUDE (dBFS) -20 -10 SNR (dBFS) 65 60 55 0 50 1.75 1.80 1.85 1.90 1.95 Figure 22. Two-Tone SFDR vs. Input Amplitude; 500 MSPS, 119.2 MHz, 122.5 MHz Figure 24. SNR/SFDR vs. Power Supply 800 400 120 700 350 IMD3 (dBFS) 100 TOTAL POWER 600 300 60 SFDR, 1.9V SFDRFS, 1.9V IMD3FS, 1.9V SFDR, 1.8V SFDRFS, 1.8V IMD3FS, 1.8V SFDR (dBc) 20 0 -90 -80 -70 -60 -50 -40 -30 AMPLITUDE (dBFS) -20 -10 IAVDD 250 500 200 400 150 300 200 100 IDRVDD 50 0 09813-023 SFDR (dB) CURRENT (mA) SFDR (dBFS) 80 40 2.00 POWER SUPPLY (V) Figure 23. Two-Tone SFDR vs. Input Amplitude; 500 MSPS, 139.3 MHz, 141.3 MHz 0 250 300 350 100 400 450 500 SAMPLE RATE (MSPS) Figure 25. Current and Power vs. Sample Rate Rev. 0 | Page 17 of 28 POWER (mW) 0 -90 70 09813-024 SFDR (dBc) 75 0 550 09813-025 40 09813-022 SFDR (dB) SNR/SFDR (dB) SFDR (dBFS) 80 AD6641 EQUIVALENT CIRCUITS VBOOST AVDD CML AVDD DC VIN+ DRVDD 500 AVDD AIN+ V- V+ SPI CONTROLLED 500 OUTPUT+ OUTPUT- V+ V- 09813-110 AIN- 09813-016 VIN- Figure 26. DC Equivalent Analog Input Circuit Figure 30. LVDS Outputs (PDOR, PD[5:0], PCLK) DRVDD DVDD VIN+ 350 SCLK 1k 30k VIN- 09813-129 09813-017 1.3pF Figure 31. Equivalent SCLK Input Circuit Figure 27. AC Equivalent Analog Input Circuit AVDD DRVDD AVDD AVDD DRVDD 0.9V CLK+ OR FILL+ 15k CLK- OR FILL- 15k 30k DRVDD 350 09813-130 09813-127 CSB Figure 32. Equivalent CSB Input Circuit Figure 28. Equivalent CLK and FILL Input Circuit DRVDD DRVDD DRVDD 30k 350 CTRL Figure 29. Equivalent PD[11:0], FULL, EMPTY, PCLK, and SP_SDO Output Circuit Figure 33. Equivalent SDIO Circuit Rev. 0 | Page 18 of 28 09813-131 DRGND 09813-128 SDIO AD6641 AVDD 20k (00) DRVDD (01) VREF 350 30k MASTER/SLAVE CTRL Figure 35. Equivalent VREF Circuit Figure 34. Equivalent SP_SDFS and SP_SCLK Circuit Rev. 0 | Page 19 of 28 09813-133 NOT USED SPI CTRL VREF SELECT 00: INTERNAL VREF 01: IMORT VREF 10: EXPORT VREF 11: NOT USED 09813-132 SP_SDFS/ SP_SCLK (10) (11) AD6641 SPI REGISTER MAP Table 10. Memory Map Register Addr. (Hex) Parameter Name Chip Configuration Registers 0x00 CHIP_PORT_CONFIG 0x01 CHIP_ID 0x02 CHIP_GRADE Bit 7 (MSB) 0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) LSB first Soft reset 1 1 Soft reset LSB first 0 8-bit chip ID, Bits[7:0] = 0xA0 0 0 Speed grade: 10 = 500 MSPS Transfer Register 0xFF DEVICE_UPDATE ADC Functions 0x08 Modes X1 0 0 0 0 0x0D TEST_IO (For user-defined mode only, set Bits[3:0] = 1000) 00 = Pattern 1 only 01 = toggle Pattern 1/ Pattern 2 10 = toggle Pattern 1/0000 11 = toggle Pattern 1/ Pattern 2/0000 Reset PN23 gen: 1 = on 0 = off (default) Reset PN9 gen: 1 = on 0 = off (default) 0x14 OUTPUT_MODE 0 0 Output disable: 0= enable (default) 1= disable 0 Default Notes/ Comments 0x18 The nibbles should be mirrored by the user so that LSB or MSB first mode registers correctly, regardless of shift mode. Default is unique chip ID, different for each device. This is a read-only register. Child ID used to differentiate graded devices. Read only X1 Read only SW transfer 0x00 Synchronously transfers data from the master shift register to the slave. Internal power-down mode: 000 = normal (power-up, default) 001 = full power-down 010 = standby 011 = reserved Output test mode: 0000 = off (default) 0001 = midscale short 0010 = +FS short 0011 = -FS short 0100 = checkerboard output 0101 = PN23 sequence 0110 = PN9 0111 = one/zero word toggle 1000 = user defined 1001 = unused 1010 = unused 1011 = unused 1100 = unused (format determined by OUTPUT_MODE) Data format select: Output 0= 00 = offset binary invert: CMOS: (default) 1 = on 1= 01 = twos 0 = off LVDS complement (default) (default) 10 = Gray code 11 = reserved 0x00 Determines various generic modes of chip operation. When set, the test data is placed on the output pins in place of normal data. Set pattern values: Pattern 1: Reg 0x19, Reg 0x1A Pattern 2: Reg 0x1B Reg 0x1C. [7:1] = 0000000 0 Rev. 0 | Page 20 of 28 X1 Default Value (Hex) X1 X X 0x00 0x08 AD6641 Parameter Name OUTPUT_ADJUST 0x16 OUTPUT_PHASE 0x17 OUTPUT_DELAY 0x18 Input range 0x19 USER_PATT1_LSB [7:0] 0 0x1A USER_PATT1_MSB [7:0] 0 0x1B USER_PATT2_LSB [7:0] 0 0x1C USER_PATT2_MSB [7:0] 0 Digital Controls 0x101 Fill control register 0x102 FIFO Config 0x104 Fill count Bit 7 (MSB) Output clock polarity: 1= inverted 0= normal (default) 0 Bit 6 Bit 5 [7:4] = 0000 Bit 3 LVDS course adjust: 0= 3.5 mA (default) 1= 2.0 mA Bit 2 [6:0] = 0000000 0 VREF select: 00 = internal VREF (20 k pull-down) 01 = import VREF (0.59 V to 0.80 V on VREF pin) 10 = export VREF 11= not used Reserved Bit 4 Bit 0 Bit 1 (LSB) LVDS fine adjust: 001 = 3.50 mA 010 = 3.25 mA 011 = 3.00 mA 100 = 2.75 mA 101 = 2.50 mA 110 = 2.25 mA 111 = 2.00 mA Default Value (Hex) 0x00 Addr. (Hex) 0x15 0 0 Reserved Fill input pin disable [7:4] = reserved LIFO mode 0x03 0 Output clock delay: 0000 = 0 0001 = -1/10 0010 = -2/10 0011 = -3/10 0100 = reserved 0101 = +5/10 0110 = +4/10 0111 = +3/10 1000 = +2/10 1001 = +1/10 Input voltage range setting (V): 11100 = 1.60 11101 = 1.58 11110 = 1.55 11111 = 1.52 00000 = 1.50 00001 = 1.47 00010 = 1.44 00011 = 1.42 00100 = 1.39 00101 = 1.36 00110 = 1.34 00111 = 1.31 01000 = 1.28 01001 = 1.26 01010 = 1.23 01011= 1.20 01100 = 1.18 0 FIFO fill mode: 00 = single 01 = continuous 1x = reserved Dump Fill reset reset [7:0] Rev. 0 | Page 21 of 28 Default Notes/ Comments Shown as fractional value of sampling clock period that is subtracted or added to initial tSKEW, see Figure 3). 0 Reserved Standby after fill 0 Dump Fill 0 0x7F User Defined Pattern 1 LSB. User Defined Pattern 1 MSB. User Defined Pattern 2 LSB. User Defined Pattern 2 MSB. Number of words to use for fill or dump. AD6641 Addr. (Hex) 0x105 Parameter Name Settle Count0 0x106 Settle Count1 0x107 Dump control [7:3] = reserved 0= slave 1= master 0x10A FIFO status [7:3] = reserved Overrange 0x10B FIFO Dump Data0 0x10C FIFO Dump Data1 0x10F Read Offset Data0 0x110 0x111 Read Offset Data1 PPORT control 0x112 SPORT control [7:5] = reserved 0x13A FIFO test BIST [7:5] = reserved 1 Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 [7:0] Bit 2 Bit 1 Bit 0 (LSB) [7:0] 0 Readback mode: 00 = off 01 = parallel 10 = SPORT 11 = reserved Empty Full [7:0] = LSBs [7:4] = reserved [3:0] = MSBs [5:0] = MSBs Divide ratio = 2 x (bit word): 00100 = divide by 8 (default) ... 01111 = divide by 30 1xxxx = divide by 32 Divide ratio= 2 x (bit word): 00100 = divide by 8 (default) ... 01111 = divide by 30 1xxxx = divide by 32 Sets the BIST mode for the FIFO: 1xxx = reserved 0111 = reserved 0110 = 12'hFFF (-1 LSB) 0101 = 12'h001 (+1 LSB) 0100 = PN data 0011 = checkerboard (12'hAAA, 12'h555, 12'hAAA, ... ) 0010 = checkerboard (12'h555, 12'hAAA, 12'h555, ... ) 0001 = decrementing ramp 0000 = incrementing ramp X = don't care. Rev. 0 | Page 22 of 28 0 0 0 0 0x04 0x04 FIFO BIST enable Default Notes/ Comments LSBs settling time given to ADC before initiating fill. MSBs settling time given to ADC before initiating fill. Customer drives SP_SCLK, SP_SDFS in slave mode. 0 0 [7:0] = LSBs [7:6] = reserved [7:5] = reserved Default Value (Hex) 0 0 LSBs readback data. MSBs upper four bits readback data. LSBs offset to RAM, allowing subsegments of data capture to be read. MSB's offset. CMOS parallel port divide rate. Serial port divide rate. AD6641 THEORY OF OPERATION The on-chip FIFO allows small snapshots of time to be captured via the ADC and read back at a lower rate. This reduces the constraints of signal processing by transferring the captured data at an arbitrary time and at a much lower sample rate. FIFO OPERATION The capture of the data can be signaled through writes to the SPI port by pulsing the FILL pins. The transaction diagram shown in Figure 36 illustrates the loading of the FIFO. At Event 1, the FIFO is instructed to fill either by asserting the FILL pins or via a write to the SPI bits. FILL pin operation can be delayed by a programmable fill hold-off counter so that the FIFO data can be surrounding a fill event. The FIFO then loads itself with data. The number of samples of data is determined by the SPI fill count register (0x104). This is an 8bit register with values from 0 to 255. The number of samples placed in the FIFO is determined by the following equation: Number of Samples = (FILL_CNT + 1) x 64 After the FIFO has begun filling at Event 2, the AD6641 asserts a full flag to indicate that the FIFO has finished capturing data and enters a wait state in which the device waits to receive the dump instruction from the DUMP pin or the SPI. After the data has been shifted (Event 4), the FIFO goes into the idle state and waits for another fill command. During the idle state, the ADC can optionally be placed into standby mode to save power. If the ADC powers down in the idle state, initiating a fill operation (Event 1) powers up the ADC. In this mode, the ADC waits for settle count cycles (0x105, 0x106) before capturing the data. Settle count is programmable from the SPI port and 1 2 allows the analog circuitry to stabilize before taking data. An intelligent trade-off between speed of acquisition and accuracy can be made by using this register. The data can be read back through any of the three output interfaces at a low data rate, which further saves power. If the SPI or SPORT is used to read back the data, the interface can require as few as three pins. A full flag and an empty flag are provided to signal the state of the FIFO. The FIFO status register (0x10A) in the SPI also allows this to be monitored via software. Single Capture Mode The FIFO can be placed into single capture mode by writing the FIFO fill mode bits in the fill control register (0x101[3:2]) to 00. In the single capture mode, the user initiates a capture either by driving the FILL pins high or by initiating a fill command through the SPI port by writing the standby after fill bit (0x101[0]). This powers up the ADC (if needed) after a programmable amount of time as determined by the SPI settle count registers (0x105, 0x106). If Bit 0 of the 0x101 register in the SPI is set, the ADC returns to standby mode after the capture is complete. Fill Pin Timing A fill of the FIFO can be initiated by asserting the differential FILL pins. When a pulse is detected on the FILL pins, the FIFO is filled. Dump Pin Timing A readback of the FIFO can be initiated by asserting the DUMP pin. When a logic high is detected on the DUMP pin, the FIFO data is available through the chosen interface. 3 4 STATE IDLE STATE FILLING FIFO WITH DATA WAIT FOR DUMP (OPTIONAL) IDLE STATE START SP_SCLK AND SP_SDFS SHIFT DATA Figure 36. On-Chip FIFO Transaction Timing Assuming Serial Port CLK+ 09813-035 CLK- FILL+, FILL- Figure 37. FIFO Fill Timing CLK+ 09813-036 CLK- DUMP Figure 38. FIFO DUMP Timing Rev. 0 | Page 23 of 28 09813-034 EVENTS AD6641 SPORT Master Mode (Single Capture) Dump Signal (4)--Transition to High Details of the transaction diagram for serial master mode are shown in Figure 39 for single capture mode with the SDO output. Clock cycles are approximate because the fill and dump signals can be driven asynchronously. In this example, SCLK is derived from the master clock with a divide by 8 programmed from the SPI. The dump signal initiates reading data from the FIFO. Dump is enabled with a high level and should be initiated only after the full signal goes high. The dump signal should be held high until all data has been read out of the FIFO. SCLK Signal (5) The SCLK (serial clock) signal is configured as an output from the device when in the master mode of operation. SCLK begins cycling five ADC clock cycles after the dump signal is sampled high and continues cycling up until one additional cycle after the empty signal goes high. SCLK then remains low until the next dump operation. Fill Pulse (1) The FIFO captures data after a fill signal (high level) is detected on the rising edge of the sampling clock. In synchronous operation, a valid high level is accomplished by adhering to the setup and hold times specified. For nonsynchronous control, the fill signal can be widened to accommodate two or more clock cycles to guarantee capture of a high level. Fill count (0x104) is reset on the rising edge of the clock and is incremented on subsequent clock cycles only after the fill signal returns low. A new fill signal at any point during the capture resets the counter and begins filling the FIFO. SDFS Signal (6) The SDFS (serial data frame sync) signal is configured as an output from the device when in the master mode of operation. Frame synchronization begins 15 ADC clock cycles after the dump signal is sampled. Empty Signal (2) Dump Signal (7)--Transition to Low After the FIFO state machine has begun loading data, the empty signal goes low 24 clock cycles after the fill signal was last sampled high. A dump signal transition to low is applied after data has been read out of the FIFO. Full Signal (3) The empty signal transitions to high after data has been output from the FIFO based on the clock cycle count of (FILL_CNT + 1) x 64. Empty Signal (8)--Transition to High The full signal indicates when the FIFO has been filled and is driven high when the number of samples specified has been captured in the FIFO, where The transition occurs 76 ADC clock cycles after the last LSB(s) of data have been output on the serial port. Number of Samples = (FILL_CNT + 1) x 64 The time at which the full signal goes high is based on (FILL_CNT + 1) x 64 + 13 clock cycles after the fill signal was last sampled high. 1 FILL 8 2 EMPTY 3 FULL 4 7 DUMP 5 SCLK 6 09813-037 SDFS SDO Figure 39. SPORT Master Mode Transaction Diagram Rev. 0 | Page 24 of 28 AD6641 Parallel Master Mode (Single Capture) Dump Signal (4)--Transition to High Details of the transaction diagram for parallel master mode are shown in Figure 40 with the PD[11:0] output word. Clock cycles are approximate because the fill and dump signals can be driven asynchronously. In this example, PCLK is derived from the master clock with a divide by 8 programmed from the SPI. The dump signal initiates reading data from the FIFO. Dump is enabled with a high level and should be initiated only after the full signal goes high. The dump signal should be held high until all data has been read out of the FIFO. PCLK Signal (5) Fill Pulse (1) The PCLK (parallel clock) signal is configured as an output from the device. PCLK begins cycling 71 ADC clock cycles after the dump signal is sampled high. PCLK goes low after the last data is read out of the FIFO and remains low until the next dump operation. The FIFO captures data after a fill signal (high level) is detected on the rising edge of the sampling clock. In synchronous operation, a valid high level is accomplished by adhering to the setup and hold times specified. For nonsynchronous control, the fill signal can be widened to accommodate two or more clock cycles to guarantee capture of a high level. Fill count (0x104) is reset on the rising edge of the clock and is incremented on subsequent clock cycles only after the fill signal returns low. A new fill signal at any point during the capture resets the counter and begins filling the FIFO. The PD (parallel data) output provides 12 data bits (PD[11:0]) at a maximum rate of 1/8th of the sampling clock. Data begins after two PCLK cycles (assuming the dump signal has been sampled). Empty Signal (2) Dump Signal (7)--Transition to Low After the FIFO state machine has begun loading data, the empty signal goes low 24 clock cycles after the fill signal was last sampled high. A dump signal transition to low is applied after data has been read out of the FIFO. Full Signal (3) The empty signal transitions to high after data has been output from the FIFO based on the clock cycle count of (FILL_CNT + 1) x 64. The transition occurs nine clock cycles after the last PCLK rising edge. PD[11:0] Signal (6) Empty Signal (8)--Transition to High The full signal indicates when the FIFO has been filled and is driven high when the number of samples specified has been captured in the FIFO, where Continuous Capture Mode Number of Samples = (FILL_CNT + 1) x 64 The FIFO can be placed into continuous capture mode by writing the FIFO fill mode bits in the fill control register (0x101[3:2]) to 01. In the continuous capture mode, data is loaded continuously into the FIFO and the FILL pins pulsing high is used to stop the operation. This allows the history of the samples that preceded an event to be captured. The time at which the full signal goes high is based on (FILL_CNT + 1) x 64 + 13 clock cycles after the fill signal was last sampled high. 1 FILL 2 8 EMPTY 3 FULL 4 7 DUMP 5 PCLK+ PCLK- D0 D8 Figure 40. Parallel Mode Transaction Diagram Rev. 0 | Page 25 of 28 D16 09813-038 6 PD[11:0] AD6641 at a 500 MSPS input sample rate. See Figure 3 for the parallel CMOS mode output interface timing diagram. FIFO OUTPUT INTERFACES The FIFO data is available through one of three interfaces. The data can be output on the serial data port (SPORT), the SPI port, or a 12-bit CMOS interface. The data port chosen must be selected from the SPI port before the data is read from the FIFO. Only one interface can be chosen at a time. The SPORT and SPI interfaces are powered via the SPI_VDDIO pin and can support either 1.9 V or 3.3 V logic levels. LVDS Output Interface The AD6641 differential outputs conform to the ANSI-644 LVDS standard on default power-up. This can be changed to a low power, reduced signal option similar to the IEEE 1596.3 standard using the SPI. This LVDS standard can further reduce the overall power dissipation of the device, which reduces the power by ~39 mW. The LVDS driver current is derived on chip and sets the output current at each output equal to a nominal 3.5 mA. A 100 differential termination resistor placed at the LVDS receiver inputs results in a nominal 350 mV differential or 700 mV p-p swing at the receiver. SPORT Interface The SPORT consists of a clock (SP_SCLK) and frame sync (SP_SDFS) signal. The SP_SCLK and SP_SDFS signals are output from the AD6641 when the SPORT is configured as a bus master and are input to the device when it is configured as a slave port. The AD6641 LVDS outputs facilitate interfacing with LVDS receivers in custom ASICs and FPGAs that have LVDS capability for superior switching performance in noisy environments. Single point-to-point net topologies are recommended with a 100 termination resistor placed as close to the receiver as possible. No far-end receiver termination and poor differential trace routing may result in timing errors. It is recommended that the trace length be no longer than 24 inches and that the differential output traces be kept close together and at equal lengths. Serial Data Frame (Serial Bus Master) The serial data transfer is initiated with SP_SDFS. In master mode, the internal serial controller initiates SP_SDFS after the dump input goes high requesting the data. SP_SDFS is valid for one complete clock cycle prior to the data shift. On the next clock cycle, the AD6641 begins shifting out the data stream. CMOS Output Interface The data stored in the FIFO can also be accessed via a 12-bit parallel CMOS interface. The maximum output throughput supported by the AD6641 is in the 12-bit CMOS mode and is internally limited to 1/8th of the maximum input sample rate. Therefore, the output maximum output data rate is 62.5 MHz 0 4 8 The data on the LVDS output port is interleaved in a MSB/LSB format. PCLK is generated by dividing the ADC sample clock by the programmed decimation rate (8 to 32, even divides). The maximum rate of PCLK is limited to 62.5 MHz. 12 16 20 24 28 SP_SCLK SP_SDO D1 D2 D3 09813-039 SP_SDFS Figure 41. Data Output in Serial Bus Master Mode PCLK+ PCLK- X D0[5:0] D0[11:6] LSB/MSB D0 SAMPLE D8[5:0] D8[11:6] D16[5:0] D16[11:6] D24[5:0] LSB/MSB D8 SAMPLE Figure 42. DDR LVDS Output MSB/LSB Interleaving with Decimate by 8 Rev. 0 | Page 26 of 28 D24[11:6] 09813-040 PD[5:0] AD6641 ANALOG INPUT AND VOLTAGE REFERENCE Table 11. Serial Port Interface Pins The analog input to the AD6641 is a differential buffer. For best dynamic performance, match the source impedances driving VIN+ and VIN- such that common-mode settling errors are symmetrical. The analog input is optimized to provide superior wideband performance and requires that the analog inputs be driven differentially. SNR and SINAD performance degrades significantly if the analog input is driven with a singleended signal. Pin SCLK SDIO CSB The falling edge of the CSB pin, in conjunction with the rising edge of the SCLK pin, determines the start of the framing. An example of the serial timing can be found in Figure 43 (for symbol definitions, see Table 5). A wideband transformer, such as Mini-Circuits(R) ADT1-1WT, can provide the differential analog inputs for applications that require a single-ended-to-differential conversion. Both analog inputs are self-biased by an on-chip reference to a nominal 1.7 V. CSB can be held low indefinitely, which permanently enables the device; this is called streaming. CSB can stall high between bytes to allow additional external timing. When CSB is tied high, SPI functions are placed in high impedance mode. An internal differential voltage reference creates positive and negative reference voltages that define the 1.5 V p-p fixed span of the ADC core. This internal voltage reference can be adjusted by means of an SPI control. During an instruction phase, a 16-bit instruction is transmitted. The first bit of the first byte in a serial data transfer frame indicates whether a read command or a write command is issued. Data follows the instruction phase, and its length is determined by the W0 and W1 bits. All data is composed of 8-bit words. VREF The AD6641 VREF pin (Pin 31) allows the user to monitor the on-board voltage reference or provide an external reference (requires configuration through the SPI). The three optional settings are internal VREF (pin is connected to 20 k to ground), export VREF, and import VREF. Do not attach a bypass capacitor to this pin. VREF is internally compensated and additional loading may impact performance. The instruction phase determines whether the serial frame is a read or write operation, allowing the serial port to be used both to program the chip and to read the contents of the on-chip memory. If the instruction is a read operation, the serial data input/output (SDIO) pin changes direction from an input to an output at the appropriate point in the serial frame. CONFIGURATION USING THE SPI Three pins define the SPI of the AD6641: SCLK, SDIO, and CSB (see Table 11). SCLK (a serial clock) is used to synchronize the read and write data presented from and to the AD6641. SDIO (serial data input/output) is a bidirectional pin that allows data to be sent to and read from the internal memory map registers. CSB (chip select) is an active low control that enables or disables the read and write cycles. tDS tS tHIGH Function Serial clock. Serial shift clock input. SCLK is used to synchronize serial interface reads and writes. Serial data input/output. Bidirectional pin that serves as an input or an output, depending on the instruction being sent and the relative position in the timing frame. Chip select (active low). This control gates the read and write cycles. Data can be sent in MSB first mode or in LSB first mode. MSB first is the default mode on power-up and can be changed via the SPI port configuration register. For more information about this and other features, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. tH tCLK tDH tLOW CSB SCLK DON'T CARE DON'T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 DON'T CARE 09813 -073 SDIO DON'T CARE Figure 43. Serial Port Interface Timing Diagram Rev. 0 | Page 27 of 28 AD6641 OUTLINE DIMENSIONS 8.00 BSC SQ 0.60 MAX 0.50 0.40 0.30 SEATING PLANE 29 28 0.50 BSC 15 14 0.25 MIN 6.50 REF 0.80 MAX 0.65 TYP 12 MAX 6.25 6.10 SQ 5.95 EXPOSED PAD (BOTTOM VIEW) 7.75 BSC SQ 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VLLD-2 030509-A TOP VIEW PIN 1 INDICATOR 56 1 43 42 PIN 1 INDICATOR 1.00 0.85 0.80 0.30 0.23 0.18 0.60 MAX Figure 44. 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 8 mm x 8 mm Body, Very Thin Quad (CP-56-1) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD6641BCPZ-500 AD6641BCPZRL7-500 AD6641-500EBZ 1 Temperature Range -40C to +85C -40C to +85C Package Description 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 7" Tape and Reel Evaluation Board Z = RoHS Compliant Part. (c)2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09813-0-4/11(0) Rev. 0 | Page 28 of 28 Package Option CP-56-1 CP-56-1