ON Semiconductor MC1494 Linear Four-Quadrant Multiplier The MC1494 is designed for use where the output voltage is a linear product of two input voltages. Typical applications include: multiply, divide, square root, mean square, phase detector, frequency doubler, balanced modulator/ demodulator, electronic gain control. The MC1494 is a variable transconductance multiplier with internal level-shift circuitry and voltage regulator. Scale factor, input offsets and output offset are completely adjustable with the use of four external potentiometers. Two complementary regulated voltages are provided to simplify offset adjustment and improve power supply rejection. * Operates with 15 V Supplies * Excellent Linearity: Maximum Error (X or Y) 1.0 % * Wide Input Voltage Range: 10 V * Adjustable Scale Factor, K (0.1 nominal) * Single-Ended Output Referenced to Ground * Simplified Offset Adjust Circuitry * Frequency Response (3.0 dB Small-Signal): 1.0 MHz * Power Supply Sensitivity: 30 mV/V typical LINEAR FOUR-QUADRANT MULTIPLIER INTEGRATED CIRCUIT SEMICONDUCTOR TECHNICAL DATA 16 1 P SUFFIX PLASTIC PACKAGE CASE 648C ORDERING INFORMATION 10 X Y 6.0 KXY 4.0 1 10 k= 2.0 0 -2.0 -4.0 -6.0 -8.0 -10 -10 -8.0 -6.0 -4.0 -2.0 0 2.0 4.0 6.0 8.0 MC1494P TA = 0 to + 70C Plastic DIP 0.50 0.25 -25 0 25 50 75 100 125 TA, AMBIENT TEMPERATURE (C) Figure 1. Multiplier Transfer Characteristic May, 2001 - Rev. 1 Package 0.75 0 -50 10 VX, INPUT VOLTAGE (V) Semiconductor Components Industries, LLC, 2001 Tested Operating Temperature Range 1.00 + E RX or E RY, LINEARITY ERROR (%) VO , OUTPUT VOLTAGE (V) 8.0 Device Figure 2. Linearity Error versus Temperature 1 Publication Order Number: MC1494/D MC1494 MAXIMUM RATINGS (TA = + 25C, unless otherwise noted.) Symbol Rating Value Unit Power Supply Voltages V 18 Vdc Differential Input Signal V9-V6 V10-V13 |6 + I1RY|<30 |6 + I1RX|<30 Vdc Common Mode Input Voltage VCMY = V9 = V6 VCMX = V10 = V13 VCMY VCMX 11.5 11.5 Power Dissipation (Package Limitation) TA = + 25C Derate above TA = + 25C PD 1/JA 1.25 20 W mW/C Operating Temperature Range TA 0 to +70 C Storage Temperature Range Tstg - 65 to +150 C Vdc ELECTRICAL CHARACTERISTICS (V = 15 V, TA = + 25C, R1 = 16 k, RX = 30 k, RY = 62 k, RL = 47 k, unless otherwise noted.) Characteristics Figure Symbol 3 ERX or ERY Linearity Output error in percent of full scale -10 V <VX < +10 V (VY = 10 V) -10 V <VY < +10 V (VX = 10 V) TA = +25C TA = Thigh or Tlow (Note 1) Input Voltage Range (VX = VY = Vin) Resistance (X or Y Input) Offset Voltage Bias Current Offset Current Max Unit % - - 0.5 - 1.0 1.3 Vin Rin |Viox| |Vioy| Ib |Iio| 10 - - - - - - 300 0.2 0.8 1.0 50 - - 2.5 2.5 2.5 400 Vpk M V VO RO |VOO| |IOO| 10 - - - - 850 1.2 25 - - 2.5 52 Vpk k V A |TCVOO| |TCIOO| |TCViox| |TCVioy| |TCK| |TCE| - - - - - - 1.3 27 0.3 1.5 0.07 0.09 - - - - - - mV/C nA/C mV/C BW3dB (X) BW3dB (Y) PBW f f - - - - - 0.8 1.0 440 240 30 - - - - - MHz CMV ACM 10.5 - - - 65 - - Vpk dB Id+ Id- PD S+ S- - - - - - 6.0 6.5 185 13 30 12 12 350 100 200 mAdc VR+, VR- TCVR SR+, SR- 3.5 - - 4.3 0.03 0.6 5.0 - - Vdc mV/C mV/V (X Input) (Note 1) (Y Input) (Note 1) (X or Y Input) (X or Y Input) 5, 6 Temperature Stability (Drift) TA = Thigh to Tlow - Voltage Current X Input Offset (Y = 0) Y Input Offset (X = 0) Scale Factor Total DC Accuracy Drift (X = 10, Y = 10) Dynamic Response Small Signal (3.0 dB) A nA %/C 7 Power Bandwidth (47 k) 3 Relative Phase Shift 1% Absolute Error Common Mode Input Swing Gain Typ 4, 5, 6 Output Voltage Swing Capability Impedance Offset Voltage (Note 1) Offset Current (Note 1) Output Offset (X = 0, Y = 0) Min kHz 8 (X or Y) (X or Y) Power Supply Current 9 Quiescent Power Dissipation Sensitivity Regulated Offset Adjust Voltages Positive/Negative Temperature Coefficient (VR+ or VR-) Power Supply Sensitivity (VR+ or VR-) mW mV/V 9 NOTE: 1. Offsets can be adjusted to zero with external potentiomers. THigh = +70C, TLow = 0C http://onsemi.com 2 MC1494 Adjust RL for a null in Eo RL To A E = 20 Vpp VX 10 12 RY = 62 k 7 8 R1 = 16 k 3 1 14 + VY 13 f = 20 Hz 10 V RX = 30 k 11 I15 - + 9 - 6 15 MC1494 + - VR I5 + 4 20 k VR 5 2 f = 20 Hz 22 k 50 k - +15 V 0.1 F A -15 V 0.1 F 1.0 M 10 1.0 M 13 10 VX 11 RX 12 7 RY 9 6 - 8 1 3 0.1 F + 5 2 +15 V 0.1 F -15 V 0.1 F 50 k - MC1456 + VO [ Y= [ ]M ] Rin X = e1X e2X - 2 Rin e1Y M e2Y - 2 10 I13 13 I9 9 I6 6 30 k 62 k RX 12 7 RY 16 k 8 1 3 14 VO + - - - +15 V 0.1 F R 15 MC1494 + 5 + 8.2 k 4 O 47 k -15 V 0.1 F 2 50 k VO off Figure 6. Input Bias Current/Input Offset Current, Output Resistance Figure 5. Offset Voltages, Gain VY I10 11 20 k VX off VX 2 Figure 4. Input Resistance 22 k I5 + 20 k VY off -15 V 0.1 F Eo 14 15 4 5 + RL MC1494 + +15 V 8.2 k ES(peak) I15 - VO 16 k + 13 VY 62 k 47 k 3 14 0.1 F 4 e2Y Figure 3. Linearity 30 k - - Eo(peak) 1 MC1494 + MC1456 Linearity, Error = 8 15 - 6 10 k 16 k 7 RY + 9 1.0 M e1Y 62 k RX 12 11 1.0 M + 10 k 50 k VO MC1456 10 k 20 k e1X 30 k e2X 10 13 9 6 11 30 k 62 k RX 12 7 RY 16 k 8 1 + + 4 5 + 8.2 k 2 CO = 3.0 pF 14 15 MC1494 - 3 10 VO +15 V 0.1 F -15 V 0.1 F 13 9 47 k RL 6 CMVY (20 Hz) 51 Figure 7. Frequency Response 11 30 k 62 k RX 12 7 RY 16 k 8 1 + - - 4 5 + 8.2 k 2 Figure 8. Common Mode http://onsemi.com 3 VO 14 15 MC1494 + 3 +15 V 0.1 F 47 k -15 V 0.1 F MC1494 10 13 9 6 11 30 k 62 k RX 12 7 RY 16 k 16 k 8 1 3 + - - 4 VR- 14 VO +15 V 0.1 F 5 + 8.2 k 16 2 15 MC1494 + 1 5 -15 V 0.1 F 13 MC1494 12 7 62 k -15 V VO 47 k 6 100 Hz VR+ 14 4 47 k VS 2 +15 V 0.1 F 15 3 8.2 k NC 30 k 11 8 10 Vin - +10 V 9 Figure 9. Power Supply Sensitivity 15 Figure 10. Burn-In 15 RL = 1.0 k 10 RL = 10 k 5.0 RELATIVE GAIN (dB) RELATIVE GAIN (dB) 10 RL = 33 k 0 RL = 47 k -5.0 -10 -15 -20 103 VY = 1.0 Vrms, VX = 10 Vdc RX = 30 k, RY = 62 k CO = 6.0 pF 104 0 106 -10 RL Adjusted for K = 1 Vin = 2.0 Vpp 0.3 0.2 0.1 0 2.0 4.0 4.0 8.0 6.0 12 8.0 16 VX = 1.0 Vrms, VY = 10 Vdc RX = 30 k, RY = 62 K CO = 6.0 pF 104 RL = 47 k 105 f, FREQUENCY (Hz) 106 107 Figure 12. Frequency Response of X Input versus Load Resistance ERX or ERY , LINEARITY ERROR (%) ERX or ERY , LINEARITY ERROR (%) Figure 11. Frequency Response of Y Input versus Load Resistance 0.4 RL = 33 k -20 103 107 RL = 10 k -5.0 -15 105 f, FREQUENCY (Hz) RL = 1.0 k 5.0 0.5 0.4 0.3 0.2 10 RX (k) RL Adjusted for K = 1/10 Vin = 20 Vpp 0.6 20 RY (k) 20 30 40 50 RX (k) 40 60 80 100 RY (k) Figure 14. Linearity versus RX or RY with K = 1/10 Figure 13. Linearity versus RX or RY with K = 1 http://onsemi.com 4 MC1494 0.106 1 20 K, SCALE FACTOR VO , OUTPUT VOLTAGE (Vpp) 0.108 2 10 1 2 With MC1456 Buffer Op Amp No Op Amp, RL = 47 k K Factor Adjusted for 1/10 at 25C) 0.104 0.102 0.1 0.098 0.096 0.094 0 100 1.0 k 10 k f, FREQUENCY (Hz) -55 100 k Figure 15. Large Signal Voltage versus Frequency -35 -15 5.0 25 45 65 85 105 TA, AMBIENT TEMPERATURE (C) 125 145 Figure 16. Scale Factor (K) versus Temperature CIRCUIT DESCRIPTION Introduction Therefore, the output is proportional to the product of the two input voltages. The MC1494 is a monolithic, four-quadrant multiplier that operates on the principle of variable transconductance. It features a single-ended current output referenced to ground and provides two complementary regulated voltages for use with the offset adjust circuits to virtually eliminate sensitivity of the offset voltage nulls to changes in supply voltages. As shown in Figure 17, the MC1494 consists of a multiplier proper and associated peripheral circuitry to provide these features. Differential Current Converter This portion of the circuitry converts the differential output current (IA -IB) of the multiplier to a single-ended output current (IO); IO = IA - IB or 2VX VY RXRYI1 The output current can be easily converted to an output voltage by placing a load resistor RL from the output (Pin 14) to ground (Figure 19) or by using an op amp as a current-to-voltage converter (Figure 18). The result in both circuits is that the output voltage is given by: Regulator The regulator biases the entire MC1494 circuit making it essentially independent of supply variation. It also provides two convenient regulated supply voltages which can be used in the offset adjust circuitry. The regulated output voltage at Pin 2 is approximately + 4.3 V, while the regulated voltage at Pin 4 is approximately - 4.3 V. For optimum temperature stability of these regulated voltages, it is recommended that |I2| = |I4| = 1.0 mA (equivalent load of 8.6 k). As will be shown later, there will normally be two 20 k potentiometers and one 50 k potentiometer connected between Pins 2 and 4. The regulator also establishes a constant current reference that controls all of the constant current sources in the MC1494. Note that all current sources are related to current I1 which is determined by R1. For best temperatures performance, R1 should be 16 k so that I1 0.5 mA for all applications. VO = 2RL VX VY RXRYI1 = KVXVY 2RL RXRYI1 where, K (scale factor) = DC OPERATION Selection of External Components For low frequency operation the circuit of Figure 18 is recommended. For this circuit, RX = 30 k, RY = 62 k, R1 = 16 k and, hence, I1 0.5 mA. Therefore, to set the scale factor (K) equal to 1/10, the value of RL can be calculated to be: K= or RL = Multiplier The multiplier section of the MC1494 (center section of Figure 17) is nearly identical to the MC1495 and is discussed in detail in Application Note AN489, Analysis and Basic Operation of the MC1495. The result of this analysis is that the differential output current of the multiplier is given by: IA - IB = I IO = 1 10 = 2RL RXRYI1 RXRYI1 (2) (10) = (30 k) (62 k) (0.5 mA) 20 RL = 46.5 k Thus, a reasonable accuracy in scale factor can be achieved by making RL a fixed 47 k resistor. However, if it is desired that the scale factor be exact, RL can be comprised of a fixed resistor and a potentiometer as shown in Figure 18. 2VX VY RXRYI1 http://onsemi.com 5 MC1494 Block Diagram 15 +V + VR -VR -V 2 +4.3 V 4 14 IA 3 1 Current and Voltage Regulator 9 6 VY -4.3 V Four Quadrant Multiplier + - R1 7 8 + - 11 RY 5 IB IO (IO = IA - IB) Differential Current Converter 10 V 13 X 12 RX +V 15 I1 Constant Current Source Control +9.4 V +4.3 V 8.7 k 2 I1 +8.7 V R1 I1 IA 4 -4.3 V 7.2 k 9 10 VX 13 VY 5 15 I1 I1 3 I1 500 500 5.4 k 7 6 -9.4 V -V +V 14 IB 7.2 k -VR 8 RY 11 I1 12 RX I1 500 3.0 k R1 GND +VR 2 500 7.2 k 500 500 500 2.0 k 2.0 k 10 pF 10 pF 8.7 k 14 1 3 4 7.2 k 9 10 7.2 k VY + VX 6 13 RY 7 10 k 10 k 10 k 10 k 500 500 500 5 Regulator 500 500 500 500 12 RX 11 8 -V IO I1 Complete Circuit Schematic 500 500 8.7 k + VR 1.7 V 2 I1 I1 8.7 k + VR 2 3 Simplified Circuit Schematic 2.4 V 500 500 500 500 Multiplier This device contains 44 active transistors. Figure 17. Internal Schematic (Recommended External Circuitry is Depicted within Dotted Lines) http://onsemi.com 6 Differential Current Converter IO MC1494 +15 V 0.1 F 10 VX 10 pF 510 30 k RX - 510 + 8 R* 62 k RY 1 3 12 9 10 pF 5 + 13 VY 0.1 F RL 15 11 R* +15 V MC1494 + 50 k 22 k P4 R1 16 k 10 pF 14 2 - 6 MC1456 7 6 3 -4 + P1 20 k 4 + 7 2 0.1 F P2 0.1 F 20 k +15 V P3 VO 50 k -15 V VO = -VX VY 10 *R is not necessary if inputs are DC coupled. -10 V VX +10 V -10 V VY +10 V Figure 18. Typical Multiplier Connection It should be pointed out that there is nothing magic about setting the scale factor to 1/10. This is merely a convenient factor to use if the VX and VY input voltages are expected to be large, say 10 V. Obviously with VX = VY = 10 V and a scale factor of unity, the device could not hope to provide a 100 V output, so the scale factor is set to 1/10 and provides an output scaled down by a factor of ten. For many applications it may be desirable to set K = 1/2 or K = 1 or even K = 100. This can be accomplished by adjusting RX, RY and RL appropriately. The selection of RL is arbitrary and can be chosen after resistors RX and RY are found. Note in Figure 18 that RY is 62 k while RX is 30 k. The reason for this is that the "Y" side of the multiplier exhibits a second order nonlinearity whereas the "X" side exhibits a simple nonlinearity. By making the RY resistor approximately twice the value of the RX resistor, the linearity on both the "X" and "Y" sides are made equal. The selection of the RX and RY resistor values is dependent upon the expected amplitude of VX and VY inputs. To maintain a specified linearity, resistors RX and RY should be selected according to the following equations: RX 3 VX (max) in k when VX is in Volts, RY 6 VY (max) in k when VY is in Volts. For example, if the maximum input on the "X" side is 1.0 V, resistor RX can be selected to be 3.0 k. If the maximum input on the "Y" side is also 1.0 V, then resistor RY can be selected to be 6.0 k (6.2 k nominal value). If a scale factor of K = 10 is desired, the load resistor is found to be 47 k. In this example, the multiplier provides a gain of 20 dB. converter. The output current of the multiplier flows through the feedback resistor RL to provide a low impedance output voltage from the op amp. Since the offset current and bias currents of the op amp will cause errors in the output voltage, particularly with temperature, one with very low bias and offset currents is recommended. The MC1456 or MC1741 are excellent choices for this application. Since the MC1494 is capable of operation at much higher frequencies than the op amp, the frequency characteristics of the circuit in Figure 18 will be primarily dependent upon the operational amplifier. Stability The current-to-voltage converter mode is a most demanding application for an operational amplifier. Loop gain is at its maximum and the feedback resistor in conjunction with stray or input capacitance at the multiplier output adds additional phase shift. It may therefore be necessary to add (particularly in the case of internally compensated op amps) a small feedback capacitor to reduce loop gain at the higher frequencies. A value of 10 pF in parallel with RL should be adequate to insure stability over production and temperature variations, etc. An externally compensated op amp might be employed using slightly heavier compensation than that recommended for unity-gain operation. Offset Adjustment The noninverting input of the op amp provides a convenient point to adjust the output offset voltage. By connecting this point to the wiper arm of a potentiometer (P3), the output offset voltage can be adjusted to zero (see Offset and Scale Factor Adjustment Procedure). Operational Amplifier Selection The operational amplifier connection in Figure 18 is a simple but extremely accurate current-to-voltage http://onsemi.com 7 MC1494 Bias Currents The input offset adjustment potentiometers, P1 and P2 will be necessary for most applications where it is desirable to take advantage of the multiplier's excellent linearity characteristics. Depending upon the particular application, some of the potentiometers can be omitted (see Figures 19, 21, 24, 26 and 27). The MC1494 multiplier, like most linear ICs, requires a DC bias current into its input terminals. The device cannot be capacitively coupled at the input without regard for this bias current. If inputs VX and VY are able to supply the small bias current ( 0.5 A) resistors R can be omitted (see Figure 18). If the MC1494 is used in an AC mode of operation and capacitive coupling is used the value of resistor R can be any reasonable value up to 100 k. For minimum noise and optimum temperature performance, the value of resistor R should be as low as practical. Offset and Scale Factor Adjustment Procedure The adjustment procedure for the circuit of Figure 18 is: A. X Input Offset 1. Connect oscillator (1.0 kHz, 5.0 Vpp sinewave) to the ``Y'' input (Pin 9). 2. Connect ``X'' input (Pin 10) to ground. 3. Adjust X-offset potentiometer, P2 for an AC null at the output. B. Y Input Offset 1. Connect oscillator (1.0 kHz, 5.0 Vpp sinewave) to the ``X'' input (Pin 10). 2. Connect ``Y'' input (Pin 9) to ground. 3. Adjust Y-offset potentiometer, P1 for an AC null at the output. C. Output Offset 1. Connect both ``X'' and ``Y'' inputs to ground. 2. Adjust output offset potentiometer, P3 until the output voltage VO is 0 Vdc. D. Scale Factor 1. Apply +10 Vdc to both the ``X'' and ``Y'' inputs. 2. Adjust P4 to achieve -10 V at the output. 3. Apply -10 Vdc to both ``X'' and ``Y'' inputs and check for VO = -10 V. E. Repeat steps A through D as necessary. Parasitic Oscillation When long leads are used on the inputs, oscillation may occur. In this event, an RC parasitic suppression network similar to the ones shown in Figure 18 should be connected directly to each input using short leads. The purpose of the network is to reduce the "Q" of the source-tuned circuits which cause the oscillation. Inability to adjust the circuit to within the specified accuracy may be an indication of oscillation. AC OPERATION General For AC operation, such as balanced modulation, frequency doubler, AGC, etc., the op amp will usually be omitted as well as the output offset adjust potentiometer. The output offset adjust potentiometer is omitted since the output will normally be AC coupled and the DC voltage at the output is of no concern providing it is close enough to zero volts that it will not cause clipping in the output waveform. Figure 19 shows a typical AC multiplier circuit with a scale factor K 1. Again, resistor RX and RY are chosen as outlined in the previous section, with RL chosen to provide the required scale factor. The ability to accurately adjust the MC1494 is dependent on the offset adjust potentiometers. Potentiometers should be of the "infinite" resolution type rather than wirewound. Fine adjustments in balanced-modulator applications may require two potentiometers to provide "coarse" and "fine" adjustment. Potentiometers should have low temperature coefficients and be free from backlash. 1 1 Temperature Stability 9 ey While the MC1494 provides excellent performance in itself, overall performance depends to a large degree on the quality of the external components. Previous discussion shows the direct dependence on RX, RY and RL and indirect dependence on R1 (through I1). Any circuit subjected to temperature variations should be evaluated with these effects in mind. 3.0 k 6.2 k RX RY 12 5 + eo 14 MC1494 10 R 8 15 R ex 7 +15 V -15 V 1 + 6 13 4 51 k 20 k 2 RL 4.7 k 16 k CO 3 K=1 20 k ex (max) = ey(max) = 1.0 V Figure 19. Wideband Multiplier http://onsemi.com 8 MC1494 amplifier applications, the best tradeoff with frequency response and gain is achieved by using the "Y" input for the AC signal. For AC applications requiring bandwidths greater than those specified for the MC1494, two other devices are recommended. For modulator-demodulator applications, the MC1496 may be used up to 100 MHz. For wideband multiplier applications, the MC1495 (using small collector loads and AC coupling) can be used. The offset voltage then existing at the output will be equal to the offset current times the load resistance. The output offset current of the MC1494 is typically 17 A and 35 A maximum. Thus, the maximum output offset would be about 160 mV. Bandwidth The bandwidth of the MC1494 is primarily determined by two factors. First, the dominant pole will be determined by the load resistor and the stray capacitance at the output terminal. For the circuit shown in Figure 19, assuming a total output capacitance (CO) of 10 pF, the 3.0 dB bandwidth would be approximately 3.4 MHz. If the load resistor were 47 k, the bandwidth would be approximately 340 kHz. Secondly, a "zero" is present in the frequency response characteristic for both the "X" and "Y" inputs which causes the output signal to rise in amplitude at a 6.0 dB/octave slope at frequencies beyond the breakpoint of the "zero". The "zero" is caused by the parasitic and substrate capacitance which is related to resistors RX and RY and the transistors associated with them. The effect of these transmission "zeros" is seen in Figures 11 and 12. The reason for this increase in gain is due to the bypassing of RX and RY at high frequencies. Since the RY resistor is approximately twice the value of the RX resistor, the zero associated with the "Y" input will occur at approximately one octave below the zero associated with "X" input. For RX = 30 k and RY = 62 k, the zeros occur at 1.5 MHz for the "X" input and 700 kHz for the "Y" input. These two measured breakpoints correspond to a shunt capacitance of about 3.5 pF. Thus, for the circuit of Figure 19, the "X" input zero and "Y" input zero will be at approximately 15 MHz and 7.0 MHz respectively. It should be noted that the MC1494 multiplies in the time domain, hence, its frequency response is found by means of complex convolution in the frequency (Laplace) domain. This means that if the "X" input does not involve a frequency, it is not necessary to consider the "X" side frequency response in the output product. Likewise, for the "Y" side. Thus, for applications such as a wideband linear AGC amplifier which has a DC voltage as one input, the multiplier frequency response has one zero and one pole. For applications which involve an AC voltage on both the "X" and "Y" side such as a balanced modulator, the product voltage response will have two zeros and one pole, hence, peaking may be present in the output. From this brief discussion, it is evident that for AC applications; (1) the value of resistors RX, RY and RL should be kept as small as possible to achieve maximum frequency response, and (2) it is possible to select a load resistor RL such that the dominant pole (RL, CO) cancels the input zero (RX, 3.5 pF or RY, 3.5 pF) to give a flat amplitude characteristic with frequency. This is shown in Figures 11 and 12. Examination of the frequency characteristics of the "X" and "Y" inputs will demonstrate that for wideband Slew-Rate The MC1494 multiplier is not slew-rate limited in the ordinary sense that an op amp is. Since all the signals in the multiplier are currents and not voltages, there is no charging and discharging of stray capacitors and thus no limitations beyond the normal device limitations. However, it should be noted that the quiescent current in the output transistors is 0.5 mA and thus the maximum rate of change of the output voltage is limited by the output load capacitance by the simple equation: Slew Rate VO IO = T C Thus, if CO is 10 pF, the maximum slew rate would be: 0.5 x 10- 3 VO = 50 V/s = T 10 x 10-12 This can be improved, if necessary, by the addition of an emitter-follower or other type of buffer. Phase Vector Error All multipliers are subject to an error which is known as the phase vector error. This error is a phase error only and does not contribute an amplitude error per se. The phase vector error is best explained by an example. If the "X" input is described in vector notation as; X= A0 and the "Y" input is described as; Y= B0 then the output product would be expected to be; VO= AB0 (see Figure 20) However, due to a relative phase shift between the ``X'' and ``Y'' channels, the output product will be given by: VO = AB Notice that the magnitude is correct but the phase angle of the product is in error. The vector (V) associated with this error is the ``phase vector error''. The startling fact about the phase vector error is that it occurs and accumulates much more rapidly than the amplitude error associated with frequency response. In fact, a relative phase shift of only 0.57 will result in a 1% phase vector error. For most applications, this error is meaningless. If phase of the output product is not important, then neither is the phase vector error. If phase is important, such as in the case of double sideband modulation or http://onsemi.com 9 MC1494 DC APPLICATIONS demodulation, then a 1% phase vector error will represent a 1% amplitude error a the phase angle of interest. Squaring Circuit If the two inputs are connected together, the resultant function is squaring: VO = KV2 X = A 0 Y = B 0 AB V where K is the scale factor (see Figure 21). However, a more careful look at the multiplier's defining equation will provide some useful information. The output voltage, without initial offset adjustments is given by: VO = K(VX + Viox -VX off) (VY + Vioy -VY off) + VOO (Refer to "Definitions" section for an explanation of terms.) With VX = VY = V (squaring) and defining; x = Viox - Vx (off) y = Vioy - Vy (off) The output voltage equation becomes: VO = KVx2+ KVx (x + y) + Kx y + VOO AB 0 Figure 20. Phase Vector Error Circuit Layout If wideband operation is desired, careful circuit layout must be observed. Stray capacitance across RX and RY should be avoided to minimize peaking (caused by a zero created by the parallel RC circuit). 30 k 11 9 V 12 7 P4 8 + 5 + 2 14 10 pF - + 1 510 16 k 6 MC1456 3 10 pF 22 k 50 k 15 MC1494 10 +15 V -15 V 62 k 3 6 13 4 51 k 20 k P1 20 k 2 + VO = -V2 10 7 4 Input Offset P3 -15 V Output Offset +15 V Figure 21. MC1494 Squaring Circuit This shows that all error terms can be eliminated with only three adjustment potentiometers, eliminating one of the input offset adjustments. For instance, if the "X" input offset adjustment is eliminated, x is determined by the internal offset (Viox) but y is adjustable to the extent that the (x+y) term can be zeroed. Then the output offset adjustment is used to adjust the Voo term and thus zero the remaining error terms. An AC procedure for nulling with three adjustments is: 5. Repeat steps 1 through 4 as necessary. B. DC Procedure: 1. Set VX = VY = 0 V and adjust P3 (output offset potentiometer) such that VO = 0 Vdc. 2. Set VX = VY = 1.0 V and adjust P1 (Y input offset potentiometer) such that the output voltage is - 0.100 V. 3. Set VX = VY = 10 Vdc and adjust P4 (load resistor) such that the output voltage is -10 V. 4. Set VX = VY = -10 Vdc and check that VO = -10 V. 5. Repeat steps 1 through 4 as necessary. A. AC Procedure: 1. Connect oscillator (1.0 kHz, 15 Vpp) to input. 2. Monitor output at 2.0 kHz with tuned voltmeter and adjust P4 for desired gain ( Be sure to peak response of voltmeter). 3. Tune voltmeter to 1.0 kHz and adjust P1 for a minimum output voltage. 4. Ground input and adjust P3 (output offset) for 0 Vdc out. Divide Divide circuits warrant a special discussion as a result of their special problems. Classic feedback theory teaches that if a multiplier is used as a feedback element in an operational amplifier circuit, the divide function results. Figure 22 http://onsemi.com 10 MC1494 illustrates the theoretical simplicity of such an approach and a practical realization is shown in Figure 23. The characteristic "failure" mode of the divide circuit is latch-up. One way it can occur is if VX is allowed to go negative, or in some cases, if VX approaches zero. Figure 22 illustrates why this is so. For VX > 0 the transfer function through the multiplier is noninverting. Its output is fed to the inverting input of the op amp Thus, operation is in the negative feedback mode and the circuit is DC stable. Should VX change polarity, the transfer function through the multiplier becomes inverting, the amplifier has positive feedback and latch-up results. The problem resulting from VX being near zero is a result of the transfer through the multiplier being near zero. The op amp is then operating with a very high closed-loop gain and error voltages can thus become effective in causing latch-up. The other mode of latch-up results from the output voltage of the op amp exceeding the rated common mode input voltage of the multiplier. The input stage of the multiplier becomes saturated, phase reversal results, and the circuit is latched up. The circuit of Figure 23 protects against this happening by clamping the output swing of the op amp to approximately 10.7 V. Five percent tolerance, 10 V zeners are used to assure adequate output swing but still limit the output voltage of the op amp from exceeding the common mode input range of the MC1494. Setting up the divide circuit for reasonably accurate operation is somewhat different from the procedure for the multiplier itself. One approach, however, is to break the feedback loop, null out the multiplier circuit, and then close the loop. VX KVX VY + + + VY VZ = -KVXVY or -VZ VO = KVX MC1494 VZ + - - VO + Figure 22. Basic Divide Circuit Using Multiplier RL 30 k 11 9 10 pF 12 7 10 pF 14 1 MC1494 10 3 2 - 6 MC1741CP1 16 k 3 4 + VO 1N5240A (10 V) or Equivalent 7 + 5 VZ 22 k 8 + 510 VX 10 pF 50 k 62 k 6 15 13 510 4 P1 20 k VO = 2 -10 VZ VX P3 50 k +15 V P2 20 k -15 V -15 V +15 V 0 < VX < +10 V -10 V VZ +10 V Figure 23. Practical Divide Circuit 4. A simpler approach, since it does not involve breaking the loop (thus making it more practical on a production basis), is: 1. Set VZ = 0 V and adjust the output offset potentiometer (P3) until the output voltage (VO) remains at some (not necessarily zero) constant value as VX is varied between +1.0 V and +10 V. 2. Maintain VZ at 0 V, set VX at +10 V and adjust the Y input offset potentiometer (P1) until VO = 0 V. 3. With VX = VZ, adjust the X input offset potentiometer (P2) until the output voltage remains at some (not necessarily -10 V) constant value as VZ = VX is varied between +1.0 V and +10 V. 5. Maintain VX = VZ and adjust the scale factor potentiometer (RL) until the average value of VO is -10 V as VZ = VX is varied between +1.0 V and +10 V. Repeat steps 1 through 4 as necessary to achieve optimum performance. Users of the divide circuit should be aware that the accuracy to be expected decreases in direct proportion to the denominator voltage. As a result, if VX is set to 10 V and 0.5% accuracy is available, then 5% accuracy can be expected when VX is only 1.0 V. In accordance with an earlier statement, VX may have only one polarity (positive) while VZ may be either polarity. http://onsemi.com 11 MC1494 KVO2 KVO2 = -VZ X MC1494 or + + VZ |VZ| K VO = + NOTE: Operation near 0 V input may prove very inaccurate, hence, it may not be possible to adjust VO to zero but rather only to within 100 mV to 400 mV of zero. VZ 0 V - AC APPLICATIONS Wideband Amplifier with Linear AGC VO + If one input to the MC1494 is a DC voltage and a signal voltage is applied to the other input, the amplitude of the output signal can be controlled in a linear fashion by varying the DC voltage. Hence, the multiplier can function as a DC coupled, wideband amplifier with linear AGC control. In addition to the advantage of linear AGC control, the multiplier has three other distinct advantages over most other types of AGC systems. First, the AGC dynamic range is theoretically infinite. This stems from the basic fact that with 0 Vdc applied to the AGC, the output will be zero regardless of the input. In practice, the dynamic range is limited by the ability to adjust the input offset adjust potentiometers. By using cermet multi-turn potentiometers, a dynamic range of 80 dB can be obtained. The second advantage of the multiplier is that variation of the AGC voltage has no effect on the signal handling capability of the signal port, nor does it alter the input impedance of the signal port. This feature is particularly important in AGC systems which are phase sensitive. A third advantage of the multiplier is that the output voltage swing capability and output impedance are unchanged with variations in AGC voltage. Figure 24. Basic Square Root Circuit Square Root A special case of the divide circuit in which the two inputs to the multiplier are connected together results in the square root function as indicated in Figure 24. This circuit too may suffer from latch-up problems similar to those of the divide circuit. Note that only one polarity of input is allowed and diode clamping (see Figure 25) protects against accidental latch-up. This circuit too, may be adjusted in the closed-loop mode: 1. Set VZ = -0.01 Vdc and adjust P3 (output offset) for VO = 0.316 Vdc. 2. Set VZ to -0.9 Vdc and adjust P2 ("X" adjust) for VO = +3.0 Vdc. 3. Set VZ to -10 Vdc and adjust P4 (gain adjust) for VO = +10 Vdc. 4. Steps 1 through 3 may be repeated as necessary to achieve desired accuracy. RL 30 k 11 9 50 k 62 k 12 7 P4 8 14 + 10 pF 1 510 MC1494 6 10 + 5 15 13 4 2 51 k 2 16 k 3 VZ 22 k 10pF - 6 MC1741C + 4 1N962B (1N5241B) (11V) or VO Equivalent 7 3 VO = 10 |VZ| P3 20 k +15 V -15 V P2 20 k -10 V < VZ < 0 V -15 V +15 V Figure 25. Square Root Circuit 0 Vdc to 1.0 Vdc. The bandwidth of the amplifier is determined by the load resistor and output stray capacitance. For this reason, an emitter-follower buffer has been added to extend the bandwidth in excess of 1.0 MHz. The circuit of Figure 26 demonstrates the linear AGC amplifier. The amplifier can handle 1.0 Vrms and exhibits a gain of approximately 20 dB. It is AGC'd through a 60 dB dynamic range with the application of an AGC voltage from http://onsemi.com 12 MC1494 -15 V +15 V 3.0 k 11 ein 9 12 0.1 F 7 8 0.1 F 5 15 + R + 1 -15 V +15 V 2N3946 (2N3904) or Equivalent 16 k 6 13 11 eo 4 2 51 k em 3.0 k 51 k 3 3.0 k 14 MC1494 10 VAGC 6.2 k The circuit of Figure 27 will provide at typical carrier rejection of 70 dB from 10 kHz to 1.5 MHz. 9 12 ec 20 k P2 10 1 3 15 14 eo = Kecem K=1 RL 4.7 k 6 13 4 51 k eo = em ec P1 Figure 27. Balanced Modulator The adjustment procedure for this circuit is quite simple. 1. Place the carrier signal at Pin 10. With no signal applied to Pin 9, adjust potentiometer P1 such that an AC null is obtained at the output. 2. Place a modulation signal at Pin 9. With no signal applied to Pin 10, adjust potentiometer P2 such that an AC null is obtained at the output. Again, the ability to make careful adjustment of these offsets will be a function of the type of potentiometers used for P1 and P2. Multiple turn cermet type potentiometers are recommended. where m is the modulation frequency and c is the carrier frequency. This equation can be expanded to show the suppressed carrier or balanced modulation: VO = 2 P2 20 k Balanced Modulator When two-time variant signals are used as inputs, the resulting output is suppressed-carrier double-sideband modulation. In terms of sinusoidal inputs, this can be seen in the following equation: VO = K(e1 cosmt) (e2 cosct) 5 20 k ec = 1 Vpk em = 2 Vpk Figure 26. Wideband Amplifier with Linear AGC 8 + 16 k P1 7 0.1 F MC1494 R 20 k 0.1 F + R -15 V 6.2 k Ke1e2 [cos( + ) t + cos( - )t] c m c m 2 Unlike many modulation schemes, which are nonlinear in nature, the modulation which takes place when using the MC1494 is linear. This means that for two sinusoidal inputs, the output will contain only two frequencies, the sum and difference, as seen in the above equation. There will be no spectrum centered about the second harmonic of the carrier, or any multiple of the carrier. For this reason, the filter requirements of a modulation system are reduced to the minimum. Figure 27 shows the MC1494 configuration to perform this function. Notice that the resistor values for RX, RY and RL have been modified. This has been done primarily to increase the bandwidth by lowering the output impedance of the MC1494 and then lowering RX and RY to achieve a gain of 1. The ec can be as large as 1.0 V peak and em as high as 2.0 V peak. No output offset adjust is employed since we are interested only in the AC output components. The input resistors (R) are used to supply bias current to the multiplier inputs as well as provide matching input impedance. The output frequency range of this configuration is determined by the 4.7 k output impedance and capacitive loading. Assuming a 6.0 pF load, the small-signal bandwidth is 5.5 MHz. Frequency Doubler If for Figure 27 both inputs are identical: em = ec = E cost then the output is given by, eo = emec = E2 cos2 t which reduces to, eo = E2 (1 + cos2t) 2 This equation states that the output will consist of a DC term equal to one half the peak voltage squared and the second harmonic of the input frequency. Thus, the circuit acts as a frequency doubler. Two facts about this circuit are worthy of note. First, the second harmonic of the input frequency is the only frequency appearing at the output. The fundamental does not appear. Second, if the input is sinusoidal, the output will be sinusoidal and requires no filtering. The circuit of Figure 27 can be used as a frequency doubler with input frequencies in excess of 2.0 MHz. http://onsemi.com 13 MC1494 Amplitude Modulator exactly equal to the peak value of the modulation (Em). This is done by observing the output waveform and adjusting the input offset potentiometer (P1) until the output exhibits the familiar amplitude modulation waveform. The circuit of Figure 27 is also easily used as an amplitude modulator. This is accomplished by simply varying the input offset adjust potentiometer (P1) associated with the modulation input. This procedure places a DC offset on the modulation input of the multiplier such that the carrier still passes through the multiplier when the modulating signal is zero. The result is amplitude modulation. This is easily seen by examining the basic mathematical expression for amplitude modulation given below. For the case under discussion, with K = 1, eo = (E + Em cosmt) (Ec cosct) Phase Detector If the circuit of Figure 27 has as its inputs two signals of identical frequency, but having a relative phase shift, the output will be a DC signal which is directly proportional to the cosine of phase difference as well as the double frequency term. ec= Ec cosct em= Em cos(ct + ) eo= ecem = EcEm cosct cos(ct + ) where E is the DC input offset adjust voltage. This expression can be written as: eo = Eo [1 + M cosct] cosct or, eo = Ec Em 2 [cos + cos(2ct + )] The addition of a simple low pass filter to the output (which eliminates the second cosine term) and return of R L to an offset adjustment potentiometer will result in a DC output voltage which is proportional to the cosine of the phase difference. Hence, the circuit functions as a synchronous detector. where, Eo = EEc Em = modulation index. and, M = E This is the standard equation for amplitude modulation. From this, it is easy to see that 100% modulation can be achieved by adjusting the input offset adjust voltage to be http://onsemi.com 14 MC1494 DEFINITION OF SPECIFICATIONS Output Offset Current and Voltage - Output offset current (IOO) is the DC current flowing in the output lead when Vx = Vy = 0 and X and Y offset voltages are adjusted to zero. Output offset voltage (VOO) is: Because of the unique nature of a multiplier, i.e., two inputs and one output, operating specifications are difficult to define and interpret. Indeed the same specification may be defined in several completely different ways depending upon which manufacturer is doing the defining. In order to clear up some of the mystery, the following definitions and examples are presented. Multiplier Transfer Function - The output of the multiplier may be expressed by the following equation: VO = K[Vx Viox - Vx(off)] [Vy Vioy -Vy(off)] VOO (1) where, K = scale factor Vx = "x" input voltage Vy = "y" input voltage Viox = "x" input offset voltage Vioy = "y" input offset voltage Vx(off) = "x" input offset adjust voltage Vy(off) = "y" input offset adjust voltage VOO = output offset voltage The voltage transfer characteristic below indicates x, y and output offset voltages. VO VO Output Offset where RL is the load resistance. NOTE: Output offset voltage is defined by many manufacturers with all inputs at zero but without adjusting X and Y offset voltages to zero. Thus, it includes input offset terms, an output offset term and a scale factor term. Scale Factor - Scale factor is the K term in Equation (1). It determines the gain of the multiplier and is expressed approximately by the following equation. K= Output Offset y Offset (Vy = + 10V) (Vx = + 10V) Figure 28. Offset Voltages Linearity - Linearity is defined to be the maximum deviation of output voltage from a straight line transfer function. It is expressed as a percentage of full-scale output and is measured for Vx and Vy separately, either using an X-Y plotter (and checking the deviation from a straight line) or by using the method shown in Figure 3. The latter method nulls the output signal with the input signal, resulting in distortion components proportional to the linearity. Example: 0.35% linearity means VO = Vx Vy 10 2RL kT , where Rx and Ry >> ql1 RxRyl1 and l1 is the current out of Pin 1. Total DC Accuracy - The total DC accuracy of a multiplier is defined as error in multiplier output with DC ( 10 Vdc) applied to both inputs. It is expressed as a percent of full scale. Accuracy is not specified for the MC1494 because error terms can be nulled by the user. Temperature Stability (Drift) - Each term defined above will have a finite drift with temperature. The temperature specifications are obtained by readjusting the multiplier offsets and scale factor at each new temperature (see previous definitions and the adjustment procedure) and noting the change. Assume inputs are grounded and initial offset voltages have been adjusted to zero. Then output voltage drift is given by: VO = [KK (TCK) (T)] [(TCViox) (T)] [(TCVioy) (T)] (TCVOO) (T) Vy Vx x Offset VOO = IOO RL Total DC Accuracy Drift - This is the temperature drift in output voltage with 10 V applied to each input. The output is adjusted to 10 V at TA = + 25C. Assuming initial offset voltages have been adjusted to zero at TA = +25C, then: VO = [ KK (TCK) (T)] [10 (TCViox) (T)] [10 (TCVioy) (T)] (TCVOO) (T) Power Supply Rejection - Variation in power supply voltages will cause undesired variation of the output voltage. It is measured by superimposing a 1.0 V, 100 Hz signal on each supply (15 V) with each input grounded. The resulting change in the output is expressed in mV/V. Output Voltage Swing - Output voltage swing capability is the maximum output voltage swing (without clipping) into a resistive load. (Note, output offset is adjusted to zero). If an op amp is used, the multiplier output becomes a virtual ground - the swing is then determined by the scale factor and the op amp selected. (0.0035)(10 V) Input Offset Voltage - The input offset voltage is defined from Equation (1). It is measured for Vx and Vy separately and is defined to be that DC input offset adjust voltage (x or y) that will result in minimum AC output when AC (5.0 Vpp, 1.0 kHz) is applied to the other input (y or x, respectively). From Equation (1) we have: VO(AC) = K [0 Viox -Vx(off)] [sint] adjust Vx(off) so that [ Viox -Vx(off)] = 0. http://onsemi.com 15 MC1494 OUTLINE DIMENSIONS P SUFFIX PLASTIC PACKAGE CASE 648C-04 ISSUE D A C N F K K T E G 16X 0.005 (0.13) J 8 16X 1 L 9 B 16 M M T B B A NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. DIM A B C D E F G J K L M N INCHES MIN MAX 0.744 0.783 0.240 0.260 0.145 0.185 0.015 0.021 0.050 BSC 0.040 0.70 0.100 BSC 0.008 0.015 0.115 0.135 0.300 BSC 0 10 0.015 0.040 MILLIMETERS MIN MAX 18.90 19.90 6.10 6.60 3.69 4.69 0.38 0.53 1.27 BSC 1.02 1.78 2.54 BSC 0.20 0.38 2.92 3.43 7.62 BSC 0 10 0.39 1.01 SEATING PLANE D 0.005 (0.13) M T A ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION NORTH AMERICA Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: ONlit@hibbertco.com Fax Response Line: 303-675-2167 or 800-344-3810 Toll Free USA/Canada N. American Technical Support: 800-282-9855 Toll Free USA/Canada EUROPE: LDC for ON Semiconductor - European Support German Phone: (+1) 303-308-7140 (Mon-Fri 2:30pm to 7:00pm CET) Email: ONlit-german@hibbertco.com French Phone: (+1) 303-308-7141 (Mon-Fri 2:00pm to 7:00pm CET) Email: ONlit-french@hibbertco.com English Phone: (+1) 303-308-7142 (Mon-Fri 12:00pm to 5:00pm GMT) Email: ONlit@hibbertco.com CENTRAL/SOUTH AMERICA: Spanish Phone: 303-308-7143 (Mon-Fri 8:00am to 5:00pm MST) Email: ONlit-spanish@hibbertco.com Toll-Free from Mexico: Dial 01-800-288-2872 for Access - then Dial 866-297-9322 ASIA/PACIFIC: LDC for ON Semiconductor - Asia Support Phone: 1-303-675-2121 (Tue-Fri 9:00am to 1:00pm, Hong Kong Time) Toll Free from Hong Kong & Singapore: 001-800-4422-3781 Email: ONlit-asia@hibbertco.com JAPAN: ON Semiconductor, Japan Customer Focus Center 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan 141-0031 Phone: 81-3-5740-2700 Email: r14525@onsemi.com ON Semiconductor Website: http://onsemi.com EUROPEAN TOLL-FREE ACCESS*: 00-800-4422-3781 *Available from Germany, France, Italy, UK, Ireland For additional information, please contact your local Sales Representative. http://onsemi.com 16 MC1494/D