E5551A-DOW - Atmel Corporation

e5551

Rev. A1, 26-Jul-99 1 (20)

Standard R/W Identification IC with Anticollision

Description

The e5551 is a contactless R/W-IDentification IC

(IDIC)* for general-purpose applications in the 125 kHz

range. A single coil, connected to the chip, serves as the

IC’s power supply and bidirectional communication

interface. Coil and chip together form a transponder.

The on-chip 264-bit EEPROM (8 blocks 33 bits each) can

be read and written blockwise from a base station. The

blocks can be protected against overwriting. One block is

reserved for setting the operation modes of the IC.

Another block can contain a password to prevent

unauthorized writing.

Reading occurs by damping the coil by an internal load.

There are different bitrates and encoding schemes

possible. Writing occurs by interrupting the RF field in a

special way.

Features

Low-power, low-voltage operation

Contactless power supply

Contactless read/write data transmission

Radio Frequency (RF): 100 to 150 kHz

264 bit EEPROM memory in 8 blocks of 33 bits

224 bits in 7 blocks of 32 bits are free for user data

Block write protection

Extensive protection against contactless malpro-

gramming of the EEPROM

Anticollision using Answer-On-Request (AOR)

Typical < 50 ms to write and verify a block

Other options set by EEPROM:

Bitrate [bit/s]: RF/8, RF/16, RF/32, RF/40

RF/50, RF/64, RF/100, RF/128

Modulation: BIN, FSK, PSK, Manchester,

Biphase

Other: Terminator mode,

Password mode

Controller

Coil interface

Memory

Transponder

Base station Data

Power

16581

Controller

Coil interface

Memory

e5551

Transponder

Base station Data

Power

Figure 1. RFID system using e5551 tag

* IDICstands for IDentification Integrated Circuit and is a trademark of TEMIC Semiconductors

e5551

Rev. A1, 26-Jul-992 (20)

e5551 Building Blocks

Analog Front End (AFE)

The AFE includes all circuits which are directly

connected to the coil. It generates the IC’s power supply

and handles the bidirectional data communication with

the reader unit. It consists of the following blocks:

Rectifier to generate a dc supply voltage from the ac

coil voltage

Clock extractor

Switchable load between Coil1/ Coil2 for data trans-

mission from the IC to the reader unit (read)

Field gap detector for data transmission from the

reader unit into the IC (write)

Controller

The main controller has following functions:

Load mode register with configuration data from

EEPROM block 0 after power-on and also during

reading

Control memory access (read, write)

Handle write data transmission and the write error

modes

The first two bits of the write data stream are the OP-

code. There are two valid OP-codes (standard and

stop) which are decoded by the controller.

In password mode, the 32 bits received after the OP-

code are compared with the stored password in

block 7.

Bitrate Generator

The bitrate generator can deliver the following bitrates:

RF/8 - RF/16 - RF/32 - RF/40 - RF/50 - RF/64 - RF/100 - RF/128

Write Decoder

Decode the detected gaps during writing. Check if write

data stream is valid.

Test Logic

Test circuitry allows rapid programming and verification

of the IC during test.

HV Generator

Voltage pump which generates ~18 V for programming

of the EEPROM.

Coil 1

Coil 2

Modulator

Analog front end

POR

Input register

Write

decoder

Birate

generator

Memory

(264 bit EEPROM)

Controller

Test logic

Mode register

HV generator

VTest pads

DD VSS

95 10206

Figure 2. Block diagram e5551

e5551

Rev. A1, 26-Jul-99 3 (20)

Power-On Reset (POR)

The power-on reset is a delay reset which is triggered

when supply voltage is applied.

Mode Register

The mode register stores the mode data from EEPROM

block 0. It is continually refreshed at the start of every

block. This increases the reliability of the device (if the

originally loaded mode information is false, it will be

corrected by subsequent refresh cycles).

Modulator

The modulator consists of several data encoders in two

stages, which may be freely combined to obtain the

desired modulation. The basic types of modulation are:

PSK: phase shift: 1) every change; 2) every ‘1’;

3) every rising edge (carrier: fc/2, fc/4 or fc/8)

FSK: 1) f1 = rf/8 f2 = rf/5; 2) f1 = rf/8, f2 = rf/10

Manchester: rising edge = H; falling edge = L

Biphase: every bit creates a change, a data ‘H’ creates

an additional mid-bit change

Note: The following modulation type combinations will

not work:

Stage1 Manchester or Biphase, stage2 PSK2, at any

PSK carrier frequency (because the first stage output

frequency is higher than the second stage strobe

frequency)

Stage1 Manchester or Biphase and stage2 PSK with

bitrate = rf/8 and PSK carrier frequency = rf/8 (for the

same reason as above)

Any stage1 option with any PSK for bitrates rf/50 or

rf/100 if the PSK carrier frequency is not an integer

multiple of the bitrate (e.g., br = rf/50, PSKcf = rf/4,

because 50/4 = 12.5). This is because the PSK carrier

frequency must maintain constant phase with respect

to the bit clock.

Memory

The memory of the e5551 is a 264 bit EEPROM, which

is arranged in 8 blocks of 33 bits each. All 33 bits of a

block, including the lock bit, are programmed simulta-

neously. The programming voltage is generated on-chip.

Block 0 contains the mode data, which are not normally

transmitted (see figure 5).

Block 1 to 6 are freely programmable. Block 7 may be

used as a password. If password protection is not required,

it may be used for user data.

Bit 0 of every block is the lock bit for that block. Once

locked, the block (including the lockbit itself) cannot be

field-reprogrammed.

Data from the memory is transmitted serially, starting

with block 1, bit 1, up to block ‘MAXBLK’, bit 32.

‘MAXBLK’ is a mode parameter set by the user to a value

between 0 and 7 (if maxblk=0, only block 0 will be trans-

mitted).

Block 7

Block 6

Block 5

Block 4

Block 3

Block 2

Block 1

Block 0

User data or password

32 bits

User data

Configuration data

1320

Not transmitted 16600

Figure 3. Memory map

Direct

Manchester

Biphase

PSK1

PSK2

PSK3

Direct

FSK1, 1a

FSK2, 2a

From memory to load

Carrier frequency

muxmux

95 10207

Figure 4. Modulator block diagram

e5551

Rev. A1, 26-Jul-994 (20)

MAXBLK

reserved

011 25 2715

[2] [1] [0]

MS2

18 20

[2] [1] [0]

MS1

16 17

[1] [0]

31302928242322

[1] [0]

12 14

[2] [1] [0] res’d

*useSTOP

useBT

AOR

”0”

useST

send blocks:

usePWD

Key:

–––––––––––––––––––––––––––––––––––––

AOR Anwer-On-Request

useBT use Block Terminator

useST use Sequence Terminator

usePWD use Password

useSTOP obey stop header (active low!)

BR Bit Rate

MS1 Modulator Stage 1

MS2 Modulator Stage 2

PSKCF PSK Clock Frequency

MAXBLK see Maxblock feature

reserved do not use

* Bit 15 and 24 must always be at ”0”,

otherwise malfunction will appear.

lock bit (never transmitted)

PSKCF

21 261913

95 10228

0000

0011

0101 to 2

0111 to 3

1001 to 4

1011 to 5

1101 to 6

1111 to 7

0 0 RF/2

0 1 RF/4

1 0 RF/8

1 1 reserved

0 0 0 direct

0 0 1 psk1 (phase change when input changes)

0 1 0 psk2 (phase change on bitclk if input high)

0 1 1 psk3 (phase change on rising edge of input)

–––––––––––––––––––––––––––––––––––

o/p freq. DATA=1 DATA=0

1 0 0 fsk1 rf/8 rf/5

1 0 1 fsk2 rf/8 rf/10

1 1 0 fsk1a rf/5 rf/8

1 1 1 fsk2a rf/10 rf/8

0 0 direct

0 1 Manchester

1 0 Biphase

1 1 reserved

0 0 0 RF/8 bitrate_8cpb

0 0 1 RF/16 bitrate_16cpb

0 1 0 RF/32 bitrate_32cpb

0 1 1 RF/40 bitrate_40cpb

1 0 0 RF/50 bitrate_50cpb

1 0 1 RF/64 bitrate_64cpb

1 1 0 RF/100 bitrate_100cpb

1 1 1 RF/128 bitrate_128cpb

”0”

Figure 5. Memory map of block 0

e5551

Rev. A1, 26-Jul-99 5 (20)

Operating the e5551

General

The basic functions of the e5551 are: supply IC from the

coil, read data from the EEPROM to the reader, write

data into the IC and program these data into the

EEPROM. Several errors can be detected to protect the

memory from being written with the wrong data (see

figure 20).

Supply

The e5551 is supplied via a tuned LC circuit which is con-

nected to the Coil1 and Coil2 pads. The incoming RF

(actually a magnetic field) induces a current into the coil.

The on-chip rectifier generates the dc supply voltage

(Vdd, Vss pads). Overvoltage protection prevents the IC

from damage due to high-field strengths. Depending on

the coil, the open-circuit voltage across the LC circuit can

reach more than 100 V. The first occurrence of RF trig-

gers a power-on reset pulse, ensuring a defined start-up

state.

Read

Reading is the default mode after power-on reset. It is

done by switching a load between the coil pads o n and of f.

This changes the current through the IC coil, which can

be detected from the reader unit.

Start-Up

The many different modes of the e5551 are activated after

the first readout of block 0. The modulation is off while

block 0 is read. After this set-up time of 256 field clock

periods, modulation with the selected mode starts.

Any field gap during this initialization will restart the

complete sequence.

Read Datastream

The first block transmitted is block 1. When the last block

is reached, reading restarts with block 1. Block 0, which

contains mode data, is normally never transmitted. How-

ever, the mode register is continuously refreshed with the

contents of EEPROM block 0.

e5551

IAC

125 kHz

Energy

Data

Tuned LCReader coil

16582

Figure 6. Application circuit

Damping on Damping off

Read data with configured

modulation and bitrate

16583

Coil 1 – Coil 2

* FC –> Field clocks

Loading block 0 (256 FC2 ms)

2 ms

Power-on

reset

Figure 7. Voltage at Coil1/Coil2 after power-on

e5551

Rev. A1, 26-Jul-996 (20)

Block

Sequence

Bit period

Last bit First bit

ÏÏÏÏ

Data bit ’1’

ÏÏÏÏ

Data bit ’1’ Data bit ’1’

13366

Waveforms for different

modulations Manchester

FSK

PSK

Terminator not suitable for Biphase modulation

First bit ’0’ or ’1’

Block terminator

Sequence terminator

VCoil1–Coil2

Figure 8. Terminators

ÏÏÏÏ

Block 1

ÏÏÏÏÏ

Block 2

ÏÏÏÏÏ

Block 7

ÏÏÏÏÏ

Block 1

ÏÏÏÏÏ

Block 2

No terminators

ÏÏÏÏÏ

Block 1

ÏÏÏÏÏ

Block 2

ÏÏÏÏ

Block 7

ÏÏÏÏ

Block 1

ÏÏÏÏÏ

Block 2

useST = on useBT = off

useST = off useBT = on

useST = on useBT = on

ÏÏÏÏÏ

Block 1

ÏÏÏÏÏ

Block 2

ÏÏÏÏ

Block 7

ÏÏÏÏ

Block 1

ÏÏÏÏ

Block 2

ÏÏ

ÏÏÏÏÏ

Block 1

ÏÏÏÏÏ

Block 2

ÏÏÏÏ

Block 7

ÏÏÏÏÏ

Block 1

ÏÏÏÏ

Block 2

ÏÏ

95 10232

ÏÏ

Loading block 0

Block terminator

Sequence terminator

Figure 9. Read data streams and terminators

Block 1 Block 4 Block 5 Block 1 Block 2

MAXBLK = 5

MAXBLK = 2

MAXBLK = 0

Block 1 Block 2 Block 1 Block 2 Block 1

Block 0 Block 0 Block 0 Block 0 Block 0

95 10233

Loading block 0

Figure 10. MAXBLK examples

e5551

Rev. A1, 26-Jul-99 7 (20)

Maxblock Feature

If it is not necessary to read all user data blocks; the

MAXBLK field in block 0 can be used to limit the number

of blocks read. For example, if MAXBLK = 5, the e5551

repeatedly reads and transmits only blocks 1 to 5 (see fig-

ure 10). If MAXBLK is set to ‘0’, block 0 – which is

normally not transmitted – can be read.

Terminators

The terminators are (optionally selectable) special

damping patterns, which may be used to synchronize the

reader. There are two types available; a block terminator

which precedes every block, and a sequence terminator

which always follows the last block.

The sequence terminator consists of two consecutive

block terminators. The terminators may be individually

enabled with the mode bits useST (sequence terminator

enable) or useBT (block terminator enable).

Note: It is not possible to include a sequence terminator

in a transmission where MAXBLK = 0.

Dir ect Access

The direct access command allows the reading of an indi-

vidual block by sending the OP-code (’10‘), the lock-bit

and the 3-bit address.

Note: usePWD has to be 0.

Modulation and Bitrate

There are two modulator stages in the e5551 (see figure 4)

whose mode can be selected using the appropriate bits in

block 0 (MS1[1:0] and MS[2:0]). Also the bitrate can be

selected using BR[2:0] in block 0. These options are

described in detail in figures 21 through 26.

Anticollision Mode

When the AOR bit is set, the IC does not start modulation

after loading configuration block 0. It waits for a valid

AOR data stream (wake-up command) from the reader

before modulation is enabled.

The wake-up command consists of the OP-code (’10‘) fo-

lowing by a valid password. The IC will remain active

until the RF field is turned off or a stop OP-code is re-

ceived.

Table 1. e5551 – modes of operation

usePWD AOR useSTOP Behavior of Tag after Reset / POR STOP Function

110Anticollision mode:

Modulation starts after wake-up

with a matching PWD

Programming needs valid PWD

AOR allows programing with read

protection (no read after write)

STOP OP-code (’11‘) defeats modu-

lation until RF field is turned off

100Password mode:

Modulation starts after reset

Programming needs valid PWD

010Modulation starts after wake-up

command

Programming with modulation

defeat without previous wake-up

possible

AOR allows programing with read

protection (no read after write)

000Modulation starts after reset

Direct access command

Programming without password

x01See corresponding modes above STOP OP-code ignored, modulation

continues until RF field is turned off

e5551

Rev. A1, 26-Jul-998 (20)

POR Loading block 0 No modulation

(

useSTOP = 0

AOR = 1

)

Modulation on

16601

Coil 1 – Coil 2

OP-code (’10’) followed by valid password

Figure 11. Answer-on-request (AOR) mode

enter AOR mode

POWER ON RESET

read configuration

wait for OPCODE + PWD

(== wake up command)

write damping

PWD correct ?

send block 1...MAXBLK

until ST OP command

internal reset sequence

YES

TAG

init tags with

AOR = ’1’, usePWD = ’1’, useStop = ’0’

send stop command

”select single tag”

send OPCODE + PWD

(== wake up command)

decode data

all tags read ?

EXIT

wait for t W > 2.5ms

YES

BASE station

Field OFF –> ON

16602

Figure 12. Anticollision procedure

e5551

Rev. A1, 26-Jul-99 9 (20)

RF_Field

Gap

Write data

Field clock

Start 110

Damping

Write mode

Data Clock

Load On Load Off

>64 FCs = stop write

Programming Read modeRead mode Writing 95 11378

Modulation during read mode

Figure 13. Signals during writing

Write data decoder

1 16324864

fail 0 fail 1 writing done

95 10236

Figure 14. Write data decoding schemes

2 Addr 0

Password mode

AOR (wake-up command)

Standard write

Stop command

16603

10 1 Data bits 32

1 Password 32

Direct access

2 Addr 0

Figure 15. e5551 – OP-code formats

Write

Writing data into the IC occurs via the TEMIC write

method. It is based on interrupting the RF field with short

gaps. The time between two gaps encodes the ‘0/1’

information to be transmitted.

Start Gap

The first gap is the start gap which triggers write mode.

In write mode, the damping is permanently enabled

which eases gap detection. The start gap may need to be

longer than subsequent gaps in order to be detected

reliably.

A start gap will be detected at any time after block 0 has

been read (field-on plus approximately 2 ms).

e5551

Rev. A1, 26-Jul-9910 (20)

Start of writing

Read mode Write mode

(start gap)

95 10238

Figure 16. Start of writing

Decoder

The duration of the gaps is usually 50 to 150 s. The time

between two gaps is nominally 24 field clocks for a ‘0’

and 56 field clocks for a ‘1’. When there is no gap for more

than 64 field clocks after previous gap, the IDIC exits

write mode; it starts with programming if the correct

number of valid bits were received.

If there is a gap fail – i.e., one or more of the intervals did

represent not a valid ‘0’ or ‘1’ – the IC does not program,

but enters read mode beginning with block 1, bit 1.

Writing Data into the e5551

The e5551 expects a two bit OP-code first. There are two

valid OP-codes (’10‘ and ’11‘). If the OP-code is invalid,

the e5551 starts read mode beginning with block 1 after

the last gap. The OP-code (’10‘) is followed by different

information (see figure 15):

Standard writing needs the OP-code, the lock bit, the

32 data bits and the 3-bit block address.

Writing with usePWD set requires a valid password

between OP-code and address/data bits.

In AOR mode with usePWD, OP-code and a valid

password are necessary to enable modulation.

The STOP OP-code is used to silence the e5551 (dis-

able damping until power is cycled).

Note: The data bits are read in the same order as written.

STOP OP-Code

The S TOP OP-code (‘11’) is used to stop modulation until

a power-on reset occurs. This feature can be used to have

a steady RF field where single transponders are collected

one by one. Each IC is read and than disabled, so that it

does not interfere with the next IC.

Note: The STOP OP-code should contain only the two

OP-code bits to disable the IC. Any additional data sent

will not be ignored, and the IC will not stop modulation.

Standard OP-code

Stop OP-code

Read mode Write mode

Start gap

more data ...

> 64 clocks

1 1

95 10239

Figure 17. OP-code transmission

Password

When password mode is on (usePWD = 1), the first

32 bits after the OP-Code are regarded as the password.

They are compared bit-by-bit with the contents of block

7, starting at bit 1. If the comparison fails, the IC will not

program the memory, but restart in read mode at block 1

once writing has completed.

Notes:

If usePWD is not set, but the IC receives a write

datastream containing any 32 bits in place of a pass-

word, the IC will enter programming mode.

The first 4 bits of the password have to be ”0”.

In password mode, MAXBLK should be set to a value

below 7 to prevent the password from being trans-

mitted by the e5551.

Every transmission of 2 OP-code bits, 32 password

bitsplus, one lock bit, 32 data bits and 3 address bits

(=70 bits) needs about 35 ms. Testing all 232 possible

combinations (about 4.3 billion) takes about 40,000 h,

or over four years. This is a sufficient password

protection for a general-purpose IDIC.

e5551

Rev. A1, 26-Jul-99 11 (20)

16 ms

No modulation

W rite mode

Check V

HV on

Modulation

Operation Write Vpp/Lock ok? Program EEPROM READ

0.12 ms

W riting done (> 64 clocks since last gap)

Programming ends

Reading starts

Programming starts

HV on for testing if Vpp is ok

(HV at EEPROMs)

95 10240

Figure 18. Programming

16 ms Read programming block Read next block

Programming with updated modes

Write data into the IC

(e.g., new bitrate)

(= block 0)

95 10241

Coil 1 – Coil 2

Figure 19. Coil voltage after programming of block 0

Programming

When all necessary information has been written to the

e5551, programming may proceed. There is a 32-clock

delay between the end of writing and the start of pro-

gramming. During this time, Vpp – the EEPROM

programming voltage – is measured and the lock bit for

the block to be programmed is examined. Further, Vpp is

continually monitored throughout the programming

cycle. If at any time Vpp is too low, the chip enters read

mode immediately.

The programming time is 16 ms.

After programming is done, the e5551 enters read mode,

starting with the block just programmed. If either block

or sequence terminators are enabled, the block is pre-

ceded by a block terminator. If the mode register (block 0)

has been reprogrammed, the new mode will be activated

after the just-programmed block has been transmitted

using the previous mode.

Error Handling

Several error conditions can be detected to ensure that

only valid bits are programmed into the EEPROM. There

are two error types which lead to different actions.

Errors During Writing

There are four detectable errors which could occur during

writing data into the e5551:

Wrong number of field clocks between two gaps

The OP-code is neither the standard OP-code (’10‘)

nor the stop OP-code (’11‘)

Password mode is active but the password does not

match the contents of block 7

The number of bits received is incorrect;

valid bit counts are

Standard write 38 bits (usePWD not set)

Password write 70 bits (usePWD set)

AOR wake-up 34 bits

e5551

Rev. A1, 26-Jul-9912 (20)

Stop command 2 bits

If any of these four conditions are detected, the IC

starts read mode immediately after leaving write mode.

Reading starts with block 1.

Errors During Programming

If writing was successful, the following errors could

prevent programming:

The lock bit of the addressed block is set

VPP is too low

In these cases, programming stops immediately. The IC

reverts to read mode, starting with the currently addressed

block.

Power-on reset

block 0

READ

OP-code

Password

Number of bits

Lock bit

W rite mode

PROGRAM

addr1addrcurrent

Stop fail

fail

16604

Figure 20. Functional diagram of the e5551

e5551

Rev. A1, 26-Jul-99 13 (20)

RF-field

18 18 916

16 1 8916

916

Inverted modulator

Data stream

1001

8 FC

Data rate = 10

Manchester coded

50 Field Clocks (FC)

signal

16585

Figure 21. Example of Manchester coding with data rate RF/16

16586

RF-field

818

18 91616

916

818916

Inverted modulator

signal

Biphase coded

Data stream

1001

8 FC

Data rate = 10

50 Field Clocks (FC)

Figure 22. Example of Biphase coding with data rate RF/16

e5551

Rev. A1, 26-Jul-9914 (20)

16587

Data stream

1001

Data rate= 10

RF-field

15 18 18 18515

Inverted modulator

signal

40 Field Clocks (FC)

f = RF/8,

f = RF/5

Figure 23. Example of FSK coding with data rate RF/40, sub-

carrier f0 = RF/8, f1 = RF/5

16588

Data stream

001 10

RF-field

21 8 9 161 8 161 8 161 8 16 1 8 16 1 8

Inverted modulator

signal

subcarrier RF/2

8 FC8 FC

Data rate =

16 Field Clocks (FC)

Figure 24. Example of PSK1 coding with data rate RF/16

e5551

Rev. A1, 26-Jul-99 15 (20)

16589

Datas stream

001 10

RF-field

21 8 9 161 8 161 8 161 8 16 1 8 16 1 8

Inverted

modulator signal

subcarrier RF/2

8 FC8 FC

Data rate =

16 Field Clocks (FC)

Figure 25. Example of PSK2 coding with data rate RF/16

16590

Data stream

1001

8 FC8 FC

Data rate = 10

RF-field

21 8 9 161 8 161 8 161 8 16 1 8 16 1 8

Inverted

modulator signal

sub carrier RF/2

16 Field Clocks (FC)

Figure 26. Example of PSK3 coding with data rate RF/16

e5551

Rev. A1, 26-Jul-9916 (20)

Coil 1

Coil 2

VDD

VSS

=2 V

IDD

Vpp Coil≅1.5 V 96 12303

Figure 27. Measurement setup for IDD

Coil 1

Mod

96 12304

Coil 2

100 

~ 2 V

100 

Figure 28. Simplified damping circuit

Application Example

125 kHz Coil 1 (Pin 8)

Coil 2 (Pin 1)

2.2 nF

To read

amplifier

e5551

360 pF4.2 mH

From

oscillator Energy

Data

fres 1

2LC

125 kHz

16584

AC 740 HInput capacitance

5 pF static, 25 pF dynamic

Figure 29. Typical application circuit

e5551

Rev. A1, 26-Jul-99 17 (20)

Absolute Maximum Ratings

Parameters Symbol Value Unit

Maximum DC current into COIL 1/ COIL 2 Icoil 10 mA

Maximum AC current into COIL 1/ COIL 2,

f = 125 kHz icoil pp 20 mA

Power dissipation (dice) 1) Ptot 100 mW

Electro-static discharge maximum to

MIL-Standard 883 C method 3015 Vmax 2000 V

Operating ambient temperature range Tamb –40 to +85 °C

Storage temperature range 2) Tstg –40 to +125 °C

Maximum assembly temperature for less than 5 min 3) Tsld +150 °C

Notes: 1) Free-air condition, time of application: 1 s

2) Data retention reduced

3) Assembly temperature of 150°C for less than 5 minutes does not affect the data retention.

Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.

Operating Characteristics

Tamb = 25°C; fRF = 125 kHz, reference terminal is VSS

Parameters Comments Symbol Min. Typ. Max. Unit

ÁÁÁÁÁÁÁÁÁ

RF frequency range

ÁÁÁÁÁÁÁÁÁ

ÁÁÁÁ

fRF

ÁÁÁÁ

100

ÁÁÁÁ

125

ÁÁÁÁ

150

ÁÁÁÁ

kHz

ÁÁÁÁÁÁÁÁÁ

current

ÁÁÁÁÁÁÁÁÁ

Read and write over the full

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁ

Supply

current

(see figure 27)

ÁÁÁÁÁÁÁÁÁ

Read

and

write

over

the

full

temperature range

ÁÁÁÁ

IDD

ÁÁÁÁ

7.5

ÁÁÁÁ

A

ÁÁÁÁÁÁÁÁÁ

(see

figure

27)

ÁÁÁÁÁÁÁÁÁ

Programming over the full

temperature range

ÁÁÁÁ

IDD

ÁÁÁÁ

100

ÁÁÁÁ

200

ÁÁÁÁ

A

ÁÁÁÁÁÁÁÁÁ

Clamp voltage

ÁÁÁÁÁÁÁÁÁ

10 mA current into Coil1/2

ÁÁÁÁ

Vcl

ÁÁÁÁ

9.5

ÁÁÁÁ

11.5

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁ

Programming voltage

ÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁ

From on-chip HV-

Generator

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

Vpp

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁ

Programming time

ÁÁÁÁÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁ

Startup time

ÁÁÁÁÁÁÁÁÁ

ÁÁÁÁ

tstartup

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁ

Data retention

ÁÁÁÁÁÁÁÁÁ

ÁÁÁÁ

tretention

ÁÁÁÁ

Years

ÁÁÁÁÁÁÁÁÁ

Programming cycles

ÁÁÁÁÁÁÁÁÁ

ÁÁÁÁ

ncycle

ÁÁÁÁ

100 000

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁ

Supply voltage

ÁÁÁÁÁÁÁÁÁ

Read and write

ÁÁÁÁ

VDD

ÁÁÁÁ

1.6

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁ

Supply voltage

ÁÁÁÁÁÁÁÁÁ

Read-mode, T = – 30°C

ÁÁÁÁ

VDD

ÁÁÁÁ

2.0

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁ

Coil voltage

ÁÁÁÁÁÁÁÁÁ

Read and write

ÁÁÁÁ

Vcoil pp

ÁÁÁÁ

6.0

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁ

Coil voltage

ÁÁÁÁÁÁÁÁÁ

Programming,

RF field not damped

ÁÁÁÁ

Vcoil pp

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁ

Damping resistor

ÁÁÁÁÁÁÁÁÁ

ÁÁÁÁ

300

ÁÁÁÁ



Note

1) Since EEPROM performance may be influenced by assembly and packaging, we can confirm the

parameters for dow (= die-on-wafer) and ICs assembled in standard package.

e5551

Rev. A1, 26-Jul-9918 (20)

Ordering Information

Extended Type Number Package Remarks

e5551A-DOW

e5551A-DIT DOW

Dice in tray Default programming: Manchester modulation, RF/32, MAXBLK = 2

Chip Dimensions (m)

Coil 1 Coil 2

16591

e5551

Rev. A1, 26-Jul-99 19 (20)

e5551

Rev. A1, 26-Jul-9920 (20)

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