NCP717
www.onsemi.com
13
APPLICATIONS INFORMATION
The NCP717 is a high performance, small package size,
300 mA LDO voltage regulator. This device delivers very
good noise and dynamic performance. Thanks to its adaptive
ground current feature the device consumes only 25 mA of
quiescent current at no−load condition. The regulator
features very−low noise of 22 mVRMS, PSRR of typ. 70 dB
at 1 kHz and very good load/line transient response. The
device is an ideal choice for space constrained portable
applications.
A logic EN input provides ON/OFF control of the output
voltage. When the EN is low the device consumes as low as
typ. 10 nA from the IN pin.
The device is fully protected in case of output overload,
output short circuit condition and overheating, assuring a
very robust design.
Input Capacitor Selection (CIN)
It is recommended to connect a minimum of 1 μF Ceramic
X5R or X7R capacitor close to the IN pin of the device.
Larger input capacitors may be necessary if fast and large
load transients are encountered in the application. There is
no requirement for the min./max. ESR of the input capacitor
but it is recommended to use ceramic capacitors for their low
ESR and ESL.
Output Capacitor Selection (COUT)
The NCP717 is designed to be stable with small 1.0 mF and
larger ceramic capacitors on the output. The minimum
effective output capacitance for which the LDO remains
stable i s 100 nF. The safety margin is provided to account for
capacitance variations due to DC bias voltage, temperature,
initial tolerance. There is no requirement for the minimum
value of Equivalent Series Resistance (ESR) for the COUT
but the maximum value of ESR should be less than 700 mΩ.
Larger output capacitors could be used to improve the load
transient response or high frequency PSRR characteristics.
It is not recommended to use tantalum capacitors on the
output due to their large ESR. The equivalent series
resistance of tantalum capacitors is also strongly dependent
on the temperature, increasing at low temperature. The
tantalum capacitors are generally more costly than ceramic
capacitors.
No−load Operation
The regulator remains stable and regulates the output
voltage properly within the ±2% tolerance limits even with
no external load applied to the output.
Enable Operation
The NCP717 uses the EN pin to enable/disable its output
and to control the active discharge function. If the EN pin
voltage is < 0.4 V the device is guaranteed to be disabled.
The pass transistor is turned*off so that there is virtually no
current flow between the IN and OUT. In case of the option
equipped with active discharge − the active discharge
transistor i s turned−on and the output voltage VOUT is pulled
to GND through a 1.2 kW resistor (A version) or 120 W
(C version). In the disable state the device consumes as low
as typ. 10 nA from the VIN. If the EN pin voltage > 0.9 V the
device is guaranteed to be enabled. The NCP717 regulates
the output voltage and the active discharge transistor is
turned−off. The EN pin has an internal pull−down current
source with typ. value of 180 nA which assures that the
device is turned−off when the EN pin is not connected. A
build i n 5 6 m V o f h ysteresis a nd d eglitch t ime i n t he E N b lock
prevents from periodic on/off oscillations that can occur due
to noise on EN line. In the case that the EN function isn’t
required the EN pin should be tied directly to IN.
Reverse Current
The PMOS pass transistor has an inherent body diode
which will be forward biased in the case that VOUT > VIN.
Due to this fact in cases where the extended reverse current
condition is anticipated the device may require additional
external protection.
Output Current Limit
Output Current is internally limited within the IC to a
typical 379 mA. The NCP717 will source this amount of
current measured with the output voltage 100 mV lower
than the nominal VOUT. If the Output Voltage is directly
shorted to ground (VOUT = 0 V), the short circuit protection
will limit the output current to 390 mA (typ). The current
limit and short circuit protection will work properly up to
VIN =5.5 V at TA = 25°C. There is no limitation for the short
circuit duration.
Thermal Shutdown
When the die temperature exceeds the Thermal Shutdown
threshold (TSD − 160°C typical), Thermal Shutdown event
is detected and the device is disabled. The IC will remain in
this state until the die temperature decreases below the
Thermal Shutdown Reset threshold (TSDU − 140°C
typical). Once the IC temperature falls below the 140°C the
LDO is enabled again. The thermal shutdown feature
provides protection from a catastrophic device failure due to
accidental overheating. This protection is not intended to be
used as a substitute for proper heat sinking.
Power Dissipation
As power dissipated in the NCP717 increases, it might
become necessary to provide some thermal relief. The
maximum power dissipation supported by the device is
dependent upon board design and layout. Mounting pad
configuration on the PCB, the board material, and the
ambient temperature affect the rate of junction temperature
rise for the part. The maximum power dissipation the
NCP717 can handle is given by:
PD(MAX) +ƪ125 *TAƫ
qJA
(eq. 1)