TLE42744 Low Dropout Linear Voltage Regulator T LE42744DV50 T LE42744GV50 T LE42744EV50 T LE42744GV33 T LE42744DV33 T LE42744GSV33 Data Sheet Rev. 1.3, 2018-03-05 Automotive Power Low Dropout Linear Voltage Regulator 1 TLE42744 Overview Features * Very Low Current Consumption * Output Voltages 5 V and 3.3 V 2% * Output Current up to 400 mA * Very Low Dropout Voltage * Output Current Limitation * Reverse Polarity Protection * Overtemperature Shutdown * Wide Temperature Range From -40 C up to 150 C * Green Product (RoHS compliant) * AEC Qualified PG-TO252-3 PG-SSOP-14 exposed pad PG-TO263-3 PG-SOT223-4 Description The TLE42744 is a monolithic integrated low dropout voltage regulator for load currents up to 400 mA. An input voltage up to 40 V is regulated to VQ,nom = 5 V / 3.3 V with a precision of 2%. The device is designed for the harsh environment of automotive applications. Therefore it is protected against overload, short circuit and overtemperature conditions by the implemented output current limitation and the overtemperature shutdown circuit. The TLE42744 can be also used in all other applications requiring a stabilized 5 V / 3.3 V voltage. Due to its very low quiescent current the TLE42744 is dedicated for use in applications permanently connected to VBAT. Type Package Marking TLE42744DV50 PG-TO252-3 42744V5 TLE42744GV50 PG-TO263-3 42744V5 TLE42744EV50 PG-SSOP-14 exposed pad 42744V5 TLE42744DV33 PG-TO252-3 4274433 TLE42744GV33 PG-TO263-3 42744V33 TLE42744GSV33 PG-SOT223-4 427443 Data Sheet 2 Rev. 1.3, 2018-03-05 TLE42744 Block Diagram 2 Block Diagram Saturation Control and Protection Circuit Temperature Sensor Q Control Amplifier Buffer Bandgap Reference GND AEB01959 Figure 1 Data Sheet Block Diagram 3 Rev. 1.3, 2018-03-05 TLE42744 Pin Configuration 3 Pin Configuration 3.1 Pin Assignment PG-TO252-3, PG-TO263-3 and PG-SOT223-4 GND 4 GND 1 3 Q 1 I GND Q AEP02561 2 GND 3 Q PinConfig_PG-SOT2234.vsd AEP02281 Figure 2 Pin Configuration (top view) 3.2 Pin Definitions and Functions PG-TO252-3, PG-TO263-3 and PG-SOT223-4 Pin No. Symbol Function 1 I Input block to ground directly at the IC with a ceramic capacitor 2 GND Ground internally connected to heat slug 3 Q Output block to ground with a capacitor close to the IC terminals, respecting the values given for its capacitance and ESR in "Functional Range" on Page 6 4 / Heat Slug - Heat Slug internally connected to GND; connect to GND and heatsink area Data Sheet 4 Rev. 1.3, 2018-03-05 TLE42744 Pin Configuration 3.3 Pin Assignment PG-SSOP-14 exposed pad n.c. n.c. 1 14 2 13 n.c. I n.c. 3 12 n.c. GND 4 11 n.c. n.c. 5 10 n.c. n.c. 6 9 Q n.c. 7 8 n.c. TLE7274-2_PINCONFIG_SSOP14.SVG Figure 3 Pin Configuration (top view) 3.4 Pin Definitions and Functions PG-SSOP-14 exposed pad Pin No. Symbol Function 1, 2, 3, 5, 6, 7 n.c. Not connected can be open or connected to GND 4 GND Ground 8, 10, 11, 12, 14 n.c. Not connected can be open or connected to GND 9 Q Output block to ground with a capacitor close to the IC terminals, respecting the values given for its capacitance and ESR in "Functional Range" on Page 6 13 I Input block to ground directly at the IC with a ceramic capacitor Pad - Exposed Pad connect to GND and heatsink area Data Sheet 5 Rev. 1.3, 2018-03-05 TLE42744 General Product Characteristics 4 General Product Characteristics 4.1 Absolute Maximum Ratings Table 1 Absolute Maximum Ratings1) Tj = -40 C to 150 C; all voltages with respect to ground, (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. VI -42 - 45 V - P_4.1.1 VQ -1 - 40 V - P_4.1.2 Tj Tstg -40 - 150 C - P_4.1.3 -50 - 150 C - P_4.1.4 ESD Absorption VESD,HBM -4 - 4 kV Human Body Model (HBM)2) P_4.1.5 ESD Absorption VESD,CDM -1000 - 1000 V Charge Device Model (CDM)3) at all pins P_4.1.6 Input I Voltage Output Q Voltage Temperature Junction temperature Storage temperature ESD Susceptibility 1) not subject to production test, specified by design 2) ESD susceptibility Human Body Model "HBM" according to AEC-Q100-002 - JESD22-A114 3) ESD susceptibility Charged Device Model "CDM" according to ESDA STM5.3.1 Notes 1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as "outside" normal operating range. Protection functions are not designed for continuous repetitive operation. 4.2 Functional Range Table 2 Functional Range Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition Number Input voltage VI 5.5 - 40 V TLE42744DV50, TLE42744GV50, TLE42744EV50 P_4.2.1 Input voltage VI 4.7 - 40 V TLE42744GV33, TLE42744DV33, TLE42744GSV33 P_4.2.2 Data Sheet 6 Rev. 1.3, 2018-03-05 TLE42744 General Product Characteristics Table 2 Functional Range (cont'd) Parameter Symbol Values Min. Unit Note / Test Condition Number Typ. Max. Output Capacitor's Requirements for Stability CQ 22 - F 1) P_4.2.3 Output Capacitor's Requirements for Stability ESR(CQ) - 3 2) P_4.2.4 Junction temperature Tj -40 150 C - P_4.2.5 1) the minimum output capacitance requirement is applicable for a worst case capacitance tolerance of 30% 2) relevant ESR value at f = 10 kHz Note: Within the functional or operating range, the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the Electrical Characteristics table. 4.3 Thermal Resistance Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go to www.jedec.org. Table 3 Thermal Resistance Parameter Symbol Values Unit Note / Test Condition Number K/W measured to heat slug P_4.3.1 Min. Typ. Max. TLE42744DV50, TLE42744DV33 (PG-TO252-3) Junction to Case1) RthJC RthJA RthJA - Junction to Ambient1) Junction to Ambient1) Junction to Ambient 1) Junction to Ambient 1) 3.6 - 2) - 27 - K/W FR4 2s2p board P_4.3.2 - 115 - K/W FR4 1s0p board, footprint only3) P_4.3.3 RthJA - 52 - K/W FR4 1s0p board, 300 mm heatsink area3) P_4.3.4 RthJA - 40 - K/W FR4 1s0p board, 600 mm heatsink area3) P_4.3.5 3.6 - K/W measured to heat slug P_4.3.6 TLE42744GV50, TLE42744GV33 (PG-TO263-3) Junction to Case1) RthJC RthJA RthJA - Junction to Ambient1) Junction to Ambient1) Junction to Ambient 1) Junction to Ambient 1) Data Sheet 2) - 22 - K/W FR4 2s2p board - 74 - K/W FR4 1s0p board, footprint only3) P_4.3.8 RthJA - 42 - K/W FR4 1s0p board, 300 mm heatsink area3) P_4.3.9 RthJA - 34 - K/W FR4 1s0p board, 600 mm heatsink area3) P_4.3.10 7 P_4.3.7 Rev. 1.3, 2018-03-05 TLE42744 General Product Characteristics Table 3 Thermal Resistance (cont'd) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. TLE42744EV50 (PG-SSOP-14 exposed pad) Junction to Case1) RthJC - 7 - K/W measured to exposed pad P_4.3.11 Junction to Ambient1) RthJA RthJA - 43 - K/W FR4 2s2p board2) P_4.3.12 - 120 - K/W FR4 1s0p board, footprint only3) P_4.3.13 Junction to Ambient1) RthJA - 59 - K/W FR4 1s0p board, 300 mm heatsink area3) P_4.3.14 Junction to Ambient1) RthJA - 49 - K/W FR4 1s0p board, 600 mm heatsink area3) P_4.3.15 - 17 - K/W measured to heat slug P_4.3.16 - 54 - K/W FR4 2s2p board2) P_4.3.17 Junction to Ambient1) RthJC RthJA RthJA - 139 - K/W FR4 1s0p board, footprint only3) P_4.3.18 Junction to Ambient1) RthJA - 73 - K/W FR4 1s0p board, 300 mm heatsink area3) P_4.3.19 Junction to Ambient1) RthJA - 64 - K/W FR4 1s0p board, 600 mm heatsink area3) P_4.3.20 Junction to Ambient 1) TLE42744GSV33 (PG-SOT223-4) Junction to Case1) Junction to Ambient1) 1) Not subject to production test, specified by design. 2) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product (Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70m Cu, 2 x 35m Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer. 3) Specified RthJA value is according to Jedec JESD 51-3 at natural convection on FR4 1s0p board; The Product (Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm3 board with 1 copper layer (1 x 70m Cu). Data Sheet 8 Rev. 1.3, 2018-03-05 TLE42744 Electrical Characteristics 5 Electrical Characteristics 5.1 Electrical Characteristics Voltage Regulator Table 4 Electrical Characteristics VI =13.5 V; Tj = -40 C to 150 C; all voltages with respect to ground (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition Number Output Q Output Voltage VQ 4.9 5.0 5.1 V TLE42744DV50, TLE42744GV50, TLE42744EV50 5 mA < IQ< 400 mA 6 V < VI < 28 V P_5.1.1 Output Voltage VQ 4.9 5.0 5.1 V TLE42744DV50, TLE42744GV50, TLE42744EV50 5 mA < IQ<200 mA 6 V < VI < 40 V P_5.1.2 Output Voltage VQ 3.23 3.3 3.37 V TLE42744GV33, TLE42744DV33, TLE42744GSV33; 5 mA < IQ< 400 mA 4.7 V < VI < 28 V P_5.1.3 Output Voltage VQ 3.23 3.3 3.37 V TLE42744GV33, TLE42744DV33, TLE42744GSV33; 5 mA < IQ<200 mA 4.7 V < VI < 40 V P_5.1.4 Dropout Voltage Vdr - 250 500 mV TLE42744DV50, TLE42744GV50, TLE42744EV50 IQ = 250 mA Vdr = VI - VQ1) P_5.1.5 Load Regulation VQ, lo - 20 50 mV TLE42744DV50, TLE42744GV50, TLE42744EV50; IQ = 5 mA to 400 mA VI = 6 V P_5.1.6 Load Regulation VQ, lo - 40 70 mV TLE42744GV33, TLE42744DV33, TLE42744GSV33; IQ = 5 mA to 300 mA P_5.1.7 Line Regulation VQ, li - 10 25 mV Vl = 12 V to 32 V IQ = 5 mA P_5.1.8 Data Sheet 9 Rev. 1.3, 2018-03-05 TLE42744 Electrical Characteristics Table 4 Electrical Characteristics (cont'd) VI =13.5 V; Tj = -40 C to 150 C; all voltages with respect to ground (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number P_5.1.9 Min. Typ. Max. IQ PSRR 400 600 1100 mA 1) - 60 - dB fr = 100 Hz; Vr = 0.5 Vpp P_5.1.10 Temperature Output Voltage Drift dV Q ----------dT - 0.5 - mV/K - P_5.1.11 Overtemperature Shutdown Threshold Tj,sd 151 - 200 C Tj increasing2) P_5.1.12 Overtemperature Shutdown Threshold Hysteresis Tj,sdh - 25 - C Tj decreasing2) P_5.1.13 Iq - 100 220 A IQ = 1 mA P_5.1.14 Current Consumption Iq = II - IQ Iq - 8 15 mA IQ = 250 mA P_5.1.15 Current Consumption Iq = II - IQ Iq - 15 25 mA TLE42744DV50, TLE42744GV50, TLE42744EV50; IQ = 400 mA P_5.1.16 Iq - Output Current Limitation Power Supply Ripple Rejection 2) Current Consumption Quiescent Current Iq = II - IQ P_5.1.17 TLE42744GV33, TLE42744DV33, TLE42744GSV33; IQ = 400 mA 1) Measured when the output voltage VQ has dropped 100 mV from the nominal value obtained at VI = 13.5 V. Current Consumption Iq = II - IQ 20 30 mA 2) not subject to production test, specified by design Data Sheet 10 Rev. 1.3, 2018-03-05 TLE42744 Electrical Characteristics 5.2 Typical Performance Characteristics Voltage Regulator Current Consumption Iq versus Output Current IQ Current Consumption Iq versus Low Output Current IQ 16 01_IQ_IQ.VSD 02_IQ_IQLOW.VSD 1,4 14 1,2 V I = 13.5 V T j = 25 C 12 V I = 13.5 V T j = 25 C 1 I q [mA] I q [mA] 10 8 6 0,8 0,6 0,4 4 0,2 2 0 0 0 100 200 300 400 0 20 I Q [mA] 80 100 Dropout Voltage Vdr versus Output Current IQ (5 V versions only) 03_VQ_TJ.VSD 0,5 04_VDR_IQ.VSD 500 0,4 T j = 150 C 450 = 5 mA IQ V I = 13.5 V 0,3 T j = 25 C 400 0,2 350 0,1 300 V DR [mV] V Q [%] 60 I Q [mA] Output Voltage Variation VQ versus Junction Temperature TJ 0 -0,1 200 150 -0,3 100 -0,4 50 -0,5 T j = -40 C 250 -0,2 0 -40 0 40 80 120 0 150 100 200 300 400 I Q [mA] T j [C] Data Sheet 40 11 Rev. 1.3, 2018-03-05 TLE42744 Electrical Characteristics Dropout Voltage Vdr versus Junction Temperature (5 V versions only) Maximum Output Current IQ versus Input Voltage VI 05_VDR_TJ.VSD 500 450 800 400 I Q = 400 mA 350 300 IQ,max [mA] V DR [mV] 06_IQMAX_VI.VSD 900 250 200 I Q = 100 mA 150 700 T j = 25 C 600 T j = -40 C T j = 150 C 500 400 300 100 200 V Q = V Q,nom - 100 mV I Q = 10 mA 50 100 0 -40 0 40 80 120 0 160 0 T j [C] 10 20 30 40 V I [V] Region Of Stability: Output Capacitor's ESR ESR(CQ) versus Output Current IQ ESR(C Q ) [ ] 10 07_ESR_IQ.VSD Unstable Region 1 C Q = 22 F V I = 13.5 V Stable Region 0,1 0,01 0 100 200 300 400 I Q [mA] Data Sheet 12 Rev. 1.3, 2018-03-05 TLE42744 Application Information 6 Application Information Note: The following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. 6.1 Application Diagram Supply II Regulated I Q I Q Output Voltage Current Limitation DI <45V C I2 C I1 10F 100 nF CQ Bandgap Reference 22 F (ESR<3) Load ( e.g. Micro Controller) Temperature Shutdown GND GND Figure 4 Application Diagram 6.2 Selection of External Components 6.2.1 Input Pin The typical input circuitry for a linear voltage regulator is shown in the application diagram above. A ceramic capacitor at the input, in the range of 100 nF to 470 nF, is recommended to filter out the high frequency disturbances imposed by the line e.g. ISO pulses 3a/b. This capacitor must be placed very close to the input pin of the linear voltage regulator on the PCB. An aluminum electrolytic capacitor in the range of 10 F to 470 F is recommended as an input buffer to smooth out high energy pulses, such as ISO pulse 2a. This capacitor should be placed close to the input pin of the linear voltage regulator on the PCB. An overvoltage suppressor diode can be used to further suppress any high voltage beyond the maximum rating of the linear voltage regulator and protect the device against any damage due to over-voltage. The external components at the input are not mandatory for the operation of the voltage regulator, but they are recommended in case of possible external disturbances. 6.2.2 Output Pin An output capacitor is mandatory for the stability of linear voltage regulators. The requirement to the output capacitor is given in "Functional Range" on Page 6. The graph "Region Of Stability: Output Capacitor's ESR ESR(CQ) versus Output Current IQ" on Page 12 shows the stable operation range of the device. Data Sheet 13 Rev. 1.3, 2018-03-05 TLE42744 Application Information TLE42744 is designed to be stable with extremely low ESR capacitors. According to the automotive environment, ceramic capacitors with X5R or X7R dielectrics are recommended. The output capacitor should be placed as close as possible to the regulator's output and GND pins and on the same side of the PCB as the regulator itself. In case of rapid transients of input voltage or load current, the capacitance should be dimensioned in accordance and verified in the real application that the output stability requirements are fulfilled. 6.3 Thermal Considerations Knowing the input voltage, the output voltage and the load profile of the application, the total power dissipation can be calculated: (1) PD = ( VI - VQ ) x IQ + VI x Iq with * * * * * PD: continuous power dissipation VI: input voltage VQ: output voltage IQ: output current Iq: quiescent current The maximum acceptable thermal resistance RthJA can then be calculated: (2) T j, max - T a R thJA, max = --------------------------PD with * * Tj,max: maximum allowed junction temperature Ta: ambient temperature Based on the above calculation the proper PCB type and the necessary heat sink area can be determined with reference to the specification in "Thermal Resistance" on Page 7. Example Application conditions: VI = 13.5 V VQ = 5 V IQ = 250 mA Ta = 85 C Calculation of RthJA,max: PD = (VI - VQ) * IQ + VI * Iq = (13.5 V - 5 V) * 250 mA + 13.5 V * 15 mA = 2.125 W + 0.2025 W = 2.3275 W Data Sheet 14 Rev. 1.3, 2018-03-05 TLE42744 Application Information RthJA,max = (Tj,max - Ta) / PD = (150 C - 85 C) / 2.3275 W = 27.93 K/W As a result, the PCB design must ensure a thermal resistance RthJA lower than 27.93 K/W. By considering TLE42744GV50 (PG-TO263-3 package) and according to "Thermal Resistance" on Page 7, only the FR4 2s2p board is applicable. 6.4 Reverse Polarity Protection TLE42744 is self protected against reverse polarity faults and allows negative supply voltage. External reverse polarity diode is not needed. However, the absolute maximum ratings of the device as specified in "Absolute Maximum Ratings" on Page 6 must be kept. The reverse voltage causes several small currents to flow into the IC hence increasing its junction temperature. As the thermal shut down circuitry does not work in the reverse polarity condition, designers have to consider this in their thermal design. Data Sheet 15 Rev. 1.3, 2018-03-05 TLE42744 Package Outlines Package Outlines 6.5 +0.15 -0.05 A 0.15 MAX. per side B (5) 3x 0.75 0.1 0.5 +0.08 -0.04 2.28 4.57 0.5 +0.08 -0.04 0.9 +0.20 -0.01 0...0.15 0.8 0.15 (4.24) 1 0.1 9.98 0.5 6.22 -0.2 5.4 0.1 2.3 +0.05 -0.10 0.51 MIN. 7 0.1 B 0.25 M A B All metal surfaces tin plated, except area of cut. GPT09277 Figure 5 Data Sheet PG-TO252-3 16 Rev. 1.3, 2018-03-05 TLE42744 Package Outlines 4.4 10 0.2 1.27 0.1 B 0.1 A 8.5 1) 0.05 2.4 2.7 0.3 4.7 0.5 7.55 1) 9.25 0.2 (15) 1 0.3 0...0.3 0...0.15 0.75 0.1 0.5 0.1 1.05 8 MAX. 2.54 5.08 0.25 M A B 1) Typical All metal surfaces: tin plated, except area of cut. Metal surface min. x=7.25, y=6.9 Figure 6 Data Sheet 0.1 B GPT09362 PG-TO263-3 17 Rev. 1.3, 2018-03-05 TLE42744 0.35 x 45 6 x 0.65 = 3.9 0.25 0.05 2) 0.19 +0.06 0.1 H D 2x H 0.08 C SEATING PLANE 0.64 0.25 D 8 MAX. C 0.65 3.9 0.11) 1.7 MAX. 0.05 0.05 STAND OFF (1.45) Package Outlines 0.2 C 14x 6 0.2 0.15 M C A-B D 14x A 14 1 8 1 7 Index Marking 4.9 0.11) Exposed Diepad B 0.1 H A-B 2x 14 7 8 2.65 0.2 Bottom View 3 0.2 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Lead width can be 0.61 max. in dambar area Figure 7 Data Sheet PG-SSOP-14 exposed pad 18 Rev. 1.3, 2018-03-05 TLE42744 Package Outlines 1.60.1 6.5 0.2 3 0.1 A 0.1 MAX. B 1 0.25 M A 2 3 2.3 0.7 0.1 4.6 3.5 0.2 0.5 MIN. 7 0.3 4 0.28 0.04 0.25 M B 0...10 SOT223-PO V04 Figure 8 PG-SOT223-4 Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). For further information on alternative packages, please visit our website: http://www.infineon.com/packages. Data Sheet 19 Dimensions in mm Rev. 1.3, 2018-03-05 TLE42744 Revision History 8 Revision History Revision Date Changes 1.3 2018-03-05 Marking update in Chapter Overview (TLE42744GSV33 and TLE42744DV33) Updated Template on the last page. 1.2 2014-07-03 Application Information added. PG-TO252-3 and PG-SSOP-14 EP package outlines updated. 1.1 2010-01-13 Updated Version Data Sheet: version TLE42744EV50 in PG-SSOP-14 exposed pad and all related description added; 3.3V versions TLE42744GV33 in PG-TO263-3, TLE42744DV33 in PG-TO252-3 and TLE42744GSV33 in PG-SOT223-4 and all related description added 1.0 2009-01-14 Initial Version final Data Sheet Data Sheet 20 Rev. 1.3, 2018-03-05 Trademarks All referenced product or service names and trademarks are the property of their respective owners. Edition 2018-03-05 Published by Infineon Technologies AG 81726 Munich, Germany (c) 2018 Infineon Technologies AG. All Rights Reserved. Do you have a question about any aspect of this document? Email: erratum@infineon.com IMPORTANT NOTICE The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics ("Beschaffenheitsgarantie"). With respect to any examples, hints or any typical values stated herein and/or any information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. In addition, any information given in this document is subject to customer's compliance with its obligations stated in this document and any applicable legal requirements, norms and standards concerning customer's products and any use of the product of Infineon Technologies in customer's applications. The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of customer's technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this document with respect to such application. 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