SY89831U
Ultra-Precision 1:4 LVPECL Fanout
Buffer/Translator with Internal Termination
Precision Edge®
Precision Edge is a registered trademark of Micrel, Inc.
MicroLeadF ram e and MLF are registered trademarks of Amkor Technology, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
January
17, 2014
Revision 7.0
hbwhelp@micrel.com or (408) 955-1690
General Description
The SY89831U is a high-speed, 2GHz differential LVPECL
1:4 fanout buffer optim ized f or ultra-low skew applications.
Within-device skew is guaranteed to be less than 20ps
(5ps typ.) over supply voltage and temperature. The
differential input buffer has a unique internal termination
design that allows access to the termination network
through a VT pin. This feature allows the device to easily
interface to different logic standards. A VREF-AC
reference output is included for AC-coupled applications.
The SY89831U is a part of Micrel's high-speed clock
synchronization family. For applications that require a
different I/O combination, consult Micrel’s website at:
www.micrel.com, and choose from a comprehensive
product line of high-speed, low-skew fanout buffers,
translators, and clock generators.
Datasheets and support documentation are available on
Micrel’s web site at: www.micrel.com.
Precision Edge®
Features
• Guaranteed AC performance over temperature and
voltage
− DC-to 2.5GH z throu ghp ut (typical)
− 350ps propagation delay (IN-to-Q) (typical)
− 5ps within-device skew (typical)
− 150ps rise/f all t ime (typical)
• Ultra-low jitter design
− 62fs RMS phase jitter (typical)
• Unique patent -pending input termination and VT pin
accepts DC- and AC-coupled differential inputs
• 800mV, 100K LVPECL typical output swing
• Power supply 2.5V ±5% or 3.3V ±10%
• Industrial temperature range: –40°C to +85°C
• Availab le in 16-pin (3mm x 3mm) MLF® package
Applications
• Processor clock distribution
• SONET clock distribution
• Fibre Channel clock distribution
• Gigabit Ethernet clock distribution
Micrel, Inc.
SY89831U
January
17, 2014 2 Revision 7.0
hbwhelp@micrel.com or (408) 955-1690
Ordering Information(1)
Part Number Package Type Operating Range Package Marking Lead Finish
SY89831UMG
(2)
MLF-16 Industrial 831U with Pb-Free bar-line indicator NiPdAu Pb-Free
SY89831UMGTR
(2, 3)
MLF-16 Industrial 831U with Pb-Free bar-line indicator NiPdAu Pb-Free
Notes:
1. Contact f act ory for die availabi lity. Dice are guaranteed at TA = 25°C, DC electric als only.
2. Pb-Free package is recommended for new designs.
3. Tape and Reel.
Pin Configuration
16-MLF (MLF-16)
Pin Description
Pin # Pin Name Functional Description
15, 16
1, 2
3, 4
5, 6
Q0, /Q0
Q1, /Q1
Q2, /Q2
Q3, /Q3
Differential 100K LVPECL Outputs: These LVPECL outputs are the precision, low-skew copies of the
inputs. Please refer to the “Truth Table” sectio n for deta ils. Unuse d output pairs may be left open.
Terminate with 50Ω to VCC – 2V. See the “Output Termination Recommendations” section for more
details.
8 EN This single-ended TTL/CMOS-compati ble inp ut funct ion s as a synchronous output enabl e. The
synchronous enable ens ures that enable/disable only occurs when the outputs are in a logic low state.
Note that this input is internall y connected to a 25kΩ pull-up resistor and will defa ult t o logi c high stat e
(enabled) if left open.
9, 12 /IN, IN Differential Inputs: These input pai rs are the differential signal inputs to the device. Inputs accept AC-
or DC-coupled differential signs as small as 100mV. Each pin of a pair internally termina tes to a VT pin
through 50Ω. Note that these inputs default to an inter me diate state if left open. Please refer to the
“Input Interfac e App lic atio ns” section for more details.
10 VREF-AC Referenc e Voltage: These outputs bias to VCC – 1.4V. They are used when AC coupling the inputs
(IN, /IN). For AC-coupled applications, c onnect VREF-AC to the VT pin and bypass with a 0.01µF low-
ESR capacitor to VCC. See the “Input Interface Applications” sect ion for more deta il s. M ax imum
sink/source current is ±1.5mA. Due to the limited drive capabi li ty, each VREF-AC pin should only drive
its respective VT pin. If VREF-AC is used with a 2.5V s upply, make sure the input swing is large
enough to comply with the VIH
min. spe c.
Micrel, Inc.
SY89831U
January
17, 2014 3 Revision 7.0
hbwhelp@micrel.com or (408) 955-1690
Pin # Pin Name Functional Description
11 VT Input Termination Center-Tap: Each side of the differential input pair terminates to a VT pin. The VT
pins provide a center-tap to a termination network for m aximum interface flexibility. See the “Input
Interface Applications” section for more details.
13 GND Ground. GND pins and exposed pad must be connected to the most negative potential of the device
ground.
7, 14 VCC Positive Power Supply: Bypass with 0.1µF/0.01µF low-ESR capacit ors pla ced as close as pos sible to
each VCC pin.
Truth Table
IN /IN EN Q /Q
0 1 1 0 1
1 0 1 1 0
X
X
0 0(4) 1(4)
Note:
4. On the next negative transition of the input signal (IN).
Micrel, Inc.
SY89831U
January
17, 2014 4 Revision 7.0
hbwhelp@micrel.com or (408) 955-1690
Absolute Maximum Ratings(5)
Supply Voltage (VCC) ..................................... −0.5V to +4.0V
Input Voltage (VIN) ................................. −0.5V to VCC + 0.5V
LVPECL Output Current (IOUT)
Continuous ............................................................ 50mA
Surge .................................................................. 100mA
Input Current
Source or Sink Current on (IN,
/IN) ....................
±50mA
VREF-AC Current
Source or Sink Current on (IVT) ............................. ±2mA
Lead Temperature (soldering, 20s) ............................ 260°C
Storage Temperature (Ts) ......................... –65°C to +150°C
Operating Ratings(6)
Supply Voltage Range ......................... +2.375V to +2.625V
............................................................... +3.0V to +3.6V
Ambient Temperature (TA) .......................... –40°C to +85°C
Package Thermal Resistance(7)
(θJA) Still Air........................................................ 60°C/W
(θJA) Junction to Board ....................................... 32°C/W
DC Electrical Characteristics(8)
TA = –40°C to +85°C, unless otherwise noted.
Symbol Parameter Condition Min. Typ. Max. Units
V
CC
Power Supply 2.375
3.0 2.625
3.6 V
I
CC
Power Supply Current No load, max. VCC 47 70 mA
RIN Input Resistance (IN-to-VT) 45 50 55 Ω
RDIFF-IN Differential Input Resistance
(IN-to-/IN) 90 100 110 Ω
VIH Input HIGH Voltage (IN, /IN) 1.2
V
CC
V
VIL Input LO W Voltage (IN, /IN) 0 VIH – 0.1 V
VIN Input Voltage Swing (IN, /IN) See Figure 1. 0.1 1.7 V
VDIFF_IN Differential Input Voltage Swing
|IN – /IN| See Figure 2. 0.2 V
VREF–AC Output Reference Voltage
V
CC
– 1.525
V
CC
– 1.425
V
CC
– 1.325 V
LVTTL/LVCMOS Input DC Electrical Characteristics
VCC = 2.375V to 3.60V; VEE = 0V; TA = –40°C to +85°C
Symbol Parameter Condition Min. Typ. Max. Units
VIH Input HIGH Voltage 2.0 VCC V
VIL Input LO W Voltage 0 0.8 V
IIH Input HIGH Current –125 20 µA
IIL Input LO W Current –300 µA
Notes:
5. Permanent device dam age may occur if absolute maximum ratings are exceeded. This is a stre ss rating only and functi onal operati on is not implied
at conditions other than those det ailed in the operat i onal sections of this datas heet. Exposure to absolute maxim um rati ng conditi ons f or extended
periods may affect device reliability.
6. The datas heet limits are not guaranteed i f the device is operated beyond the operating ratings.
7. Package t hermal resist ance assumes the exposed pad is soldered (or equivalent) to the device’s most negative potential on the PCB. ΨJB and θJA
values are determined for a 4 -layer board at the still-air pack age thermal resistance, unless otherwise stated.
8. The ci rcuit is designed to meet the DC specifications shown in the above table after thermal equil i bri um has been established.
Micrel, Inc.
SY89831U
January
17, 2014 5 Revision 7.0
hbwhelp@micrel.com or (408) 955-1690
LVPECL Output DC Electrical Characteristics(8)
VCC = 2.5V ±5% or 3.3V ±10%; RL = 50Ω to VCC − 2V; TA = –40°C to + 85°C, unless otherwise noted.
Symbol Parameter Condition Min. Typ. Max. Units
VOH Output HIGH Voltage (Q, /Q) VCC – 1.145 VCC – 0.895 V
VOL Output LOW Voltage (Q, /Q) VCC – 1.945 VCC – 1.695 V
VOUT Output Voltage Swing (Q, /Q) See Figure 1. 550 800 mV
VDIFF_OUT Differential Output Voltage
Swing (Q, /Q) See Figure 2. 1100 1600 mV
LVTTL/LVCMOS DC Electrical Characteristics(8)
VCC = 2.5V ±5% or 3.3V ±10%; TA = –40°C to + 85°C, unless otherw ise note d.
Symbol Parameter Condition Min. Typ. Max. Units
VIH Input HIGH Voltage 2.0 VCC V
VIL Input LO W Voltage 0 0.8 V
IIH Input HIGH Current –125 30 µA
IIL Input LO W Current –300 µA
AC Electrical Characteristics(9)
VCC = 2.5V ±5% or 3.3V ±10%; RL = 50Ω to VCC − 2V; TA = –40°C to + 85°C, unless otherwise noted.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
fMAX Maximum Frequency VOUT ≥ 450mV 2.0 2.5 GHz
tpd Propagation
Delay IN-to-Q VIN ≥ 100mV 390 ps
IN-to-Q VIN ≥ 800mV 250 350 450 ps
tSKEW Within-Device Skew Note 10 5 20 ps
Part-to-Part Skew Note 11 150 ps
tS Set-Up Time EN to IN, /IN Note 12 300 ps
tH Hold Time EN to IN, /IN Note 12 300 ps
tJITTER RMS Phase Jitter Output = 622MH z
Integration Range 12kHz–20MHz 62
fs
tr, tf Output Rise/Fall Times
(20% to 80%) At full output swing 70 150 225 ps
Duty Cycle Freq. < 630MHz 48 50 52 %
Notes:
9. High-frequency AC parameters are guaranteed by design and characterizati on.
10. Within-device skew is measured between two different outputs under ident ical input trans iti ons.
11. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and no skew at the edges at the respective
inputs.
12. Set-up and hold times apply to synchronous applications that will enable/disabl e before the next clock cycle. For asynchronous appl ications, s et-up
and hold times do not apply.
Micrel, Inc.
SY89831U
January
17, 2014 6 Revision 7.0
hbwhelp@micrel.com or (408) 955-1690
Typical Phase Noise
-180.00
-170.00
-160.00
-150.00
-140.00
-130.00
-120.00
-110.00
-100.00
0.01 0.1 110 100
Phase Noise (dBc/Hz)
Offset Frequency (MHZ) Millions
SY89831U Phase Noise vs Frequency
3.3V, 622MHz, 12kHz-20MHz
Additive
-180.00
-170.00
-160.00
-150.00
-140.00
-130.00
-120.00
-110.00
-100.00
0.001 0.01 0.1 110 100
Phase Noise (dBc/Hz)
Offset Frequency (MHZ) Millions
SY89831U Phase Noise vs Frequency
3.3V, 156.25MHz, 12kHz-20MHz
Additive
Micrel, Inc.
SY89831U
January
17, 2014 11 Revision 7.0
hbwhelp@micrel.com or (408) 955-1690
Input Interface Applications
Figure 5. DC-Coupled LVPECL
Input Interface
Figure 6. AC-Coupled LVPECL
Input Interface
Figure 7. DC-Coupled CML
Input Interface
Figure 8. AC-Coupled CML
Input Interface
Figure 9. DC-Coupled LVDS
Input Interface
Figure 10. AC-Coupled LVDS
Input Interface
Micrel, Inc.
SY89831U
January
17, 2014 12 Revision 7.0
hbwhelp@micrel.com or (408) 955-1690
Output Termination Recommendations
Figure 11. Parallel Termination – Thevenin Equivalent
Note:
13. For +2.5V Systems: R1 = 250Ω, R2 = 62.5Ω.
Figure 12. Three-Resistor “Y-Termination”
Notes:
14. Power-saving alternat i ve t o Thevenin term i nation.
15. Plac e terminat i on resist ors as close to desti nation i nputs as possibl e.
16. The Rb resistor sets the DC bias voltage equal to Vt. For +2.5V systems, Rb = 19Ω.
17. C1 is an optional bypass capacitor that compensates for any tr/tf mismatches.
Micrel, Inc.
SY89831U
January
17, 2014 13 Revision 7.0
hbwhelp@micrel.com or (408) 955-1690
Related Product and Support Documentation
Part Number Function Data Sheet Link
SY89830U 1:4 LVPECL Fanout Buffer w/2:1 MUX Input http://www.micrel.com/index.php/en/products/clock-
timing/clock-data-distribution/fanout-buffers/article/51-
sy89830u.html
SY89832U 2.5V Ultra-Precision 1:4 LVDS Fanout
Buffer/ Translator with Internal Termination http://www.micrel.com/index.php/en/products/clock-
timing/clock-data-distribution/fanout-buffers/article/38-
sy89832u.html
SY89833AL 3 .3 V Ultra-Precision 1:4 LVDS Fanout
Buffer/Translator with Internal Termination http://www.micrel.com/index.php/en/products/clock-
timing/clock-data-distribution/fanout-buffers/article/39-
sy89833al.html
SY89834U 2.5/3.3V Two Input, 1GHz LVTTL/CMOS-to-
LVPECL 1:4 Fanout Buffer/Translator http://www.micrel.com/index.php/en/products/clock-
timing/clock-data-distribution/fanout-buffers/article/50-
sy89834u.html
16-MLF® Manufacturing Guidelines Exposed
Pad Application Note www.amkor.com/products/notes_papers/MLF_AppNote_0
301.pdf
Micrel, Inc.
SY89831U
January
17, 2014 14 Revision 7.0
hbwhelp@micrel.com or (408) 955-1690
Package Information(18)
PCB Thermal Consideration for 16-Pin MLF Package
(Always solder, or equival ent, the exposed pad to the PCB)
16-Pin EPAD MicroLeadFrame® (MLF-16)
Notes:
18. Package i nformat i on is correct as of the publication date. For updat es and most current inform ation, go to www.micrel.com.
19. Package m eets Level 2 moisture sensiti vity class ifi cation, and is shipped in dry-pack.
20. Exposed pads must be soldered to a ground for proper thermal management.
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TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
Micrel makes no represent ations or warranties with respec t t o the accuracy or completeness of the information furnis hed in t his data sheet. This
informat i on is not intended as a warranty and Micrel does not assume responsibilit y for its use. Micrel reserves the right to change circuitry,
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