VND830SP-E Double channel high-side driver Features Type RDS(on) IOUT VCC VND830SP-E 60 m(1) 6 A(1) 36 V 10 1 1. Per each channel. ECOPACK(R): lead free and RoHS compliant Automotive Grade: compliance with AEC guidelines Very low standby current CMOS compatible input On-state open-load detection Off-state open-load detection Thermal shutdown protection and diagnosis Undervoltage shutdown Overvoltage clamp Output stuck to VCC detection Load current limitation Reverse battery protection Electrostatic discharge protection Table 1. PowerSO-10 Description The VND830SP-E is a monolithic device made by using STMicroelectronicsTM VIPowerTM M0-3 technology, intended for driving any kind of load with one side connected to ground. Active VCC pin voltage clamp protects the device against low energy spikes (see ISO7637 transient compatibility table). Active current limitation combined with thermal shutdown and automatic restart protects the device against overload. The device detects open-load condition both is on-state and off-state. Output shorted to VCC is detected in the off-state. Device automatically turns-off in case of ground pin disconnection. Device summary Order codes Package PowerSO-10 February 2011 Tube Tape and reel VND830SP-E VND830SPTR-E Doc ID 10879 Rev 2 1/25 www.st.com 1 VND830SP-E Contents Contents 1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.4 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.5 Maximum demagnetization energy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1 4 6 3.1.1 Solution 1: a resistor in the ground line (RGND only) . . . . . . . . . . . . . . 18 3.1.2 Solution 2: a diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . 19 3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3 MCU I/O protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.4 Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.1 5 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 18 PowerSO-10 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.1 ECOPACK(R) packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.2 PowerSO-10 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.3 PowerSO-10 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Doc ID 10879 Rev 2 2/28 VND830SP-E List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 5 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Thermal data (per island) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Power output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 VCC - output diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Status pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Switching (VCC = 13 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Electrical transient requirements on VCC pin (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Electrical transient requirements on VCC pin (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Electrical transient requirements on VCC pin (part 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 PowerSO-10 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Doc ID 10879 Rev 2 3/28 VND830SP-E List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Status timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Switching time waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Off-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Status leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Status low output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Status clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 On-state resistance vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 On-state resistance vs VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Open-load on-state detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Open-load off-state detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Overvoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 ILIM vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 PowerSO-10 maximum turn-off current versus load inductance . . . . . . . . . . . . . . . . . . . . 17 Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 PowerSO-10 PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . 21 Thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Thermal fitting model of a double channel HSD in PowerSO-10 . . . . . . . . . . . . . . . . . . . . 22 PowerSO-10 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 PowerSO-10 suggested pad layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 PowerSO-10 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 PowerSO-10 tape and reel shipment (suffix "TR") . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Doc ID 10879 Rev 2 4/28 VND830SP-E 1 Block diagram and pin description Block diagram and pin description Figure 1. Block diagram Vcc Vcc CLAMP OVERVOLTAGE UNDERVOLTAGE CLAMP 1 GND OUTPUT1 INPUT1 DRIVER 1 CLAMP 2 STATUS1 CURRENT LIMITER 1 DRIVER 2 LOGIC OUTPUT2 OVERTEMP. 1 OPEN-LOAD ON 1 CURRENT LIMITER 2 INPUT2 OPEN-LOAD OFF 1 OPEN-LOAD ON 2 STATUS2 OPEN-LOAD OFF 2 OVERTEMP. 2 Figure 2. Configuration diagram (top view) OUTPUT 1 OUTPUT 1 N.C. OUTPUT 2 OUTPUT 2 5 4 3 6 7 8 9 10 GROUND INPUT 1 STATUS 1 STATUS 2 INPUT 2 2 1 11 VCC Table 2. Suggested connections for unused and not connected pins Connection / pin Status N.C. Output Input Floating X X X X To ground -- X -- Through 10 K resistor Doc ID 10879 Rev 2 5/28 VND830SP-E Electrical specifications 2 Electrical specifications 2.1 Absolute maximum ratings Stressing the device above the rating listed in Table 3 may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality document. Table 3. Absolute maximum ratings Symbol Parameter Value Unit 41 V VCC DC supply voltage -VCC Reverse DC supply voltage -0.3 V -IGND DC reverse ground pin current -200 mA IOUT DC output current Internally limited A -IOUT Reverse DC output current -6 A IIN DC input current +/-10 mA ISTAT DC status current +/-10 mA VESD Electrostatic discharge (Human Body Model: R = 1.5 K; C = 100 pF) - INPUT - STATUS - OUTPUT - VCC 4000 4000 5000 5000 V V V V EMAX Maximum switching energy (L = 1.8 mH; RL = 0 ; Vbat = 13.5 V; Tjstart = 150 C; IL = 9 A) 100 mJ Power dissipation TC = 25 C 73.5 W Internally limited C Ptot Tj Junction operating temperature Tc Case operating temperature -40 to 150 C Storage temperature -55 to 150 C Tstg Doc ID 10879 Rev 2 6/28 VND830SP-E Electrical specifications 2.2 Thermal data Table 4. Thermal data (per island) Symbol Parameter Rthj-case Thermal resistance junction-case Rthj-amb Thermal resistance junction-ambient Value Unit 1.7 C/W 51.7(1) 37(2) C/W 2 1. When mounted on a standard single-sided FR-4 board with 0.5 cm of Cu (at least 35 m thick). Horizontal mounting and no artificial air flow. 2. When mounted on a standard single-sided FR-4 board with 6 cm2 of Cu (at least 35 m thick). Horizontal mounting and no artificial air flow. 2.3 Electrical characteristics Values specified in this section are for 8 V < VCC < 36 V; -40 C < Tj < 150 C, unless otherwise stated. (Per each channel) Figure 3. Current and voltage conventions IS VF1 (1) IIN1 INPUT 1 ISTAT1 VIN1 IOUT1 OUTPUT 1 STATUS 1 VSTAT1 IIN2 VOUT1 INPUT 2 VIN2 VCC VCC IOUT2 ISTAT2 OUTPUT 2 STATUS 2 VSTAT2 VOUT2 GND IGND 1. VFn = VCCn - VOUTn during reverse battery condition. Table 5. Power output Symbol Parameter VCC(1) VUSD(1) VOV(1) RON Min. Typ. Operating supply voltage 5.5 13 36 V Undervoltage shutdown 3 4 5.5 V Overvoltage shutdown 36 On-state resistance Test conditions Max. Unit V IOUT = 2 A; Tj = 25 C 60 m IOUT = 2 A; VCC > 8 V 120 m Doc ID 10879 Rev 2 7/28 VND830SP-E Electrical specifications Table 5. Power output (continued) Symbol IS(1) Parameter Test conditions Supply current Min. Typ. Max. Unit Off-state; VCC = 13 V; VIN = VOUT = 0 V 12 40 A Off-state; VCC = 13 V; VIN = VOUT = 0 V; Tj = 25C 12 25 A On-state; VCC = 13 V 5 7 mA 0 50 A -75 0 A IL(off1) Off-state output current VIN = VOUT = 0 V; VCC = 36 V; Tj = 125 C IL(off2) Off-state output current VIN = 0 V; VOUT = 3.5 V IL(off3) Off-state output current VIN = VOUT = 0 V; VCC = 13 V; Tj = 125 C 5 A IL(off4) Off-state output current VIN = VOUT = 0 V; VCC = 13 V; Tj = 25 C 3 A 1. Per device. Table 6. Symbol Protections(1) Min. Typ. Max. Unit Shutdown temperature 150 175 200 C TR Reset temperature 135 Thyst Thermal hysteresis 7 tSDL Status delay in overload Tj > TTSD conditions Ilim Current limitation TTSD Vdemag Parameter Test conditions VCC = 13 V C 15 6 C 9 5.5 V < VCC < 36 V Turn-off output clamp voltage IOUT = 2 A; L = 6 mH VCC - 41 20 s 15 A 15 A VCC - 48 VCC - 55 V 1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles. Table 7. Symbol VF Table 8. Symbol VCC - output diode Parameter Test conditions Forward on voltage -IOUT = 1.3 A; Tj = 150 C Min. Typ. Max. Unit -- -- 0.6 V Status pin Parameter Test conditions Min. Typ. Max. Unit VSTAT Status low output voltage ISTAT = 1.6 mA 0.5 V ILSTAT Status leakage current Normal operation; VSTAT = 5 V 10 A CSTAT Status pin input capacitance Normal operation; VSTAT = 5 V 100 pF Doc ID 10879 Rev 2 8/28 VND830SP-E Electrical specifications Table 8. Symbol VSCL Table 9. Symbol Status pin (continued) Parameter Test conditions Min. Typ. Max. ISTAT = 1 mA Status clamp voltage 6 ISTAT = -1 mA 6.8 8 -0.7 Unit V V Switching (VCC = 13 V) Parameter Test conditions Min. Typ. Max. Unit td(on) Turn-on delay time RL = 6.5 from VIN rising edge to VOUT = 1.3 V -- 30 -- s td(off) Turn-off delay time RL = 6.5 from VIN falling edge to VOUT = 11.7 V -- 30 -- s dVOUT/dt(on) Turn-on voltage slope RL = 6.5 from VOUT = 1.3 V to VOUT = 10.4 V -- See Figure 21 -- V/s dVOUT/dt(off) Turn-off voltage slope RL = 6.5 from VOUT = 11.7 V to VOUT = 1.3 V -- See Figure 22 -- V/s Typ. Max. Unit 100 200 mA 200 s 3.5 V 1000 s Max. Unit 1.25 V Table 10. Open-load detection Symbol Parameter Test conditions IOL Open-load on-state detection VIN = 5 V threshold tDOL(on) Open-load on-state detection IOUT = 0 A delay VOL tDOL(off) Table 11. Symbol Open-load off-state voltage detection threshold 50 VIN = 0 V 1.5 2.5 Open-load detection delay at turn-off Logic input Parameter Test conditions VIL Input low level IIL Low level input current VIH Input high level IIH High level input current VI(hyst) Input hysteresis voltage VICL Min. Input clamp voltage VIN = 1.25 V Min. Typ. 1 A 3.25 V VIN = 3.25 V 10 0.5 IIN = 1 mA IIN = -1 mA Doc ID 10879 Rev 2 6 A V 6.8 -0.7 8 V V 9/28 VND830SP-E Electrical specifications Figure 4. Status timings OPEN LOAD STATUS TIMING (with external pull-up) IOUT < IOL VOUT > VOL VINn OVER TEMP STATUS TIMING Tj > TTSD VINn VSTATn VSTATn tSDL tDOL(off) Table 12. tSDL tDOL(on) Truth table Conditions Input Output Sense Normal operation L H L H H H Current limitation L H H L X X Overtemperature L H L L H L Undervoltage L H L L X X Overvoltage L H L L H H Output voltage > VOL L H H H L H Output current < IOL L H L H H L Doc ID 10879 Rev 2 H (Tj < TTSD) H (Tj > TTSD) L 10/28 VND830SP-E Figure 5. Electrical specifications Switching time waveforms Doc ID 10879 Rev 2 11/28 VND830SP-E Electrical specifications Table 13. Electrical transient requirements on VCC pin (part 1) ISO T/R Test levels 7637/1 test pulse I II III IV Delays and impedance 1 -25 V -50 V -75 V -100 V 2 ms, 10 2 +25 V +50 V +75 V +100 V 0.2 ms, 10 3a -25 V -50 V -100 V -150 V 0.1 s, 50 3b +25 V +50 V +75 V +100 V 0.1 s, 50 4 -4 V -5 V -6 V -7 V 100 ms, 0.01 5 +26.5 V +46.5 V +66.5 V +86.5 V 400 ms, 2 Table 14. Electrical transient requirements on VCC pin (part 2) ISO T/R Test levels results 7637/1 test pulse I II III IV 1 C C C C 2 C C C C 3a C C C C 3b C C C C 4 C C C C 5 C E E E Table 15. Electrical transient requirements on VCC pin (part 3) Class Contents C All functions of the device are performed as designed after exposure to disturbance. E One or more functions of the device is not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device. Doc ID 10879 Rev 2 12/28 VND830SP-E Electrical specifications Figure 6. Waveforms NORMAL OPERATION INPUTn OUTPUT VOLTAGEn STATUSn UNDERVOLTAGE VUSDhyst VCC VUSD INPUTn OUTPUT VOLTAGEn STATUSn undefined OVERVOLTAGE VCC<VOV VCC > VOV VCC INPUTn OUTPUT VOLTAGEn STATUSn OPEN-LOAD with external pull-up INPUTn VOUT > VOL OUTPUT VOLTAGEn VOL STATUSn OPEN-LOAD without external pull-up INPUTn OUTPUT VOLTAGEn STATUSn Tj TTSD TR OVERTEMPERATURE INPUTn OUTPUT CURRENTn STATUSn Doc ID 10879 Rev 2 13/28 VND830SP-E Electrical specifications 2.4 Electrical characteristics curves Figure 7. Off-state output current Figure 8. IL(off1) (uA) High level input current Iih (uA) 2.5 5 2.25 4.5 Off state Vcc=36V Vin=Vout=0V 2 1.75 Vin=3.25V 4 3.5 1.5 3 1.25 2.5 1 2 0.75 1.5 0.5 1 0.25 0.5 0 0 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 Tc (C) Figure 9. 50 75 100 125 150 175 Tc (C) Input clamp voltage Figure 10. Status leakage current Vicl (V) Ilstat (uA) 8 0.05 7.8 Iin=1mA 7.6 0.04 7.4 Vstat=5V 7.2 0.03 7 6.8 0.02 6.6 6.4 0.01 6.2 6 -50 -25 0 25 50 75 100 125 150 175 0 -50 Tc (C) Figure 11. -25 0 25 50 75 100 125 150 175 Tc (C) Status low output voltage Figure 12. Status clamp voltage Vstat (V) Vscl (V) 0.8 8 0.7 7.8 Istat=1.6mA Istat=1mA 7.6 0.6 7.4 0.5 7.2 0.4 7 0.3 6.8 6.6 0.2 6.4 0.1 6.2 0 6 -50 -25 0 25 50 75 100 125 150 175 Tc (C) -50 -25 0 25 50 75 100 125 150 175 Tc (C) Doc ID 10879 Rev 2 14/28 VND830SP-E Electrical specifications Figure 13. On-state resistance vs Tcase Figure 14. On-state resistance vs VCC Ron (mOhm) Ron (mOhm) 120 160 Tc=150C 110 140 100 Iout=2A Vcc=8V; 13V & 36V 120 90 80 100 70 60 80 Tc=25C 50 60 40 Tc= - 40C 30 40 20 20 Iout=5A 10 0 0 -50 -25 0 25 50 75 100 125 150 5 175 10 15 Figure 15. Open-load on-state detection threshold Iol (mA) 20 25 30 35 40 Vcc (V) Tc (C) Figure 16. Open-load off-state detection threshold Vol (V) 150 5 140 4.5 Vcc=13V Vin=5V 130 Vin=0V 4 120 3.5 110 3 100 2.5 90 2 80 1.5 70 1 60 0.5 0 50 -50 -25 0 25 50 75 100 125 150 -50 175 -25 0 25 50 75 100 125 150 175 Tc (C) Tc (C) Figure 17. Input high level Figure 18. Input low level Vih (V) Vil (V) 3.6 2.6 2.4 3.4 2.2 3.2 2 3 1.8 2.8 1.6 2.6 1.4 2.4 1.2 2.2 1 -50 -25 0 25 50 75 100 125 150 175 -50 Tc (C) -25 0 25 50 75 100 125 150 175 Tc (C) Doc ID 10879 Rev 2 15/28 VND830SP-E Electrical specifications Figure 19. Input hysteresis voltage Figure 20. Overvoltage shutdown Vov (V) Vhyst (V) 50 1.5 48 1.4 46 1.3 44 1.2 42 1.1 40 1 38 0.9 36 0.8 34 0.7 32 0.6 30 0.5 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 Tc (C) Figure 21. Turn-on voltage slope 125 150 175 dVout/dt(off) (V/ms) 600 800 550 Vcc=13V Rl=6.5Ohm 600 100 Figure 22. Turn-off voltage slope dVout/dt(on) (V/ms) 700 75 Tc (C) Vcc=13V Rl=6.5Ohm 500 450 500 400 400 350 300 300 200 250 100 200 0 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175 Tc (C) Tc (C) Figure 23. ILIM vs Tcase Ilim (A) 20 18 Vcc=13V 16 14 12 10 8 6 4 2 0 -50 -25 0 25 50 75 100 125 150 175 Tc (C) Doc ID 10879 Rev 2 16/28 VND830SP-E 2.5 Electrical specifications Maximum demagnetization energy Figure 24. PowerSO-10 maximum turn-off current versus load inductance I LM AX (A) 100 10 A C B 1 0,1 1 10 100 L(mH) A = single pulse at TJstart = 150 C B= repetitive pulse at TJstart = 100 C C= repetitive pulse at TJstart = 125 C Conditions: VCC= 13.5 V VIN, IL Demagnetization Demagnetization Demagnetization t Note: Values are generated with RL = 0 . In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves B and C. Doc ID 10879 Rev 2 17/28 VND830SP-E 3 Application schematic Application schematic Figure 25. Application schematic +5V +5V +5V VCC Rprot STATUS1 Dld C Rprot INPUT1 OUTPUT1 Rprot STATUS2 Rprot INPUT2 OUTPUT2 GND RGND VGND 3.1 DGND GND protection network against reverse battery This section provides two solutions for implementing a ground protection network against reverse battery. 3.1.1 Solution 1: a resistor in the ground line (RGND only) This can be used with any type of load. The following show how to dimension the RGND resistor: 1. RGND 600 mV / IS(on)max 2. RGND (-VCC) / (-IGND) where -IGND is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device datasheet. Power dissipation in RGND (when VCC < 0 during reverse battery situations) is: PD = (-VCC)2/ RGND This resistor can be shared amongst several different HSDs. Please note that the value of this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the maximum on-state currents of the different devices. Doc ID 10879 Rev 2 18/28 VND830SP-E Application schematic Please note that, if the microprocessor ground is not shared by the device ground, then the RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output values. This shift will vary depending on how many devices are ON in the case of several high-side drivers sharing the same RGND. If the calculated power dissipation requires the use of a large resistor, or several devices have to share the same resistor, then ST suggests using solution 2 below. 3.1.2 Solution 2: a diode (DGND) in the ground line A resistor (RGND = 1 k) should be inserted in parallel to DGND if the device will be driving an inductive load. This small signal diode can be safely shared amongst several different HSD. Also in this case, the presence of the ground network will produce a shift (j600mV) in the input threshold and the status output values if the microprocessor ground is not common with the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network. Series resistor in INPUT and STATUS lines are also required to prevent that, during battery voltage transient, the current exceeds the Absolute Maximum Rating. Safest configuration for unused INPUT and STATUS pin is to leave them unconnected. 3.2 Load dump protection Dld is necessary (voltage transient suppressor) if the load dump peak voltage exceeds the VCC maximum DC rating. The same applies if the device is subject to transients on the VCC line that are greater than those shown in the ISO T/R 7637/1 table. 3.3 MCU I/O protection If a ground protection network is used and negative transients are present on the VCC line, the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to prevent the microcontroller I/O pins from latching up. The value of these resistors is a compromise between the leakage current of microcontroller and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of microcontroller I/Os: -VCCpeak / Ilatchup Rprot (VOHC - VIH - VGND) / IIHmax Example For the following conditions: VCCpeak = -100 V Ilatchup 20 mA VOHC 4.5 V 5 k Rprot 65 k. Recommended values are: Rprot = 10 k Doc ID 10879 Rev 2 19/28 VND830SP-E 3.4 Application schematic Open-load detection in off-state Off-state open load detection requires an external pull-up resistor (RPU) connected between OUTPUT pin and a positive supply voltage (VPU) like the +5V line used to supply the microprocessor. The external resistor has to be selected according to the following requirements: 1. no false open load indication when load is connected: in this case we have to avoid VOUT to be higher than VOlmin; this results in the following condition VOUT = (VPU / (RL + RPU))RL < VOlmin. 2. no misdetection when load is disconnected: in this case the VOUT has to be higher than VOLmax; this results in the following condition RPU < (VPU - VOLmax) / IL(off2). Because IS(OFF) may significantly increase if Vout is pulled high (up to several mA), the pullup resistor RPU should be connected to a supply that is switched OFF when the module is in standby. Figure 26. Open-load detection in off-state Doc ID 10879 Rev 2 20/28 VND830SP-E Package and PCB thermal data 4 Package and PCB thermal data 4.1 PowerSO-10 thermal data Figure 27. PowerSO-10 PC board Note: Layout condition of Rth and Zth measurements (PCB FR4 area = 58 mm x 58 mm, PCB thickness = 2 mm, Cu thickness = 35 m, Copper areas: from minimum pad lay-out to 8 cm2). Figure 28. Rthj-amb vs PCB copper area in open box free air condition Doc ID 10879 Rev 2 21/28 VND830SP-E Package and PCB thermal data Figure 29. Thermal impedance junction ambient single pulse Equation 1: pulse calculation formula Z TH = R TH + Z THtp ( 1 - ) where = tp T Figure 30. Thermal fitting model of a double channel HSD in PowerSO-10 Tj_1 C1 C2 C3 C4 C5 C6 R1 R2 R3 R4 R5 R6 Pd1 Tj_2 C1 C2 R1 R2 Pd2 T_amb Doc ID 10879 Rev 2 22/28 VND830SP-E Table 16. Package and PCB thermal data Thermal parameters Area / island (cm2) Footprint R1 (C/W) 0.15 R2 (C/W) 0.8 R3 (C/W) 0.7 R4 (C/W) 0.8 R5 (C/W) 12 R6 (C/W) 37 C1 (W.s/C) 0.0006 C2 (W.s/C) 2.1E-03 C3 (W.s/C) 0.013 C4 (W.s/C) 0.3 C5 (W.s/C) 0.75 C6 (W.s/C) 3 Doc ID 10879 Rev 2 6 22 5 23/28 VND830SP-E Package and packing information 5 Package and packing information 5.1 ECOPACK(R) packages In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. 5.2 PowerSO-10 package information Figure 31. PowerSO-10 package dimensions B 0.10 A B 10 H E E E2 1 SEATING PLANE e B DETAIL "A" A C 0.25 h E4 D = D1 = = = SEATING PLANE A F A1 A1 L DETAIL "A" Doc ID 10879 Rev 2 24/28 VND830SP-E Package and packing information Table 17. PowerSO-10 mechanical data mm. DIM. Min. Typ. Max. A 3.35 3.65 A(1) 3.4 3.6 A1 0 0.10 B 0.40 0.60 B(1) 0.37 0.53 C 0.35 0.55 C(1) 0.23 0.32 D 9.40 9.60 D1 7.40 7.60 E 9.30 9.50 E2 7.20 7.60 E2(1) 7.30 7.50 E4 5.90 6.10 E4(1) 5.90 6.30 e 1.27 F 1.25 1.35 F(1) 1.20 1.40 H 13.80 14.40 H(1) 13.85 14.35 h 0.50 L 1.20 1.80 L(1) 0.80 1.10 0 8 (1) 2 8 1. Muar only POA P013P. Doc ID 10879 Rev 2 25/28 VND830SP-E 5.3 Package and packing information PowerSO-10 packing information Figure 32. PowerSO-10 suggested Figure 33. PowerSO-10 tube shipment pad layout (no suffix) B CASABLANCA MUAR C C A A B All dimensions are in mm. Casablanca Muar Base Q.ty Bulk Q.ty Tube length ( 0.5) A B C ( 0.1) 50 1000 532 10.4 16.4 0.8 50 1000 532 4.9 17.2 0.8 Figure 34. PowerSO-10 tape and reel shipment (suffix "TR") Reel dimensions Base Q.ty Bulk Q.ty A (max) B (min) C ( 0.2) F G (+ 2 / -0) N (min) T (max) 600 600 330 1.5 13 20.2 24.4 60 30.4 Tape dimensions According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing W P0 ( 0.1) P D ( 0.1/-0) D1 (min) F ( 0.05) K (max) P1 ( 0.1) All dimensions are in mm. 24 4 24 1.5 1.5 11.5 6.5 2 End Start Top cover tape No components Components No components 500mm min Empty components pockets saled with cover tape. 500mm min User direction of feed Doc ID 10879 Rev 2 26/28 VND830SP-E 6 Revision history Revision history Table 18. Document revision history Date Revision Changes 01-Oct-2004 1 Initial release. 07-Feb-2011 2 Document reformatted and restructured. Updated Features list. Updated Table 16: Thermal parameters Doc ID 10879 Rev 2 27/28 VND830SP-E Please Read Carefully: Information in this document is provided solely in connection with ST products. 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The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. (c) 2011 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com Doc ID 10879 Rev 2 28/28