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©2005 Fairchild Semiconductor Corporation
www.fairchildsemi.com
Rev.1.0.0
FPS
TM
is a trademark of Fai rchild Semiconductor Corporation
Features
• Internal Avalanche Rugged SenseFET
• Advanced Burst-Mode Operation Consumes Under One
W at 240VAC & 0.5W Load
• Precision Fixed Operating Fr equency (66kHz)
• Internal Star t-up Circuit
• Improved Pulse by Pulse Current Limiting
• Over Voltage Protection (OVP) : Auto-Restart
• Over Load Pr otectio n (OLP): Auto-Restart
• Internal Thermal Shutdown (TSD) : Auto-Restart
• Under Voltage Lock Out (UVLO) with Hysteresis
• Low Operating Current (2.5mA)
• Built-in Soft Start
Application
• SMPS for LCD monitor and STB
•Adapter
Related Application Notes
•AN4137 - Design Guidelines for Off-line Flyback
Converters Using Fairchild Power Switch (FPS)
•AN4140 - T ra n sf ormer Design Considerati o n f or O ff-line
Flyback Converters Using Fairchild Power Switch
•AN4141 - Troubleshooting and Design Tips for Fairchild
Power Switch Flyback Applications
•AN4148 - Audible Noise Reduction Techniques for FPS
Applications
Description
The FSDM0465RB is an integrated Pulse Width Modulator
(PWM) and Sen se FET specifically designed for high
performance of fline Switch Mode Power Supplies (SMPS)
with minimal external components. This device is an
integrated high voltage power switching regulator which
combines a rugged avalanche, SenseFET with a current mode
PWM control block. The PWM cont roller incl ud e s integrated
fixed frequency oscillator , under voltage lockout , leading edge
blanking (LEB), optimized gate driver , internal soft start,
temperature co mpensated precise current sources for a loop
compensation and self protection circuitry . Compared with a
discrete MOSFET and PWM controller solution, the PWM/
FSDMRB can reduce total cost, component count, size and
weigh, while simultaneously increasing efficiency , productivity ,
and system reliability. This device provides a basic platform
well suited for cost-effective designs of flyback converters.
Table 1. Maximum Output Power
Notes:
1. Typical continuous power in a non-ventilated enclosed
adapter measured at 50°C ambient.
2. Maximum practical continuous power in an open frame
desi gn at 50°C ambient.
3. 230 VAC or 100/115 VA C with doubler.
4. The junction temperature can limit the maximum output
power.
Typical Circuit
Figu re 1. Typic al Flyback Appl ic a t ion
OUTPUT POWER TABLE (4)
PRODUCT 230VAC ±15%
(3)
85-265VAC
Adapt-
er
(1)
Open
Frame
(2)
Adapt-
er
(1)
Open
Frame
(2)
FSDM0465RB 48W 56W 40W 48W
FSDM0565RB 60W 70W 50W 60W
FSDM07652RB 70W 80W 60W 70W
FSDM12652RB 90W 110W 80W 90W
Drain
Source
Vstr
Vfb Vcc
PWM
AC
IN DC
OUT
FSDM0465RB
Green Mode Fairchild P ower Switch (FPS
TM
)
FSDM0465RB
2
Internal Block Diagram
Figure 2. Functional Block Diagram of FSDM0465RB
8V/12V
3 1
2
4
5
Vref Internal
Bias
S
Q
Q
R
OSC
Vcc Vref
Idelay IFB
V
SD
TSD
Vovp
Vcc
V
CL
S
Q
Q
R
R
2.5R
Vcc good
Vcc Drain
N.C
V
FB
GND
Gate
driver
6
Vstr
I
CH
Vcc good
0.5/0.7V
LEB
PWM
Soft start
+
-
Vcc Good
FSDM0465RB
3
Pin Description
Pin Assignments
Figure 3. Pin Configuration (Top View)
Pin Number Pin Name Pin Function Description
1Drain
This pin is the high v oltage power SenseFET drain. It is designed to dr iv e the
transformer directly.
2 GND This pin is the control ground and the SenseFET source.
3Vcc
This pin is the pos itive supply voltage input. During start up, the power is sup-
plied by an internal high voltage current source that is connected to the Vstr pin.
When Vcc reaches 12V, the internal high volt age current source is disabled and
the power is supplied from the auxiliary transformer winding.
4Vfb
This pin is internally connected to the inverting input of the PWM comparator.
The collector of an opto-coupler is typically tied to this pin. For stable operation,
a capac itor should be placed between this pin and GND. If the voltage of this pin
reaches 6.0V, the over load protection is activated resulting in shutdown of the
FPSTM.
5N.C-
6Vstr
This pin is connected directly to the high volt age DC link. At startup, the internal
high voltage current source supplies internal bias and charges the external ca-
pacitor that is connected to the Vcc pin. Once Vcc reaches 12V, the internal cur-
rent source is disabled.
6.Vstr
5.N.C.
4.Vfb
3.Vcc
2.GND
1.Drain
TO-220F-6L
FSDM0465RB
4
Absolute Maximum Ratings
(Ta=25°C, unless otherwise specified)
Notes:
1. Repetitive Rating: Pulse width limited by maximum junction temperature
2. Tc: Case Back Surface Temperature (With infinite heat sink)
3. T
DL
: Drain Lead Temperature (With infinite heat sink)
4. L=14mH, starting Tj=25°C2. L=14mH, starting Tj=25°C
Thermal Impedance
Notes:
1. Infinite cooling condition - refer to the SEMI G30-88.
Parameter Symbol Value Unit
Drain-source Voltage V
DSS
650 V
Vstr Max Voltage V
STR
650 V
Pulsed Drain Current (Tc=25
°C)
(1) I
DM
9.6 A
Continuous Drain Current (Tc=25
°C)
(2) I
D
2.2 A (rms)
Continuous Drain Current (Tc=100
°C)
(2) 1.4 A (rms)
Continuous Drain Current* (T
DL
=25
°C)
(3) I
D
*4 A (rms)
Single Pulsed Avalanche Energy (4) E
AS
-mJ
Supply Voltage V
CC
20 V
Input Voltage Range V
FB
-0.3 to V
CC
V
Total Power Dissipation (Tc=25
°C)
(2) P
D
33 W
Operating Junction Temperature T
j
Internally limited °C
Operating Ambient Temperature T
A
-25 to +85 °C
Storage Temperature Range T
STG
-55 to +150 °C
ESD Capability, HBM Model (All pins
except Vstr and Vfb)
-
2.0
(GND-Vstr/Vfb=1.5kV) kV
ESD Capability, Machine Model (All pins
except Vstr and Vfb)
-
300
(GND-Vstr/Vfb=225V) V
Parameter Symbol Value Unit
Junction-to-Ambient Thermal
θ
JA
-°C/W
Junction-to-Case Thermal
θ
JC
(1) 3.78 °C/W
FSDM0465RB
5
Electrical Characteristics
(Ta = 25°C unless otherwise specified)
Parameter Symbol Condition Min. Typ. Max. Unit
SenseFET SECTION
Drain Source Breakdown Voltage BV
DSS
V
GS
= 0V, I
D
= 250µA 650 - - V
Zero Gate Voltage Drain Current I
DSS
V
DS
= 650V, V
GS
= 0V - - 250 µA
V
DS
= 520V
V
GS
= 0V, T
C
= 125°C- - 250 µA
Static Drain Source On Resistance (1) R
DS(ON)
V
GS
= 10V, I
D
= 2.5A - 2.2 2.6
Ω
Output Capacitance C
OSS
V
GS
= 0V, V
DS
= 25V,
f = 1MHz -60-pF
Turn On Delay Time T
D(ON)
V
DD
= 325V, I
D
= 3.2A - 23 -
ns
Rise Time T
R
-20-
Turn Off Delay Time T
D(OFF)
-65-
Fall Time T
F
-27-
CONTROL SECTION
Initial Frequency F
OSC
V
FB
= 3V 60 66 72 kHz
Voltage Stability F
STABLE
13V ≤ Vcc ≤ 18V 0 1 3 %
Temperature Stability (2) ∆F
OSC
-25°C ≤ Ta ≤ 85°C0±5±10%
Maximum Duty Cycle DMAX -778287%
Minimum Duty Cycle DMIN ---0%
Start Threshold Voltage V
START
V
FB
=GND 11 12 13 V
Stop Threshold Voltage V
STOP
V
FB
=GND 789V
Feedback Source Current I
FB
V
FB
=GND 0.7 0.9 1.1 mA
Soft-start Time T
S
Vfb=3 - 10 15 ms
Leading Edge Blanking Time T
LEB
- - 250 - ns
BURST MODE SECTION
Burst Mode Voltages V
BURH
Vcc=14V - 0.7 - V
V
BURL
Vcc=14V - 0.5 - V
FSDM0465RB
6
Electrical Characteristics
(Continued)
(Ta = 25°C unless otherwise specified)
Notes:
1. Pulse test: Pulse width ≤ 300µS, duty ≤ 2%
2. These parameters, although guaranteed at the design, are not tested in mass production.
3. These parameters indicate the inductor current.
4. This parameter is the current flowing into the control IC.
Parameter Symbol Condition Min. Typ. Max. Unit
PROTECTION SECTION
Peak Current Limit (3) I
OVER
V
FB
=5V, V
CC
=14V 1.6 1.8 2.0 A
Over Voltage Protection V
OVP
-181920V
Thermal Shutdown Temperature (2) T
SD
-
130 145 160 °C
Shutdown Feedback Voltage V
SD
V
FB
≥ 5.5V 5.5 6.0 6.5 V
Shutdown Delay Current I
DELAY
V
FB
=5V 2.8 3.5 4.2 µA
TOTAL DEVICE SECTION
Startup Current (4) I
start
V
FB
=GND, V
CC
=11V - 1 1.3 mA
Operating Supply Current (4)
I
OP
V
FB
=GND, V
CC
=14V
-2.55mAI
OP(MIN)
V
FB
=GND, V
CC
=10V
I
OP(MAX)
V
FB
=GND, V
CC
=18V
FSDM0465RB
7
Typical Performance Characteristics
(These Characteristic Graphs are Normalized at Ta= 25°C)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
-25 0 25 50 75 100 125 150
Junction Temperature(℃)
Operating Frequency
(Fosc)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
-25 0 25 50 75 100 125 150
Junction Temperature(℃)
Stop Threshold Voltage
(Vstop)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
-25 0 25 50 75 100 125 150
Junction Temperature(℃)
Maximum Duty Cycle
(Dmax)
Operating Current vs. Temp Start Threshold Voltage vs. Temp
Stop Thre shold Voltage vs. Temp Operating Frequency vs. Temp
Maximum Duty vs. Temp Feedback So urce Current vs. Temp
0.0
0.2
0.4
0.6
0.8
1.0
1.2
-25 0 25 50 75 100 125 150
Junction Temperature(℃)
Operating Current
(Iop)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
-25 0 25 50 75 100 125 150
Junction Temperature(℃)
FB Source Current
(Ifb)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
-25 0 25 50 75 100 125 150
Junction Temperature(℃)
Start Threshold Voltage
(Vstart)
FSDM0465RB
8
Typical Performance Characteristics
(Continued)
(These Characteristic Graphs are Normalized at Ta= 25°C)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
-25 0 25 50 75 100 125 150
Junction Temperature(℃)
Shutdown Delay Current
(Idelay)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
-25 0 25 50 75 100 125 150
Junction Temperature(℃)
Over Voltage Protection
(Vovp)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
-50 -25 0 25 50 75 100 125
Junction Temperature(℃)
Peak Current Limit(Self protection)
(Iover)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
-25 0 25 50 75 100 125 150
Junction Temperature(℃)
FB Burst Mode Enable Voltage
(Vfbe)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
-25 0 25 50 75 100 125 150
Junction Temperature(℃)
FB Burst Mode Disable Voltage
(Vfbd)
Shutdown Feedback Voltage vs. Temp Shutdown Delay Current vs. Temp
Over Voltage Protection vs. Te mp Burst Mode Enable Voltage vs . Temp
Burst M ode Disable Voltage vs. Temp Current Limit vs . Temp
0.0
0.2
0.4
0.6
0.8
1.0
1.2
-25 0 25 50 75 100 125 150
Junction Temperature(℃)
Shutdown FB Voltage
(Vsd)
FSDM0465RB
9
Typical Performance Characteristics
(Continued)
(These Characteristic Graphs are Normalized at Ta= 25°C)
Soft Start Time vs. Temp
0.0
0.2
0.4
0.6
0.8
1.0
1.2
-50 -25 0 25 50 75 100 125
Junction Temperature(℃)
Soft Start Time
(Normalized to 25℃)
FSDM0465RB
10
Functional Description
1.
1. 1.
1. Startup: In previous generations of Fairchild Power
Switches (FPSTM) the Vcc pin had an external start-up
resistor to the DC input voltage line. In this generation the
startup resistor is replaced by an internal high voltage current
source. At startup, an internal high voltage current source
supplies the internal bias and charges the external capacitor
(C
a
) that is connected to the Vcc pin as illustrated in Figure
4. When Vcc reaches 12V, the FSDM0465RB begins
switching and the internal high voltage current source is
disabled. Then, the FSDM0465RB continues its normal
switching operation and the power is supplied from the
auxiliary transformer winding unless Vcc goes below the
stop voltage of 8V.
Figu re 4. Internal Startup Circuit
2. Feedback Control: FSDM0465RB employs current
mode control, as shown in Figure 5. An opto-coupler (such
as the H11A8 17A) and shunt regulator (such as the KA431)
are typically used to implement the feedback network.
Comparing the feedback voltage with the voltage across the
Rsense resistor plus an offset voltage makes it possible to
control the switching duty cycle. When the reference pin
voltage of the KA431 exceeds the internal r eference voltage
of 2.5V, the H11A817A LED current increases, thus
decreasing the feedback voltage and red u cing the d uty cycle .
This event typically happens when the input voltage is
increased or the output load is decreased.
2.1 Pulse-by-Pulse Current Limit: Because current mode
control is emp loyed, the peak current thr ough the SenseFET
is limited by the inverting input of the PWM comparator
(Vfb*) as shown in Figure 5. Assuming that the 0.9mA
current s ource flows on ly through th e internal resist or (2.5R
+R= 2. 8 kΩ), the cathode voltage of diode D2 is about 2.5V.
Since D1 is blocked when the feedback voltage (Vfb)
exceeds 2.5V, the max imum voltage of the cathode o f D2 is
clamped at this voltage, thus clamping Vfb*. Therefore, the
peak value of the current through the SenseFET is limited.
2.2 Leading Edge Blanking (LEB): At the instant the
internal SenseFET is turned on, there usually exists a high
current spike thro ugh the SenseFET, caused by primary-sid e
capacitance and secondary-side rectifier reverse recovery.
Excessive voltage across the Rsense resistor would lead to
incorrect feedback operation in the current mode PWM
control. To counter this effect, the FSDM0465RB employs
an LEB circuit. This circuit inhibits the PWM comparator for
a short time (T
LEB
) after the, SenseFET is turned on.
Figur e 5. Pulse Wi dth Modul at ion (PWM) Circuit
3. Protection Circuit: The FSDM0465RB has several self
protective functions such as over load protection (OLP), over
voltage protection (OVP), and thermal shutdown (TSD).
Because these pro tectio n circuits are fully integ rated in to the
IC without external components, the reliability can be
improved without increasing cost. Once the fault condition
occurs, switching is terminated and the SenseFET remains
off. This causes Vcc to fall. When Vcc reaches the UVLO
stop voltage, 8V, the protection is reset and the internal high
voltage current source charges the Vcc capacitor via the Vstr
pin. When Vcc reaches the UVLO start voltage,12V, the
FSDM0465RB resumes its normal operation. In this manner,
the auto-restart can alternately enable and disable the
switching of the power Sense FET until the fault condition is
eliminated (see Figure 6).
8V/12V
3
Vref
Internal
Bias
Vcc 6Vstr
I
CH
Vcc good
V
DC
C
a
Vcc Good
4
OSC
Vcc Vref
I
delay
I
FB
V
SD
R
2.5R
Gate
driver
OLP
D1 D2
+
V
fb
*
-
Vfb
KA431
C
B
Vo
H11A817A
R
sense
SenseFET
Gate
Driver
FSDM0465RB
11
Figur e 6. Auto Rest art Operation
3.1 Over Load Protection (OLP): Overload is defined as
the load current exceeding a pre-set level due to an
unexpected event. In this situation, the protection circuit
should be activated to protect the SMPS.
However, even when the SMPS is operation normally, the
over load p rotection circu it can be activated during the load
transition. To avoid this undesired operation, the over load
protection circuit is designed to be activated after a specified
time to determine whether it is a transient situation or an
overload situation.
Because of the pulse-by-pulse current limit capability, the
maximum peak current through the SenseFET is limited, and
therefore the maximum input power is restricted with a given
input voltage. I f the output c onsumes beyond this m aximum
power, the output voltage (Vo) decreases below the set
voltage. This reduces the current through the opto-coupler
LED, which also red uces the opto-coupler tran sistor current,
thus increasing the feedback voltage (Vfb).
If Vfb exceeds 2.5V, D1 is blocked and the 3.5uA current
source starts to charge C
B
slowly up to Vcc.
In this condition, Vfb continues increasing until it reaches
6V, when the switching operation is terminated as shown in
Figure 7. The delay time for shutdown is the time required to
charge C
B
from 2.5V to 6.0V with 3.5uA.
In general, a 10 ~ 50 ms delay time is typical for most
applications.
Figure 7. Over Load Protection
3.2 Over Voltage Protection (OVP): If the secondary side
feedback circuit malfunction or a solder defect caused an
open in the feedback path, the current through the opto-
coupler transistor becomes almost zer o. Th en, Vfb climbs up
in a similar manner to the over load situation, forcing the
preset maximum current to be supplied to the SMPS until the
over load protection is activated. Because more energy than
required is provided to the output, the output voltage may
exceed the rated voltage before the over load protection is
activated, resulting in the breakdown of the devices in the
secondary side. To prevent this situation, an OVP circuit is
employed. In general, Vcc is proportional to the output
voltage and the FSDM0465RB uses Vcc instead of directly
monitoring the o utput voltage. If V
CC
exceeds 19V, an OVP
circuit is activated resulting in the termination of the
switching operation. To avoid undesired activation of OVP
during normal operation, Vcc should be designed to be
below 19V.
3.3 Thermal Shutdown (TSD): The SenseFET and the
control IC are built in one package. This makes it easy for
the control IC to detect the heat generation from the Sense
FET. When the temperature exceeds approximately 150°C,
the thermal shutdown is activated.
4. So ft St art: The FSDM0 465RB’s interna l soft-start circuit
slowly increases the PWM comparator’s inverting input
voltage along with the SenseFET current after it starts up.
The typical soft-start time is 10msec, The pulse width to the
power switching device is progressively increased to
establish the correct working conditions for transformers,
inductors, and capacitors. The voltage on the output
capacitors is progressively increased with the intention of
smoothly establishing the required output voltage. It also
helps to prevent transformer satu ration and reduce the stress
on the secondary diode du ring sta r t up.
Fault
situation
8V
12V
Vcc
Vds
t
Fault
occurs Fault
removed
Normal
operation Normal
operation
Power
on
On
Occurs
Removed
Operation Situation Operation
V
VV
V
FB
FBFB
FB
t
tt
t
2.5V
2.5V2.5V
2.5V
6.0V
6.0V6.0V
6.0V
Over load protection
Over load protectionOver load protection
Over load protection
T
TT
T
12
1212
12
= Cfb*(6.0-2.5)/I
= Cfb*(6.0-2.5)/I= Cfb*(6.0-2.5)/I
= Cfb*(6.0-2.5)/I
delay
delaydelay
delay
T
TT
T
1
11
1
T
TT
T
2
22
2
Over Load Protection
FSDM0465RB
12
5. Burst Operation: To minimize power dissipation in
standby mode, the FSDM0465RB enters burst mode
operation. As the load decreases, the feedback voltage
decreases. As shown in Figure 8, the device automatically
enters burst mode when the feedback voltage drops below
V
BURL
(500mV). At this point switching stops and the
output voltages start to drop at a rate dependent on the
standby current load. This causes the feedback voltage to
rise. Once it passes V
BURH
(700mV), switching resumes.
The feedback voltage then falls and the process repeats.
Burst mode operation alternately enables and disables
switching of the power SenseFET thereby reducing
switching loss in Standby mode.
Figure 8. Waveforms of Burst Operation
V
FB
Vds
0.5V
0.7V
Ids
Vo
Vo
set
time
Switching
disabled
T1 T2 T3
Switching
disabled
T4
Switching
Disabled Switching
Disabled
FSDM0465RB
13
Typical application circuit
Features
• High efficiency (>81% at 85Vac input)
• Low zero load power consumption (<300mW at 240Vac input)
• Low standby mode power consumption (<800mW at 240Vac input and 0.3W load)
• Low component count
• Enhanced system reliability through variou s protection functions
• Intern al soft-start (10ms )
Key Design Notes
• Resistors R102 and R105 are employed to prevent start-up at low input voltage. After startup, there is no power loss in these
resistors since the startup pin is internally disconnected after startup.
• The delay time for over load protection is designed to be about 50ms with C106 of 47nF. If a faster triggerin g of OLP is
required, C106 ca n be reduced to 10nF.
• Zener diode ZD102 is used for a safety test such as UL. When the drain pin and feedback pin are shorted, the zener diode
fails and remains short, which causes the fuse (F1) to blow and prevents explosion of the opto-coupler (IC301). This zener
diode also increases the immunity against line surges.
1. Schematic
Application Output Power Input Voltage Output Vo ltage (Max Current)
LCD Monitor 34W Universal Input
(85-265Vac)
5V (2.0A)
12V (2.0A)
3
4
C102
220nF
275VAC
LF101
23mH
C101
220nF
275VAC
RT1
5D-9
F1
FUSE
250V
2A
C103
100uF
400V
R102
30kΩ
ΩΩ
Ω
R105
40kΩ
ΩΩ
Ω
R103
56kΩ
ΩΩ
Ω
2W
C104
2.2nF
1kV D101
UF 4007
C106
47nF
50V
C105
22uF
50V
D102
TVR10G R104
5Ω
ΩΩ
Ω
1
2
3
4
5
T1
EER3016
BD101
2KBP06M3N257
1
2
R101
560kΩ
ΩΩ
Ω
1W
IC1
FSDM0465RB
Vstr
NC
Vfb Vcc
Drain
GND
1
2
3
4
5
6
ZD101
22V
8
10
D202
MBRF10100
C201
1000uF
25V
C202
1000uF
25V
L201
12V, 2A
6
7
D201
MBRF1045
C203
1000uF
10V
C204
1000uF
10V
L202
5V, 2A
R201
1kΩ
ΩΩ
Ω
R202
1.2kΩ
ΩΩ
Ω
R204
5.6kΩ
ΩΩ
Ω
R203
12kΩ
ΩΩ
ΩC205
47nF
R205
5.6kΩ
ΩΩ
Ω
C301
4.7nF
IC301
H11A817A IC201
KA431
ZD102
10V
FSDM0465RB
14
2. Transformer Schematic Diagram
3.Winding Specificatio n
4.Electrical Characteristics
5. Core & Bobbin
Core: EE R 3016
Bobbin: EER3016
Ae(m m2): 96
No Pin (s→f) Wire Turns Winding Method
Na 4 → 50.2
φ × 1 8 Center Winding
Insulation: Polyester Tape t = 0.050mm, 2Layers
Np/2 2 → 10.4
φ × 1 18 Solenoid Winding
Insulation: Polyester Tape t = 0.050mm, 2Layers
N
12V
10 → 80.3
φ × 3 7 Center Winding
Insulation: Polyester Tape t = 0.050mm, 2Layers
N5V 7 → 60.3
φ × 3 3 Center Winding
Insulation: Polyester Tape t = 0.050mm, 2Layers
Np/2 3 → 20.4
φ × 1 18 Solenoid Winding
Outer Insulation: Polyester Tape t = 0.050mm, 2Layers
Pin Specification Remarks
Inductance 1 - 3 650uH ± 10% 100kHz, 1V
Leakage Inductance 1 - 3 10uH Max 2nd All Short
EER3016
N
p
/2 N
12V
N
a
1
2
3
4
56
7
8
9
10
N
p
/2
N
5V
FSDM0465RB
15
6.Demo Circuit Part List
Part Value Note Part Value Note
Fuse C301 4.7nF Polyester Film Cap.
F101 2A/250V NTC Inductor
RT101 5D-9 L201 5uH Wire 1.2mm
Resistor L202 5uH Wire 1.2mm
R101 560K 1W
R102 30K 1/4W
R103 56K 2W
R104 5 1/4W Diode
R105 40K 1/4W D101 UF4007
R201 1K 1/4W D102 TVR10G
R202 1.2K 1/4W D201 MBRF1045
R203 12K 1/4W D202 MBRF10100
R204 5.6K 1/4W ZD101 Zener Diode 22V
R205 5.6K 1/4W ZD102 Zener Diode 10V
Bridge Diode
BD101 2KBP06M 3N257 Bridge Diode
Capacitor
C101 220nF/275VAC Box Capacitor Line Filter
C102 220nF/275VAC Box Capacitor LF101 23mH Wire 0.4mm
C103 100uF/400V Electrolytic Capacitor IC
C104 2.2nF/1kV Ceramic Capacitor IC101 FSDM0465RB FPSTM(4A,650V)
C105 22uF/50V Electrolytic Capacitor IC201 KA431(TL431) Voltage Reference
C106 47nF/50V Ceramic Capacitor IC301 H11A817A Opto-Coupler
C201 1000uF/25V Electrolytic Capacitor
C202 1000uF/25V Electrolytic Capacitor
C203 1000uF/10V Electrolytic Capacitor
C204 1000uF/10V Electrolytic Capacitor
C205 47nF/50V Ceramic Capacitor
FSDM0465RB
16
7. Layout
Figure 9. PCB Top Layout Considerations for FSDM0465RB
Figure 10. PCB Bottom Layout Considerations for FSDM0465RB
FSDM0465RB
17
Package Dimensions
TO-220F-6L(Forming)
FSDM0465RB
10/14/05 0. 0m 001
2005 Fairchild Semiconductor Corporation
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