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SN74LVC1G175
SCES560G –MARCH 2004–REVISED JUNE 2015
SN74LVC1G175 Single D-Type Flip-Flop With Asynchronous Clear
1 Features 3 Description
This single D-type flip-flop is designed for 1.65-V to
1• Available in the Texas Instruments 5.5-V VCC operation.
NanoFree™ Package The SN74LVC1G175 device has an asynchronous
• Supports 5-V VCC Operation clear (CLR) input. When CLR is high, data from the
• Inputs Accept Voltages to 5.5 V input pin (D) is transferred to the output pin (Q) on
• Supports Down Translation to VCC the clock's (CLK) rising edge. When CLR is low, Q is
• Max tpd of 4.3 ns at 3.3 V forced into the low state, regardless of the clock edge
or data on D.
• Low Power Consumption, 10-µA Max ICC NanoFree™ package technology is a major
• ±24-mA Output Drive at 3.3 V breakthrough in IC packaging concepts, using the die
• Ioff Supports Live Insertion, Partial-Power-Down as the package.
Mode, and Back-Drive Protection This device is fully specified for partial-power-down
• Latch-Up Performance Exceeds 100 mA Per applications using Ioff. The Ioff circuitry disables the
JESD 78, Class II outputs, preventing damaging current backflow
• ESD Protection Exceeds JESD 22 through the device when it is powered down.
– 2000-V Human-Body Model (A114-A) Device Information(1)
– 200-V Machine Model (A115-A) PART NUMBER PACKAGE BODY SIZE (NOM)
– 1000-V Charged-Device Model (C101) SN74LVC1G175DBV SOT-23 (6) 2.90 mm × 1.60 mm
SN74LVC1G175DCK SC70 (6) 2.00 mm × 1.25 mm
2 Applications SN74LVC1G175DRY SON (6) 1.45 mm × 1.00 mm
• TV/Set Top Box/Audio SN74LVC1G175YZP DSBGA (6) 1.41 mm × 0.91 mm
• EPOS (Electronic Point-of-Sale) (1) For all available packages, see the orderable addendum at
• Motor Drives the end of the data sheet.
• PC/Notebook
• Servers
• Factory Automation and Control
• Tablets
• Medical Healthcare and Fitness
• Smart Grid
• Telecom Infrastructure
• Enterprise Switching
• Projectors
• Storage
Logic Diagram (Positive Logic)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC1G175
SCES560G –MARCH 2004–REVISED JUNE 2015
www.ti.com
Table of Contents
1 Features.................................................................. 18 Detailed Description............................................ 10
8.1 Overview ................................................................. 10
2 Applications ........................................................... 18.2 Functional Block Diagram....................................... 10
3 Description............................................................. 18.3 Feature Description................................................. 10
4 Revision History..................................................... 28.4 Device Functional Modes........................................ 10
5 Pin Configuration and Functions......................... 39 Application and Implementation ........................ 11
6 Specifications......................................................... 49.1 Application Information............................................ 11
6.1 Absolute Maximum Ratings ..................................... 49.2 Typical Application ................................................. 11
6.2 ESD Ratings.............................................................. 410 Power Supply Recommendations ..................... 12
6.3 Recommended Operating Conditions ...................... 411 Layout................................................................... 12
6.4 Thermal Information.................................................. 511.1 Layout Guidelines ................................................. 12
6.5 Electrical Characteristics........................................... 511.2 Layout Example .................................................... 13
6.6 Timing Requirements, –40°C to 85°C....................... 612 Device and Documentation Support ................. 14
6.7 Timing Requirements, –40°C to 125°C..................... 612.1 Documentation Support ........................................ 14
6.8 Switching Characteristics, –40°C to 85°C................. 612.2 Community Resources.......................................... 14
6.9 Switching Characteristics, –40°C to 85°C................. 612.3 Trademarks........................................................... 14
6.10 Switching Characteristics, –40°C to 125°C............. 712.4 Electrostatic Discharge Caution............................ 14
6.11 Operating Characteristics........................................ 712.5 Glossary................................................................ 14
6.12 Typical Characteristics............................................ 713 Mechanical, Packaging, and Orderable
7 Parameter Measurement Information .................. 8Information ........................................................... 14
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (December 2013) to Revision G Page
• Added Applications................................................................................................................................................................. 1
• Added Device Information table ............................................................................................................................................. 1
• Added ESD Ratingss table..................................................................................................................................................... 4
• Added Thermal Information table........................................................................................................................................... 5
• Added Typical Characteristics................................................................................................................................................ 7
Changes from Revision E (June 2008) to Revision F Page
• Updated document to new TI data sheet format.................................................................................................................... 1
• Deleted Ordering Information table. ....................................................................................................................................... 1
• Updated Features................................................................................................................................................................... 1
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Product Folder Links: SN74LVC1G175
GND VCC
CLK 6
5
4
2
3
DQ
CLR
1
2
GND VCC
1
5
CLK
D4
3Q
6CLR
2
GND VCC
5
34
DQ
6
1
CLK CLR
SN74LVC1G175
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SCES560G –MARCH 2004–REVISED JUNE 2015
5 Pin Configuration and Functions
DBV Package DCK Package
6-Pin SOT-23 6-Pin SC70
Top View Top View
DRY Package YZP Package
6-Pin SON 6-Pin DSBGA
Top View Bottom View
See mechanical drawings for dimensions.
Pin Functions
PIN I/O DESCRIPTION
NAME NO.
CLK 1 I Clock Input
CLR 6 I Clear Data Input
D 3 I Data Input
GND 2 — Ground
Q 4 O Output
VCC 5 — Power
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage –0.5 6.5 V
VIInput voltage –0.5 6.5 V
VOVoltage applied to any output in the high-impedance or power-off state(2) –0.5 6.5 V
VOVoltageapplied to any output in the high or low state(2)(3) –0.5 VCC + 0.5 V
IIK Input clamp current VI< 0 –50 mA
IOK Output clamp current VO< 0 –50 mA
IOContinuous output current ±50 mA
Continuous current through VCC or GND ±100 mA
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the Recommended Operating Conditions table.
6.2 ESD Ratings VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) 2000
Electrostatic
V(ESD) V
discharge Charged-device model (CDM), per JEDEC specification JESD22-C101(2) 1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Operating 1.65 5.5
VCC Supply voltage V
Data retention only 1.5
VCC = 1.65 V to 1.95 V 0.65 × VCC
VCC = 2.3 V to 2.7 V 1.7
VIH High-level input voltage V
VCC = 3 V to 3.6 V 2
VCC = 4.5 V to 5.5 V 0.7 × VCC
VCC = 1.65 V to 1.95 V 0.35 × VCC
VCC = 2.3 V to 2.7 V 0.7
VIL Low-level input voltage V
VCC = 3 V to 3.6 V 0.8
VCC = 4.5 V to 5.5 V 0.3 × VCC
VIInput voltage 0 5.5 V
VOOutput voltage 0 VCC V
VCC = 1.65 V –4
VCC = 2.3 V –8
IOH High-level output current –16 mA
VCC = 3 V –24
VCC = 4.5 V –32
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs,SCBA004.
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Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC = 1.65 V 4
VCC = 2.3 V 8
IOL Low-level output current 16 mA
VCC = 3 V 24
VCC = 4.5 V 32
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V 20
Δt/Δv Input transition rise or fall rate VCC = 3.3 V ± 0.3 V 10 ns/V
VCC = 5 V ± 0.5 V 10
TAOperating free-air temperature –40 125 °C
6.4 Thermal Information SN74LVC1G175
THERMAL METRIC(1) DBV (SOT-23) DCK (SC70) DRY (SON) YZP (DSBGA) UNIT
6 PINS 6 PINS 6 PINS 6 PINS
RθJA Junction-to-ambient thermal resistance 165 259 234 123 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
–40°C to 85°C –40°C to 125°C
PARAMETER TEST CONDITIONS VCC UNIT
MIN TYP(1) MAX MIN TYP(1) MAX
IOH = –100 µA 1.65 V to 5.5 V VCC – 0.1 VCC – 0.1
IOH = –4 mA 1.65 V 1.2 1.2
IOH = –8 mA 2.3 V 1.9 1.9
VOH V
IOH = –16 mA 2.4 2.4
3 V
IOH = –24 mA 2.3 2.3
IOH = –32 mA 4.5 V 3.8 3.8
IOL = 100 µA 1.65 V to 5.5 V 0.1 0.1
IOL = 4 mA 1.65 V 0.45 0.45
IOL = 8 mA 2.3 V 0.3 0.3
VOL V
IOL = 16 mA 0.4 0.4
3 V
IOL = 24 mA 0.55 0.55
IOL = 32 mA 4.5 V 0.55 0.55
IIVI= 5.5 V or GND 0 to 5.5 V ±1 ±1 µA
Ioff VIor VO= 5.5 V 0 ±10 ±10 µA
ICC VI= 5.5 V or GND, IO= 0 1.65 V to 5.5 V 10 10 µA
One input at VCC – 0.6 V,
ΔICC 3 V to 5.5 V 500 500 µA
Other inputs at VCC or GND
CiVI= VCC or GND 3.3 V 3 3 pF
(1) All typical values are at VCC = 3.3 V, TA= 25°C.
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6.6 Timing Requirements, –40°C to 85°C
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2)
–40°C to 85°C
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V UNIT
± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 V
MIN MAX MIN MAX MIN MAX MIN MAX
fclock Clock frequency 100 125 150 175 MHz
CLR Low 5.6 3 2.8 2.5
twPulse duration ns
CLK High or low 3.5 3 2.8 2.5
Data 3 2.5 2 1.5
tsu Setup time, before CLK↑ns
CLR inactive 0 0 0.5 0.5
thHold time, data after CLK↑0 0 0.5 0.5 ns
6.7 Timing Requirements, –40°C to 125°C
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2)
–40°C to 125°C
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V UNIT
± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 V
MIN MAX MIN MAX MIN MAX MIN MAX
fclock Clock frequency 100 125 150 175 MHz
CLR Low 5.6 3 2.8 2.5
twPulse duration ns
CLK High or low 3.5 3 2.8 2.5
Data 3 2.5 2 1.5
tsu Setup time, before CLK↑ns
CLR inactive 0.5 0.5 0.7 0.7
thHold time, data after CLK↑0.5 0.5 0.7 0.7 ns
6.8 Switching Characteristics, –40°C to 85°C
over recommended operating free-air temperature range, CL= 15 pF (unless otherwise noted) (see Figure 2)
–40°C to 85°C
FROM TO VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
PARAMETER UNIT
(INPUT) (OUTPUT) ± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 V
MIN MAX MIN MAX MIN MAX MIN MAX
fmax 100 125 150 175 MHz
CLK 2.5 12.9 2 6.5 1.4 4.6 1 3
tpd Q ns
CLR 2.5 12.4 2 6 1.2 4.3 1 3.2
6.9 Switching Characteristics, –40°C to 85°C
over recommended operating free-air temperature range, CL= 30 pF or 50 pF (unless otherwise noted) (see Figure 3)
–40°C to 85°C
FROM TO VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
PARAMETER UNIT
(INPUT) (OUTPUT) ± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 V
MIN MAX MIN MAX MIN MAX MIN MAX
fmax 100 125 150 175 MHz
CLK 2.7 13.4 2.2 7.1 1.6 5.7 1.5 4
tpd Q ns
CLR 2.7 12.9 2.2 7 1.5 5.8 1.3 4.1
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17.5
18
18.5
19
19.5
20
20.5
21
21.5
0 1 2 3 4 5 6
Power Dissipation Capacitance (pF)
Supply Voltage [VCC] (V)
Typical
&KDUDFWHU«
C001
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SCES560G –MARCH 2004–REVISED JUNE 2015
6.10 Switching Characteristics, –40°C to 125°C
over recommended operating free-air temperature range, CL= 30 pF or 50 pF (unless otherwise noted) (see Figure 3)
–40°C to 125°C
FROM TO VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
PARAMETER UNIT
(INPUT) (OUTPUT) ± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 V
MIN MAX MIN MAX MIN MAX MIN MAX
fmax 100 125 150 175 MHz
CLK 2.7 15.4 2.2 8.1 1.6 6.7 1.5 5
tpd Q ns
CLR 2.7 14.9 2.2 8 1.5 6.8 1.3 5.1
6.11 Operating Characteristics
TA= 25°C VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
PARAMETER TEST CONDITIONS UNIT
TYP TYP TYP TYP
Cpd Power dissipation capacitance f = 10 MHz 18 19 19 21 pF
6.12 Typical Characteristics
Figure 1. Voltage vs Capacitance
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th
tsu
FromOutput
UnderTest
C
(seeNote A)
L
LOADCIRCUIT
S1
VLOAD
Open
GND
RL
DataInput
TimingInput
0V
0V
0V
tW
Input
0V
Input
Output
Waveform1
S1atV
(seeNoteB)
LOAD
Output
Waveform2
S1atGND
(seeNoteB)
VOL
VOH
0V
»0V
Output
Output
t /t
PLH PHL Open
TEST S1
Output
Control
VM
VMVM
VM
VM
1.8V 0.15V±
2.5V 0.2V±
3.3V 0.3V±
5V 0.5V±
1MW
1MW
1MW
1MW
VCC RL
2× VCC
2× VCC
6V
2× VCC
VLOAD CL
15pF
15pF
15pF
15pF
0.15V
0.15V
0.3V
0.3V
VD
3V
VI
VCC/2
VCC/2
1.5V
VCC/2
VM
£2ns
£2ns
£2.5ns
£2.5ns
INPUTS
RL
t /t
r f
VCC
VCC
VCC
VLOAD
t /t
PLZ PZL
GND
t /t
PHZ PZH
VOLTAGEWAVEFORMS
ENABLE ANDDISABLETIMES
LOW- ANDHIGH-LEVEL ENABLING
VOLTAGEWAVEFORMS
PROPAGATIONDELAY TIMES
INVERTING ANDNONINVERTINGOUTPUTS
NOTES: A. C includesprobeandjigcapacitance.
B. Waveform1isforanoutputwithinternalconditionssuchthattheoutputislow,exceptwhendisabledbytheoutputcontrol.
Waveform2isforanoutputwithinternalconditionssuchthattheoutputishigh,exceptwhendisabledbytheoutputcontrol.
C. Allinputpulsesaresuppliedbygeneratorshavingthefollowingcharacteristics:PRR 10MHz,Z =50 .
D. Theoutputsaremeasuredoneatatime,withonetransitionpermeasurement.
E. t andt arethesameast .
F. t andt arethesameast .
G. t andt arethesameast .
H. Allparametersandwaveformsarenotapplicabletoalldevices.
L
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PLZ PHZ dis
PZL PZH en
PLH PHL pd
£ W
VOLTAGEWAVEFORMS
PULSEDURATION
VOLTAGEWAVEFORMS
SETUP ANDHOLDTIMES
VI
VI
VI
VM
VM
V /2
LOAD
tPZL tPLZ
tPHZ
tPZH
V – V
OH D
V +V
OL D
VM
VMVM
VM
VOL
VOH
VI
VI
VOH
VOL
VM
VM
VM
VM
tPLH tPHL
tPLH
tPHL
SN74LVC1G175
SCES560G –MARCH 2004–REVISED JUNE 2015
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7 Parameter Measurement Information
Figure 2. Load Circuit and Voltage Waveforms
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th
tsu
FromOutput
UnderTest
C
(seeNote A)
L
LOADCIRCUIT
S1
VLOAD
Open
GND
RL
DataInput
TimingInput
0V
0V
0V
tW
Input
0V
Input
Output
Waveform1
S1atV
(seeNoteB)
LOAD
Output
Waveform2
S1atGND
(seeNoteB)
VOL
VOH
0V
»0V
Output
Output
TEST S1
t /t
PLH PHL Open
Output
Control
VM
VMVM
VM
VM
1.8V 0.15V±
2.5V 0.2V±
3.3V 0.3V±
5V 0.5V±
1kW
500 W
500 W
500 W
VCC RL
2× VCC
2× VCC
6V
2× VCC
VLOAD CL
30pF
30pF
50pF
50pF
0.15V
0.15V
0.3V
0.3V
VD
3V
VI
VCC/2
VCC/2
1.5V
VCC/2
VM
£2ns
£2ns
£2.5ns
£2.5ns
INPUTS
RL
t /t
r f
VCC
VCC
VCC
VLOAD
t /t
PLZ PZL
GND
t /t
PHZ PZH
VOLTAGEWAVEFORMS
ENABLE ANDDISABLETIMES
LOW- ANDHIGH-LEVEL ENABLING
VOLTAGEWAVEFORMS
PROPAGATIONDELAY TIMES
INVERTING ANDNONINVERTINGOUTPUTS
NOTES: A. C includesprobeandjigcapacitance.
B. Waveform1isforanoutputwithinternalconditionssuchthattheoutputislow,exceptwhendisabledbytheoutputcontrol.
Waveform2isforanoutputwithinternalconditionssuchthattheoutputishigh,exceptwhendisabledbytheoutputcontrol.
C. Allinputpulsesaresuppliedbygeneratorshavingthefollowingcharacteristics:PRR 10MHz,Z =50 .
D. Theoutputsaremeasuredoneatatime,withonetransitionpermeasurement.
E. t andt arethesameast .
F. t andt arethesameast .
G. t andt arethesameast .
H. Allparametersandwaveformsarenotapplicabletoalldevices.
L
O
PLZ PHZ dis
PZL PZH en
PLH PHL pd
£ W
VOLTAGEWAVEFORMS
PULSEDURATION
VOLTAGEWAVEFORMS
SETUP ANDHOLDTIMES
VI
VI
VI
VM
VM
V /2
LOAD
tPZL tPLZ
tPHZ
tPZH
V – V
OH D
V +V
OL D
VM
VMVM
VM
VOL
VOH
VI
VI
VOH
VOL
VM
VM
VM
VM
tPLH tPHL
tPLH
tPHL
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Parameter Measurement Information (continued)
Figure 3. Load Circuit and Voltage Waveforms
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1
6
C1
D
CLR
CLK
D
R
3
4
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8 Detailed Description
8.1 Overview
This single D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC1G175 device has an asynchronous clear (CLR) input. When CLR is high, data from the input pin
(D) is transferred to the output pin (Q) on the clock's (CLK) rising edge. When CLR is low, Q is forced into the
low state, regardless of the clock edge or data on D.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
8.2 Functional Block Diagram
8.3 Feature Description
The SN74LVC1G175 device has a wide operating VCC range of 1.65 V to 5.5 V, which allows it to be used in a
broad range of systems. The 5.5-V I/Os allow down translation and also allow voltages at the inputs when
VCC = 0.
8.4 Device Functional Modes
Table 1 lists the functional modes for SN74LVC1G175.
Table 1. Function Table
INPUTS OUTPUT
Q
CLR CLK D
H↑L L
H↑H H
H H or L X Q0
L X X L
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SN74LVC1G175
GND
D
VCC = 5 V
CLK
Q
VCC
Serial
Input Data
Clock
Pulse
SN74LVC1G175
GND
D
CLK
Q
VCC
SN74LVC1G175
GND
D
CLK
Q
VCC
SN74LVC1G175
GND
D
CLK
Q
VCC Serial
Output Data
AB C D
SN74LVC1G175
www.ti.com
SCES560G –MARCH 2004–REVISED JUNE 2015
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
Multiple SN74LVC1G175 devices can be used in tandem to create a shift register of arbitrary length. In this
example, we use four SN74LVC1G175 devices to form a 4-bit serial shift register. By connecting all CLK inputs
to a common clock pulse and tying each output of one device to the next, we can store and load 4-bit values on
demand. We demonstrate loading the 4 bit value 1101 into memory by setting Serial Input Data to each desired
memory bit, and by sending a clock pulse for each bit, we sequentially move all stored bits from left to right
(A →B→C→D)
9.2 Typical Application
Figure 4. 4-Bit Serial Shift Register
Table 2. Stored Data Values
Serial Input Data Stored A Stored B Stored C Stored D
10000
01000
10100
11010
01101
9.2.1 Design Requirements
The SN74LVC1G175 device uses CMOS technology and has balanced output drive. Care must be taken to
avoid bus contention because it can drive currents that would exceed maximum limits.
The SN74LVC1G175 allows storing digital signals with a digital control signal. All input signals should remain as
close as possible to either 0 V or VCC for optimal operation.
9.2.2 Detailed Design Procedure
1. Recommended input conditions:
– For rise time and fall time specifications, see Δt/Δv in the table.
– For specified high and low levels, see VIH and VIL in the table.
– Inputs and outputs are overvoltage tolerant and can therefore go as high as 5.5 V at any valid VCC.
2. Recommended output conditions:
– Load currents should not exceed ±50 mA.
Copyright © 2004–2015, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Links: SN74LVC1G175
0.00
5.00
10.00
15.00
20.00
0.00 1.00 2.00 3.00 4.00 5.00 6.00 7.00
Max tpd (ns)
Voltage (V) C001
t from CLR to Q.pd
C = 30 pF or 50 pFL
– ° °40 C to 125 C
SN74LVC1G175
SCES560G –MARCH 2004–REVISED JUNE 2015
www.ti.com
3. Frequency selection criterion:
– The effects of frequency upon the output current should be studied in Figure 5.
– Added trace resistance and capacitance can reduce maximum frequency capability; follow the layout
practices listed in the Layout section.
9.2.3 Application Curve
Figure 5. Max tpd vs Voltage of LVC Family
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating listed in the
table.
Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, a 0.1-μF bypass capacitor is recommended. If multiple pins are labeled VCC, then a 0.01-μF or 0.022-μF
capacitor is recommended for each VCC because the VCC pins are tied together internally. For devices with dual
supply pins operating at different voltages, for example VCC and VDD, a 0.1-µF bypass capacitor is recommended
for each supply pin. To reject different frequencies of noise, use multiple bypass capacitors in parallel. Capacitors
with values of 0.1 μF and 1 μF are commonly used in parallel. The bypass capacitor should be installed as close
to the power terminal as possible for best results.
11 Layout
11.1 Layout Guidelines
When using multiple-bit logic devices, inputs must never float.
In many cases, functions (or parts of functions) of digital logic devices are unused, for example, when only two
inputs of a triple-input AND gate are used or when only 3 of the 4 buffer gates are used. Such input pins must
not be left unconnected, because the undefined voltages at the outside connections result in undefined
operational states. Figure 6 specifies the rules that must be observed under all circumstances. All unused inputs
of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that
must be applied to any particular unused input depends on the function of the device. Generally they are tied to
GND or VCC, whichever makes more sense or is more convenient. It is generally acceptable to float outputs,
unless the part is a transceiver. If the transceiver has an output enable pin, it disables the output section of the
part when asserted, which does not disable the input section of the I/Os. Therefore, the I/Os cannot float when
disabled.
12 Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated
Product Folder Links: SN74LVC1G175
Vcc
Unused Input
Input
Output
Input
Unused Input Output
SN74LVC1G175
www.ti.com
SCES560G –MARCH 2004–REVISED JUNE 2015
11.2 Layout Example
Figure 6. Layout Diagram
Copyright © 2004–2015, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: SN74LVC1G175
SN74LVC1G175
SCES560G –MARCH 2004–REVISED JUNE 2015
www.ti.com
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
•Implications of Slow or Floating CMOS Inputs,SCBA004
•Selecting the Right Texas Instruments Signal Switch,SZZA030
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
NanoFree, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.
14 Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated
Product Folder Links: SN74LVC1G175
PACKAGE OPTION ADDENDUM
www.ti.com 24-Aug-2018
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
74LVC1G175DBVRE4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 (C755, C75R)
74LVC1G175DBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 (C755, C75R)
74LVC1G175DCKRG4 ACTIVE SC70 DCK 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 (D65, D6R)
74LVC1G175DCKTG4 ACTIVE SC70 DCK 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 (D65, D6R)
SN74LVC1G175DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 (C755, C75R)
SN74LVC1G175DBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 (C755, C75R)
SN74LVC1G175DCKR ACTIVE SC70 DCK 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 (D65, D6R)
SN74LVC1G175DCKT ACTIVE SC70 DCK 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 (D65, D6R)
SN74LVC1G175DRYR ACTIVE SON DRY 6 5000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 D6
SN74LVC1G175YZPR ACTIVE DSBGA YZP 6 3000 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 D6N
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
PACKAGE OPTION ADDENDUM
www.ti.com 24-Aug-2018
Addendum-Page 2
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVC1G175 :
•Enhanced Product: SN74LVC1G175-EP
NOTE: Qualified Version Definitions:
•Enhanced Product - Supports Defense, Aerospace and Medical Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74LVC1G175DBVR SOT-23 DBV 6 3000 178.0 9.2 3.3 3.23 1.55 4.0 8.0 Q3
SN74LVC1G175DBVT SOT-23 DBV 6 250 178.0 9.2 3.3 3.23 1.55 4.0 8.0 Q3
SN74LVC1G175DCKR SC70 DCK 6 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74LVC1G175DCKT SC70 DCK 6 250 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74LVC1G175DRYR SON DRY 6 5000 179.0 8.4 1.2 1.65 0.7 4.0 8.0 Q1
SN74LVC1G175YZPR DSBGA YZP 6 3000 178.0 9.2 1.02 1.52 0.63 4.0 8.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Aug-2017
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LVC1G175DBVR SOT-23 DBV 6 3000 180.0 180.0 18.0
SN74LVC1G175DBVT SOT-23 DBV 6 250 180.0 180.0 18.0
SN74LVC1G175DCKR SC70 DCK 6 3000 180.0 180.0 18.0
SN74LVC1G175DCKT SC70 DCK 6 250 180.0 180.0 18.0
SN74LVC1G175DRYR SON DRY 6 5000 203.0 203.0 35.0
SN74LVC1G175YZPR DSBGA YZP 6 3000 220.0 220.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Aug-2017
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
0.5 MAX
0.19
0.15
1
TYP
0.5 TYP
6X 0.25
0.21
0.5
TYP
B E A
D
4219524/A 06/2014
DSBGA - 0.5 mm max heightYZP0006
DIE SIZE BALL GRID ARRAY
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. NanoFreeTM package configuration.
NanoFree Is a trademark of Texas Instruments.
BALL A1
CORNER
SEATING PLANE
BALL TYP 0.05 C
B
A
12
0.015 C A B
SYMM
SYMM
C
SCALE 9.000
D: Max =
E: Max =
1.418 mm, Min =
0.918 mm, Min =
1.358 mm
0.858 mm
www.ti.com
EXAMPLE BOARD LAYOUT
6X ( )0.225 (0.5) TYP
(0.5) TYP
()
METAL
0.225 0.05 MAX
SOLDER MASK
OPENING
METAL
UNDER
MASK
()
SOLDER MASK
OPENING
0.225
0.05 MIN
4219524/A 06/2014
DSBGA - 0.5 mm max heightYZP0006
DIE SIZE BALL GRID ARRAY
NOTES: (continued)
4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SBVA017 (www.ti.com/lit/sbva017).
SYMM
SYMM
LAND PATTERN EXAMPLE
SCALE:40X
12
A
B
C
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
SOLDER MASK
DEFINED
www.ti.com
EXAMPLE STENCIL DESIGN
(0.5)
TYP
(0.5) TYP
6X ( 0.25) (R ) TYP0.05
METAL
TYP
4219524/A 06/2014
DSBGA - 0.5 mm max heightYZP0006
DIE SIZE BALL GRID ARRAY
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
SYMM
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:40X
12
A
B
C
GENERIC PACKAGE VIEW
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
DRY 6 USON - 0.6 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
4207181/G
www.ti.com
PACKAGE OUTLINE
C
6X 0.25
0.15
4X
0.5
5X 0.35
0.25
2X
1
0.6 MAX
0.05
0.00
3X 0.6
0.4
0.3
B1.05
0.95 A
1.5
1.4
(0.05) TYP (0.127) TYP
4222894/A 01/2018
USON - 0.6 mm max heightDRY0006A
PLASTIC SMALL OUTLINE - NO LEAD
PIN 1 INDEX AREA
SEATING PLANE
0.08 C
1
34
6
(OPTIONAL)
PIN 1 ID
0.1 C A B
0.05 C
SYMM
SYMM
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
SCALE 8.500
www.ti.com
EXAMPLE BOARD LAYOUT
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
5X (0.3)
6X (0.2)
4X (0.5)
(0.6)
(R0.05) TYP
(0.35)
4222894/A 01/2018
USON - 0.6 mm max heightDRY0006A
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
1
34
6
SYMM
LAND PATTERN EXAMPLE
1:1 RATIO WITH PKG SOLDER PADS
EXPOSED METAL SHOWN
SCALE:40X
NOTES: (continued)
3. For more information, see QFN/SON PCB application report in literature No. SLUA271 (www.ti.com/lit/slua271).
METAL
SOLDER MASK
OPENING
SOLDER MASK DETAILS
NON SOLDER MASK
DEFINED
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
(PREFERRED)
EXPOSED
METAL
www.ti.com
EXAMPLE STENCIL DESIGN
5X (0.3)
6X (0.2)
4X (0.5)
(0.6)
(R0.05) TYP
(0.35)
4222894/A 01/2018
USON - 0.6 mm max heightDRY0006A
PLASTIC SMALL OUTLINE - NO LEAD
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
SOLDER PASTE EXAMPLE
BASED ON 0.075 - 0.1 mm THICK STENCIL
SCALE:40X
SYMM
1
34
6
SYMM
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Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
Texas Instruments:
74LVC1G175DBVRE4 74LVC1G175DBVTE4 74LVC1G175DCKRE4 74LVC1G175DCKTE4 SN74LVC1G175DBVR
SN74LVC1G175DBVT SN74LVC1G175DCKR SN74LVC1G175DCKT SN74LVC1G175YZPR
74LVC1G175DCKRG4 74LVC1G175DCKTG4 74LVC1G175DBVRG4 74LVC1G175DBVTG4 SN74LVC1G175DRYR
74LVC1G175DRYRG4