LTC2463CDD#TRPBF - Linear Technology Corporation

LTC2461/LTC2463

24613fa

–50 –10 10–30 50 7030 90

TEMPERATURE (°C)

REFERENCE OUTPUT VOLTAGE (V)

1.2520

1.2515

1.2510

1.2505

1.2500

24613 TA01b

1.2480

1.2485

1.2490

1.2495

TYPICAL APPLICATION

FEATURES

APPLICATIONS

DESCRIPTION

Ultra-Tiny, 16-Bit I2C ΔΣ

ADCs with 10ppm/°C Max

Precision Reference

The LTC

2461/LTC2463 are ultra tiny, 16-Bit analog-to-

digital converters with an integrated precision reference.

They use a single 2.7V to 5.5V supply and communicate

through an I2C Interface. The LTC2461 is single-ended

with a 0V to 1.25V input range and the LTC2463 is dif-

ferential with a 1.25V input range. Both ADCs include a

1.25V integrated reference with 2ppm/°C drift perfor-

mance and 0.1% initial accuracy. The converters are

available in a 12-pin 3mm × 3mm DFN package or an

MSOP-12 package. They include an integrated oscillator

and perform conversions with no latency for multiplexed

applications. The LTC2461/LTC2463 include a proprietary

input sampling scheme that reduces the average input

current several orders of magnitude when compared to

conventional delta sigma converters.

Following a single conversion, the LTC2461/LTC2463

automatically power down the converter and can also be

conﬁgured to power down the reference. When both the

ADC and reference are powered down, the supply current

is reduced to 200nA.

The LTC2461/LTC2463 can sample at 60 conversions per

second and, due to the very large oversampling ratio,

have extremely relaxed antialiasing requirements. Both

include continuous internal offset and fullscale calibration

algorithms which are transparent to the user, ensuring ac-

curacy over time and the operating temperature range.

VREF vs Temperature

n 16-Bit Resolution, No Missing Codes

n Internal Reference, High Accuracy 10ppm/°C (Max)

n Single-Ended (LTC2461) or Differential (LTC2463)

n 2LSB Offset Error (Typ)

n 0.01% Gain Error (Typ)

n 60 Conversions Per Second

n Single Conversion Settling Time for Multiplexed

Applications

n 1.5mA Supply Current

n 200nA Sleep Current

n Internal Oscillator—No External Components

Required

n 2-Wire I2C Interface with Two Addresses Plus One

Global Address for Synchronization

n Ultra-Tiny, 12-Lead, 3mm × 3mm DFN and MSOP

Packages

n System Monitoring

n Environmental Monitoring

n Direct Temperature Measurements

n Instrumentation

n Data Acquisition

n Embedded ADC Upgrades

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

Protected by U.S. Patents, including 6208279, 6411242, 7088280, 7164378.

10k

SCL I2C

INTERFACE

SDA

0.1µF

2.7V TO 5.5V

10µF

0.1µF

IN+

REFOUT

REF–

VCC

0.1µF

COMP

GND

IN–

0.1µF

LTC2463

24613 TA01a

LTC2461/LTC2463

24613fa

PIN CONFIGURATION

ABSOLUTE MAXIMUM RATINGS

Supply Voltage (VCC) ................................... –0.3V to 6V

Analog Input Voltage

(VIN+, VIN–, VIN, VREF–,

VCOMP, VREFOUT) ........................... –0.3V to (VCC + 0.3V)

Digital Voltage

(VSDA, VSCL, VA0) ..........................–0.3V to (VCC + 0.3V)

(Notes 1, 2)

ORDER INFORMATION

Storage Temperature Range .................. –65°C to 150°C

Operating Temperature Range

LTC2461C/LTC2463C ............................... 0°C to 70°C

LTC2461I/LTC2463I .............................–40°C to 85°C

LTC2463 LTC2463

TOP VIEW

DD PACKAGE

12-LEAD (3mm × 3mm) PLASTIC DFN

1VCC

GND

IN–

IN+

REF–

GND

REFOUT

COMP

GND

SCL

SDA 67

TJMAX = 125°C, θJA = 43°C/W

EXPOSED PAD (PIN 13)

REFOUT

COMP

GND

SCL

SDA

VCC

GND

IN–

IN+

REF–

GND

TOP VIEW

MS PACKAGE

12-LEAD PLASTIC MSOP

TJMAX = 125°C, θJA = 135°C/W

LTC2461 LTC2461

TOP VIEW

DD PACKAGE

12-LEAD (3mm × 3mm) PLASTIC DFN

1VCC

GND

REF–

GND

REFOUT

COMP

GND

SCL

SDA 67

TJMAX = 125°C, θJA = 43°C/W

EXPOSED PAD (PIN 13)

REFOUT

COMP

GND

SCL

SDA

VCC

GND

REF–

GND

TOP VIEW

MS PACKAGE

12-LEAD PLASTIC MSOP

TJMAX = 125°C, θJA = 135°C/W

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC2461CDD#PBF LTC2461CDD#TRPBF LFGF 12-Lead Plastic (3mm × 3mm) DFN 0°C to 70°C

LTC2461IDD#PBF LTC2461IDD#TRPBF LFGF 12-Lead Plastic (3mm × 3mm) DFN –40°C to 85°C

LTC2461CMS#PBF LTC2461CMS#TRPBF 2461 12-Lead Plastic MSOP 0°C to 70°C

LTC2461IMS#PBF LTC2461IMS#TRPBF 2461 12-Lead Plastic MSOP –40°C to 85°C

LTC2463CDD#PBF LTC2463CDD#TRPBF LFGG 12-Lead Plastic (3mm × 3mm) DFN 0°C to 70°C

LTC2463IDD#PBF LTC2463IDD#TRPBF LFGG 12-Lead Plastic (3mm × 3mm) DFN –40°C to 85°C

LTC2463CMS#PBF LTC2463CMS#TRPBF 2463 12-Lead Plastic MSOP 0°C to 70°C

LTC2463IMS#PBF LTC2463IMS#TRPBF 2463 12-Lead Plastic MSOP –40°C to 85°C

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges. *The temperature grade is identiﬁed by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based ﬁnish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

LTC2461/LTC2463

24613fa

ELECTRICAL CHARACTERISTICS

PARAMETER CONDITIONS MIN TYP MAX UNITS

Resolution (No Missing Codes) (Note 3) l16 Bits

Integral Nonlinearity (Note 4) l1 8 LSB

Offset Error LTC2461, 30Hz, LTC2463

LTC2461, 60Hz

15 LSB

LSB

Offset Error Drift 0.02 LSB/°C

Gain Error Includes Contributions of ADC and Internal Reference l±0.01 ±0.25 % of FS

Gain Error Drift Includes Contributions of ADC and Internal Reference

C-Grade

I-Grade

±2

±5

±10

ppm/°C

Transition Noise 2.2 µVRMS

Power Supply Rejection DC 80 dB

The l denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at TA = 25°C. (Note 2)

ANALOG INPUTS

The l denotes the speciﬁcations which apply over the full operating temperature range, otherwise

speciﬁcations are at TA = 25°C.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VCC Supply Voltage l2.7 5.5 V

ICC Supply Current

Conversion

Nap

Sleep

1.5

800

0.2

2.5

1500

µA

The l denotes the speciﬁcations which apply over the full operating temperature

range, otherwise speciﬁcations are at TA = 25°C.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VIN+Positive Input Voltage Range LTC2463 l0 VREF V

VIN–Negative Input Voltage Range LTC2463 l0 VREF V

VIN Input Voltage Range LTC2461 l0 VREF V

VOR+, VUR+Overrange/Underrange Voltage, IN+VIN– = 0.625V (See Figure 3) 8 LSB

VOR–, VUR–Overrange/Underrange Voltage, IN– VIN+ = 0.625V (See Figure 3) 8 LSB

CIN IN+, IN–, IN Sampling Capacitance 0.35 pF

IDC_LEAK(IN+, IN–, IN) IN+, IN– DC Leakage Current (LTC2463)

IN DC Leakage Current (LTC2461)

VIN = GND or VCC (Note 8)

–10

ICONV Input Sampling Current (Note 5) 50 nA

VREF REFOUT Output Voltage l1.247 1.25 1.253 V

REFOUT Voltage Temperature Coefﬁcient (Note 9)

C-Grade

I-Grade

±2

±5

±10

ppm/°C

Reference Line Regulation 2.7V ≤ VCC ≤ 5.5V –90 dB

Reference Short Circuit Current VCC = 5.5, Forcing REFOUT to GND l35 mA

COMP Pin Short Circuit Current VCC = 5.5, Forcing REFOUT to GND l200 µA

Reference Load Regulation 2.7V ≤ VCC ≤ 5.5V, IOUT = 100μA Sourcing 3.5 mV/mA

Reference Output Noise Density CCOMP= 0.1μF, CREFOUT = 0.1μF, At f = 1kHz 30 nV/√Hz

POWER REQUIREMENTS

LTC2461/LTC2463

24613fa

The l denotes the speciﬁcations which apply over the full operating temperature

range, otherwise speciﬁcations are at TA = 25°C. (Notes 2, 7)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VIH High Level Input Voltage l0.7VCC V

VIL Low Level Input Voltage l0.3VCC V

IIDigital Input Current l–10 10 µA

VHYS Hysteresis of Schmidt Trigger Inputs (Note 3) l0.05VCC V

VOL Low Level Output Voltage (SDA) I = 3mA l0.4 V

IIN Input Leakage 0.1VCC ≤ VIN ≤ 0.9VCC l1 µA

CICapacitance for Each I/O Pin l10 pF

CBCapacitance Load for Each Bus Line l400 pF

VIH(A0) High Level Input Voltage for Address Pin l0.95VCC V

VIL(A0) Low Level Input Voltage for Address Pin l0.05VCC V

I2C INPUTS AND OUTPUTS

The l denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at TA = 25°C. (Notes 2, 7)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

tCONV Conversion Time l13 16.6 23 ms

fSCL SCL Clock Frequency l0 400 kHz

tHD(SDA,STA) Hold Time (Repeated) START Condition l0.6 ms

tLOW LOW Period of the SCL Pin l1.3 ms

tHIGH HIGH Period of the SCL Pin l0.6 ms

tSU(STA) Set-Up Time for a Repeated START Condition l0.6 ms

tHD(DAT) Data Hold Time l0 0.9 ms

tSU(DAT) Data Set-Up Time l100 ns

trRise Time for SDA, SCL Signals (Note 6) l20 + 0.1CB300 ns

tfFall Time for SDA, SCL Signals (Note 6) l20 + 0.1CB300 ns

tSU(STO) Set-Up Time for STOP Condition l0.6 ms

tBUF Bus Free Time Between a Stop and Start Condition l1.3 ms

tOF Output Fall Time VIHMIN to VILMAX Bus Load CB = 10pF to

400pF (Note 6)

l20 + 0.1CB250 ns

tSP Input Spike Suppression l50 ns

I2C TIMING CHARACTERISTICS

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All voltage values are with respect to GND. VCC = 2.7V to 5.5V

unless otherwise speciﬁed.

Note 3: Guaranteed by design, not subject to test.

Note 4: Integral nonlinearity is deﬁned as the deviation of a code from a

straight line passing through the actual endpoints of the transfer curve.

Guaranteed by design and test correlation.

Note 5: Input sampling current is the average input current drawn from

the input sampling network while the LTC2461/LTC2463 are converting.

Note 6: CB = capacitance of one bus line in pF.

Note 7: All values refer to VIH(MIN) and VIL(MAX) levels.

Note 8: A positive current is ﬂowing into the DUT pin.

Note 9: Voltage temperature coefﬁcient is calculated by dividing the

maximum change in output voltage by the speciﬁed temperature range.

LTC2461/LTC2463

24613fa

TYPICAL PERFORMANCE CHARACTERISTICS

Offset Error vs Temperature

ADC Gain Error vs Temperature

Transition Noise vs Temperature

Conversion Mode Power Supply

Current vs Temperature

Sleep Mode Power Supply

Current vs Temperature

VREF vs Temperature

(TA = 25°C, unless otherwise noted)

TEMPERATURE (°C)

OFFSET ERROR (LSB)

24613 G04

–1

–2

–3

–4

–5

VCC = 5.5V

VCC = 4.1V

VCC = 2.7V

–50 –10 10–30 50 70

30 90

TEMPERATURE (°C)

–50

ADC GAIN ERROR (LSB)

24613 G05

–25 25 50 750 100

VCC = 5.5V

VCC = 4.1V

VCC = 2.7V

TEMPERATURE (°C)

TRANSITION NOISE RMS (µV)

24613 G06

–50 –10 10–30 50 70

30 90

VCC = 5.5V

VCC = 2.7V

–50 –10 10–30 50 70

30 90

VCC = 5.5V

VCC = 2.7V

TEMPERATURE (°C)

CONVERSION CURRENT (mA)

2.0

1.9

24613 G07

1.4

1.5

1.6

1.7

1.8

1.3

1.2

1.1

1.0

VCC = 4.1V

–50 –10 10–30 50 70

30 90

VCC = 5.5V

VCC = 2.7V

VCC = 4.1V

TEMPERATURE (°C)

SLEEP CURRENT (nA)

350

24613 G08

150

300

250

200

100

0–50 –10 10–30 50 70

30 90

TEMPERATURE (°C)

REFERENCE OUTPUT VOLTAGE (V)

1.2508

24613 G09

1.2502

1.2503

1.2504

1.2505

1.2506

1.2507

VCC = 5V

Integral Nonlinearity (VCC = 5.5V)

Integral Nonlinearity (VCC = 2.7V)

INL vs Temperature

DIFFERENTIAL INPUT VOLTAGE (V)

–1.25 –0.75 –0.25

INL (LSB)

24613 G02

–1

–2

–3 0.25 0.75 1.25

TA = –45°C, 25°C, 90°C

TEMPERATURE (°C)

–55

INL (LSB)

24613 G03

–1

–2

–3 –35 –15 25 45 65 85

5125105

VCC = 5.5V, 4.1V, 2.7V

DIFFERENTIAL INPUT VOLTAGE (V)

–1.25 –0.75 –0.25

INL (LSB)

24613 G01

–1

–2

–3 0.25 0.75 1.25

TA = –45°C, 25°C, 90°C

LTC2461/LTC2463

24613fa

PIN FUNCTIONS

REFOUT (Pin 1): Reference Output Pin. Nominally 1.25V,

this voltage sets the fullscale input range of the ADC. For

noise and reference stability connect to a 0.1µF capacitor

tied to GND. This capacitor value must be less than or

equal to the capacitor tied to the reference compensation

pin (COMP). REFOUT cannot be overdriven by an external

reference. For applications that require an input range

greater than 0V to 1.25V, please refer to the LTC2451/

LTC2453.

COMP (Pin 2): Internal Reference Compensation Pin. For

low noise and reference stability, tie a 0.1μF capacitor to

GND.

A0 (Pin 3): Chip Address Control Pin. The A0 pin can be

tied to GND or VCC. If A0 is tied to GND, the LTC2461/

LTC2463 I2C address is 0010100. If A0 is tied to VCC, the

LTC2461/LTC2463 I2C address is 1010100.

GND (Pins 4, 7, 11): Ground. Connect directly to the

ground plane through a low impedance connection.

SCL (Pin 5): Serial Clock Input of the I2C Interface. The

LTC2461/LTC2463 can only act as a slave and the SCL pin

only accepts external serial clock. Data is shifted into the

SDA pin on the rising edges of SCL and output through

the SDA pin on the falling edges of SCL.

SDA (Pin 6): Bidirectional Serial Data Line of the I2C Inter-

face. The conversion result is output through the SDA pin.

The pin is high impedance unless the LTC2461/LTC2463

is in the data output mode. While the LTC2461/LTC2463

is in the data output mode, SDA is an open drain pull

down (which requires an external 1.7k pull-up resistor

to VCC).

REF– (Pin 8): Negative Reference Input to the ADC. The

voltage on this pin sets the zero input to the ADC. This

pin should tie directly to ground or the ground sense of

the input sensor.

IN+ (LTC2463), IN (LTC2461) (Pin 9): Positive input volt-

age for the LTC2463 differential device. ADC input for the

LTC2461 single-ended device.

IN– (LTC2463), GND (LTC2461) (Pin 10): Negative input

voltage for the LTC2463 differential device. GND for the

LTC2461 single-ended device.

VCC (Pin 12): Positive Supply Voltage. Bypass to GND with

a 10μF capacitor in parallel with a low-series-inductance

0.1μF capacitor located as close to pin 12 as possible.

Exposed Pad (Pin 13 – DFN Package): Ground. Connect

directly to the ground plane through a low impedance

connection.

TYPICAL PERFORMANCE CHARACTERISTICS

(TA = 25°C, unless otherwise noted)

Power Supply Rejection

vs Frequency at VCC

Conversion Time vs Temperature

FREQUENCY AT VCC (Hz)

REJECTION (dB)

24613 G10

–20

–40

–60

–80

–100

–120 10 1k 10k 100k 1M

100 10M

TA = 25°C

VCC = 4.1V

TEMPERATURE (°C)

–50

CONVERSION TIME (ms)

24613 G11

14 –25 25 50 75

100

VCC = 5V, 4.1V, 3V

VREF vs VCC

2.0 3.52.5 4.03.0 5.0 5.54.5 6.0

VCC (V)

REF

(V)

1.24892

1.24891

24613 G12

1.24884

1.24885

1.24886

1.24887

1.24888

1.24889

1.24890

TA = 25°C

LTC2461/LTC2463

24613fa

APPLICATIONS INFORMATION

CONVERTER OPERATION

Converter Operation Cycle

The LTC2461/LTC2463 are low power, delta sigma, ana-

log to digital converters with a simple I2C interface (see

Figure 1). The LTC2463 has a fully differential input while

the LTC2461 is single-ended. Both are pin and software

compatible. Their operation is composed of three distinct

states: CONVERT, SLEEP/NAP, and DATA INPUT/OUTPUT

(see Figure 2). The operation begins with the CONVERT

state. Once the conversion is ﬁnished, the converter auto-

matically powers down (NAP) or, under user control, both

the converter and reference are powered down (SLEEP).

The conversion result is held in a static register while the

device is in this state. The cycle concludes with the DATA

INPUT/OUTPUT state. Once all 16-bits are read the device

begins a new conversion.

The CONVERT state duration is determined by the LTC2461/

LTC2463 conversion time (nominally 16.6 milliseconds).

Once started, this operation can not be aborted except by a

low power supply condition (VCC < 2.1V) which generates

an internal power-on reset signal.

After the completion of a conversion, the LTC2461/LTC2463

enters the SLEEP/NAP state and remains there until a valid

Figure 2. LTC2461/LTC2463 State Transition Diagram

read/write is acknowledged. Following this condition, the

ADC transitions into the DATA INPUT/OUTPUT state.

While in the SLEEP/NAP state, the LTC2461/LTC2463’s

converters are powered down. This reduces the supply

DATA INPUT/OUTPUT

SLEEP/NAP

CONVERT

POWER-ON RESET

YES

24613 F02

STOP

READ 16 BITS

READ/WRITE

ACKNOWLEDGE

NO YES

BLOCK DIAGRAM

Figure 1. Functional Block Diagram

∆Σ A/D

CONVERTER

DECIMATING

SINC FILTER

SDA

REFOUT COMP

REF–

IN+

(IN)

IN–

(GND)

SCL

24613 BD

–

∆Σ A/D

CONVERTER

INTERNAL

REFERENCE

( ) PARENTHESIS INDICATE LTC2461

I2C

INTERFACE

INTERNAL

OSCILLATOR

1VCC

122

8GND

4, 7, 11, 13 (DD PACKAGE)

LTC2461/LTC2463

24613fa

APPLICATIONS INFORMATION

current by approximately 50%. While in the Nap state,

the reference remains powered up. To power down the

reference in addition to the converter, the user can select

the SLEEP mode during the DATA INPUT/OUTPUT state.

Once the next conversion is complete, SLEEP state is

entered and power is reduced to 200nA. The reference

is powered up once a valid read/write is acknowledged.

The reference startup time is 12ms (if the reference and

compensation capacitor values are both 0.1μF).

Power-Up Sequence

When the power supply voltage (VCC) applied to the con-

verter is below approximately 2.1V, the ADC performs a

power-on reset. This feature guarantees the integrity of

the conversion result.

When VCC rises above this critical threshold, the converter

generates an internal power-on reset (POR) signal for

approximately 0.5ms. The POR signal clears all internal

registers. Following the POR signal, the LTC2461/LTC2463

start a conversion cycle and follow the succession of states

shown in Figure 2. The reference startup time following a

POR is 12ms (CCOMP = CREFOUT = 0.1μF). The ﬁrst conver-

sion following power-up will be invalid since the reference

voltage has not completely settled. The ﬁrst conversion

following power up can be discarded using the data abort

command or simply read and ignored. The following con-

versions are accurate to the device speciﬁcations.

Ease of Use

The LTC2461/LTC2463 data output has no latency, ﬁlter

settling delay or redundant results associated with the

conversion cycle. There is a one-to-one correspondence

between the conversion and the output data. Therefore,

multiplexing multiple analog input voltages requires no

special actions.

The LTC2461/LTC2463 perform offset calibrations every

conversion cycle. This calibration is transparent to the

user and has no effect upon the cyclic operation described

previously. The advantage of continuous calibration is

stability of the ADC performance with respect to time and

temperature.

The LTC2461/LTC2463 include a proprietary input sampling

scheme that reduces the average input current by several

orders of magnitude when compared to traditional delta-

sigma architectures. This allows external ﬁlter networks

to interface directly to the LTC2461/LTC2463. Since the

average input sampling current is 50nA, an external RC

lowpass ﬁlter using 1kΩ and 0.1µF results in <1LSB

additional error. Additionally, there is negligible leakage

current between IN+ and IN–.

Input Voltage Range (LTC2461)

Ignoring offset and full-scale errors, the LTC2461 will

theoretically output an “all zero” digital result when the

input is at ground (a zero scale input) and an “all one”

digital result when the input is at VREF (VREFOUT = 1.25V).

In an underrange condition, for all input voltages below

zero scale, the converter will generate the output code 0. In

an overrange condition, for all input voltages greater than

VREF, the converter will generate the output code 65535.

For applications that require an input range greater than

0V to 1.25V, please refer to the LTC2451.

Input Voltage Range (LTC2463)

As mentioned in the Output Data Format section, the output

code is given as 32768 • (VIN+ – VIN–)/VREF + 32768. For

(VIN+ – VIN–) ≥ VREF, the output code is clamped at 65535

(all ones). For (VIN+ – VIN–) ≤ –VREF, the output code is

clamped at 0 (all zeroes).

The LTC2463 includes a proprietary architecture that

can, typically, digitize each input up to 8 LSBs above

LTC2461/LTC2463

24613fa

VREF and below GND, if the differential input is within

±VREF. As an example (Figure 3), if the user desires to

measure a signal slightly below ground, the user could

set VIN– = GND. If VIN+ = GND, the output code would be

approximately 32768. If VIN+ = GND – 8LSB = –0.305mV,

the output code would be approximately 32760.

For ap-

plications that require an input range greater than ±1.25V,

please refer to the LTC2453.

the data line is free, it is HIGH. Data on the I2C bus can be

transferred at rates up to 100kbits/s in the Standard-Mode

and up to 400kbits/s in the Fast-Mode.

Upon entering the DATA INPUT/OUTPUT state,

SDA

outputs

the sign (D15) of the conversion result. During this state,

the ADC shifts the conversion result serially through the

SDA

output pin under the control of the SCL input pin.

There is no latency in generating this data and the result

corresponds to the last completed conversion. A new bit

of data appears at the

SDA

pin following each falling edge

detected at the SCL input pin and appears from MSB to LSB.

The user can reliably latch this data on every rising edge

of the external serial clock signal driving the SCL pin.

Each device on the I2C bus is recognized by a unique

address stored in that device and can operate either as

a transmitter or receiver, depending on the function of

the device. In addition to transmitters and receivers,

devices can also be considered as masters or slaves when

performing data transfers. A master is the device which

initiates a data transfer on the bus and generates the

clock signals to permit that transfer. Devices addressed

by the master are considered a slave. The address of the

LTC2461/LTC2463 is 0010100 (if A0 is tied to GND) or

1010100 (if A0 is tied to VCC).

The LTC2461/LTC2463 can only be addressed as a slave.

It can only transmit the last conversion result. The serial

clock line, SCL, is always an input to the LTC2461/LTC2463

and the serial data line SDA is bidirectional. Figure 4 shows

the deﬁnition of the I2C timing.

APPLICATIONS INFORMATION

Figure 4. Deﬁnition of Timing for Fast/Standard Mode Devices on the I2C Bus

SDA

SCL

S Sr P S

tHD(STA) tHD(DAT)

tSU(STA) tSU(STO)

tSU(DAT)

tLOW tHD(SDA) tSP tBUF

trtftr

tHIGH

24613 F04

Figure 3. Output Code vs VIN+ with VIN– = 0 (LTC2463)

VIN+/VREF+

–0.001

OUTPUT CODE

0.001

24613 F03

–4

–12

–8

–16

–20 –0.005 00.005 0.0015

SIGNALS

BELOW

GND

I2C INTERFACE

The LTC2461/LTC2463 communicate through an I2C in-

terface. The I2C interface is a 2-wire open-drain interface

supporting multiple devices and masters on a single bus.

The connected devices can only pull the data line (SDA)

LOW and can never drive it HIGH. SDA must be externally

connected to the supply through a pull-up resistor. When

LTC2461/LTC2463

24613fa

APPLICATIONS INFORMATION

The START and STOP Conditions

A START (S) condition is generated by transitioning SDA

from HIGH to LOW while SCL is HIGH. The bus is consid-

ered to be busy after the START condition. When the data

transfer is ﬁnished, a STOP (P) condition is generated by

transitioning SDA from LOW to HIGH while SCL is HIGH.

The bus is free after a STOP is generated. START and STOP

conditions are always generated by the master.

When the bus is in use, it stays busy if a repeated START

(Sr) is generated instead of a STOP condition. The repeated

START timing is functionally identical to the START and

is used for reading from the device before the initiation

of a new conversion.

Data Transferring

After the START condition, the I2C bus is busy and data

transfer can begin between the master and the addressed

slave. Data is transferred over the bus in groups of nine

bits, one byte followed by one acknowledge (ACK) bit. The

master releases the SDA line during the ninth SCL clock

cycle. The slave device can issue an ACK by pulling SDA

LOW or issue a Not Acknowledge (NAK) by leaving the

SDA line HIGH impedance (the external pull-up resistor

will hold the line HIGH). Change of data only occurs while

the clock line (SCL) is LOW.

Output Data Format

After a START condition, the master sends a 7-bit address

followed by a read request (R) bit. The bit R is 1 for a

Read Request. If the 7-bit address matches the LTC2461/

LTC2463’s address (0010100 or 1010100, depending on the

state of the pin A0) the ADC is selected. When the device is

addressed during the conversion state, it does not accept

the request and issues a NAK by leaving the SDA line HIGH.

If the conversion is complete, the LTC2461/LTC2463 issue

an ACK by pulling the SDA line LOW.

Following the ACK, the LTC2461/LTC2463 can output data.

The data output stream is 16 bits long and is shifted out

on the falling edges of SCL (see Figure 5a).

The DATA INPUT/OUTPUT state is concluded once all 16

data bits have been read or after a STOP condition.

The LTC2463 (differential input) output code is given by

32768 • (VIN+ – VIN–)/VREF + 32768. The ﬁrst bit output

by the LTC2463, D15, is the MSB, which is 1 for VIN+ ≥

VIN– and 0 for VIN+ < VIN–. This bit is followed by succes-

sively less signiﬁcant bits (D14, D13, …) until the LSB is

output by the LTC2463, see Table 1.

The LTC2461 (single-ended input) output code is a direct

binary encoded result, see Table 1.

1 7 8 9 2 31 8

D8D13D14

MSB

D15RSDA

SCL

7-BIT

ADDRESS

START BY

MASTER

D7 D6 D5 D0

LSB

9 1 2 3 8 9

ACK BY

MASTER

NACK BY

MASTER

SLEEP DATA OUTPUT CONVERSION

24613 F05a

ACK BY

LTC2461/LTC2463

Figure 5a. Read Sequence Timing Diagram

LTC2461/LTC2463

24613fa

APPLICATIONS INFORMATION

Data Input Format

After a START condition, the master sends a 7-bit ad-

dress followed by a read/write request (R/W) bit. The

R/W bit is 0 for a write. The data input word is 4 bits long

and consists of two enable bits (EN1 and EN2) and two

programming bits (SPD and SLP), see Figure 5b. EN1 is

applied to the ﬁrst rising edge of SCL after a valid write

address is acknowledged. Programming is enabled by

setting EN1 = 1 and EN2 = 0.

The speed bit (SPD) is only used by the LTC2461. In the

default mode, SPD = 0, the output rate is 60Hz and con-

tinuous background offset calibration is not performed. By

changing the SPD bit to 1, background offset calibration

is performed and the output rate is reduced to 30Hz. The

LTC2463 data output rate is always 60Hz and background

offset calibration is performed (SPD = don’t care).

The sleep bit (SLP) is used to power down the on chip

reference. In the default mode, the reference remains

powered up even when the ADC is powered down. If the

SLP bit is set HIGH, the reference will power down after

the next conversion is complete. It will remain powered

down until a valid address is acknowledged. The reference

startup time is approximately 12ms. In order to ensure a

stable reference for the following conversions, either the

data input/output time should be delayed 12ms after an

address acknowledge or the ﬁrst conversion following a

reference start up should be discarded.

Figure 5b. Timing Diagram for Writing to the LTC2461/LTC2463

SDA

SCL

EN1 EN2 SPD SLP

SLEEP

START BY

MASTER

DATA INPUT

7 8 9

1 2 3 4 5 6 7 8 9

1 2 …

7-BIT ADDRESS

ACK BY

LTC2461/LTC2463

ACK BY

LTC2461/LTC2463

24613 F03

Table 1. LTC2461/LTC2463 Output Data Format

SINGLE ENDED INPUT VIN

(LTC2461)

DIFFERENTIAL INPUT VOLTAGE

VIN+ – VIN– (LTC2463)

D15

(MSB)

D14 D13 D12...D2 D1 D0

(LSB)

CORRESPONDING

DECIMAL VALUE

≥VREF ≥VREF 1 1 1 1 1 1 65535

VREF – 1LSB VREF – 1LSB 1 1 1 1 1 0 65534

0.75 • VREF 0.5 • VREF 1 1 0 0 0 0 49152

0.75 • VREF – 1LSB 0.5 • VREF – 1LSB 1 0 1 1 1 1 49151

0.5 • VREF 0 1 0 0 0 0 0 32768

0.5 • VREF – 1LSB –1LSB 0 1 1 1 1 1 32767

0.25 • VREF –0.5 • VREF 0 1 0 0 0 0 16384

0.25 • VREF – 1LSB –0.5 • VREF – 1LSB 0 0 1 1 1 1 16383

0 ≤ –VREF 0 0 0 0 0 0 0

LTC2461/LTC2463

24613fa

Figure 7b. Start a New Conversion without Reading Old Conversion Result

Figure 7c. Synchronize the LTC2461/LTC2463 with the Global Address Call

SLEEP

S PR ACK READ (OPTIONAL)

DATA OUTPUT CONVERSIONCONVERSION

24613 F07a

7-BIT ADDRESS

(0010100 OR 1010100)

APPLICATIONS INFORMATION

Figure 6. Consecutive Reading

SLEEP SLEEP

S PR ACK READ READ

DATA OUTPUT

CONVERSION CONVERSION

24613 F06

S R PACK

CONVERSIONDATA OUTPUT

7-BIT ADDRESS

(0010100 OR 1010100)

7-BIT ADDRESS

(0010100 OR 1010100)

OPERATION SEQUENCE

Continuous Read

Conversions from the LTC2461/LTC2463 can be continu-

ously read, see Figure 6. The R/W is 1 for a read. At the

end of a read operation, a new conversion automatically

begins. At the conclusion of the conversion cycle, the next

result may be read using the method described above. If

the conversion cycle is not complete and a valid address

selects the device, the LTC2461/LTC2463 generate a NAK

signal indicating the conversion cycle is in progress. See

Figure 7a for an example state diagram.

Discarding a Conversion Result and Initiating a New

Conversion

It is possible to start a new conversion without reading

the old result, as shown in Figure 7b. Following a valid

7-bit address, a read request (R/W) bit, and a valid ACK,

a STOP command will start a new conversion.

Synchronizing the LTC2461/LTC2463 with the

Global Address Call

The LTC2461/LTC2463 can also be synchronized with

the global address call (see Figure 7c). To achieve this,

the LTC2461/LTC2463 must ﬁrst have completed the

Figure 7a. I2C State Diagram

24613 F07b

7-BIT ADDRESS:

0010100 OR 1010100

WRITE INPUT

CONFIGURATION

(FIGURE 5b)

FOR CYCLE N

I2C START R/W

BIT LOW

WRITE INPUT

CONFIGURATION

(FIGURE 5b)

I2C STOP CONVERT

CONVERSION

FINISHED

ACK

NAK

I2C (REPEAT) START R/W

BIT LOW

7-BIT ADDRESS:

0010100 OR 1010100 I2C START

R/W

BIT HIGH

READ DATA FROM

CYCLE N-1 I2C STOP CONVERT

CONVERSION

FINISHED

7-BIT ADDRESS:

0010100 OR 1010100

GLOBAL ADDRESS

(1110111)

SLEEP CONVERSION

S W ACK WRITE (OPTIONAL) P

24613 F07c

DATA INPUT

LTC2461/LTC2463

24613fa

APPLICATIONS INFORMATION

conversion cycle. The master issues a START, followed

by the LTC2461/LTC2463 global address 1110111, and a

write request. The LTC2461/LTC2463 will be selected and

acknowledge the request. If desired, the master then sends

the write byte to program the 30Hz or 60Hz mode. After

the optional write byte, the master ends the write operation

with a STOP. This will update the conﬁguration registers

(if a write byte was sent) and initiate a new conversion on

the LTC2461/LTC2463, as shown in Figure7c. In order to

synchronize the start of the conversion without affecting

the conﬁguration registers, the write operation can be

aborted with a STOP. This initiates a new conversion on

the LTC2461/LTC2463 without changing the conﬁgura-

tion registers.

PRESERVING THE CONVERTER ACCURACY

The LTC2461/LTC2463 are designed to minimize the conver-

sion result’s sensitivity to device decoupling, PCB layout,

antialiasing circuits, line and frequency perturbations. Nev-

ertheless, in order to preserve the high accuracy capability

of this part, some simple precautions are desirable.

Digital Signal Levels

Due to the nature of CMOS logic, it is advisable to keep

input digital signals near GND or VCC. Voltages in the range

of 0.5V to VCC – 0.5V may result in additional current

leakage from the part. Undershoot and overshoot should

also be minimized, particularly while the chip is convert-

ing. Excessive noise on the digital lines could degrade the

ADC performance.

Driving VCC and GND

In relation to the VCC and GND pins, the LTC2461/LTC2463

combines internal high frequency decoupling with damping

elements, which reduce the ADC performance sensitivity

to PCB layout and external components. Nevertheless,

the very high accuracy of this converter is best pre-

served by careful low and high frequency power supply

decoupling.

A 0.1µF, high quality, ceramic capacitor in parallel with

a 10µF low ESR ceramic capacitor should be connected

between the VCC and GND pins, as close as possible to

the package. The 0.1µF capacitor should be placed closest

to the ADC package. It is also desirable to avoid any via

in the circuit path, starting from the converter VCC pin,

passing through these two decoupling capacitors, and

returning to the converter GND pin. The area encompassed

by this circuit path, as well as the path length, should be

minimized.

As shown in Figure 8, REF– is used as the negative refer-

ence voltage input to the ADC. This pin can be tied directly

to ground or Kelvined to sensor ground. In the case where

REF– is used as a sense input, it should be bypassed to

ground with a 0.1μF ceramic capacitor in parallel with a

10μF low ESR ceramic capacitor.

Very low impedance ground and power planes, and star

connections at both VCC and GND pins, are preferable.

The VCC pin should have two distinct connections: the

ﬁrst to the decoupling capacitors described above, and

the second to the ground return for the power supply

voltage source.

Figure 8. LTC2461/LTC2463 Analog Input/Reference

Equivalent Circuit

RSW

15k

(TYP)

ILEAK

VCC

CEQ

0.35pF

(TYP)

IN+

IN–

REF–

REFOUT

INTERNAL

REFERENCE

24613 F08

RSW

15k

(TYP)

ILEAK

RSW

15k

(TYP)

ILEAK

RSW

15k

(TYP)

ILEAK

LTC2461/LTC2463

24613fa

APPLICATIONS INFORMATION

REFOUT and COMP

The on-chip 1.25V precision reference is internally tied

to the LTC2461/LTC2463 converter’s reference input and

its output to the REFOUT pin. A 0.1μF capacitor should

be placed on the REFOUT pin. It is possible to reduce

this capacitor, but the transition noise increases. A 0.1μF

capacitor should also be placed on the COMP pin. This

pin is tied to an internal point in the reference and is used

for stability. In order for the reference to remain stable the

capacitor placed on the COMP pin must be greater than or

equal to the capacitor tied to the REFOUT pin. The REFOUT

pin should not be overridden by an external voltage. If

a reference voltage greater than 1.25V is required, the

LTC2451/LTC2453 should be used.

The internal reference has a corresponding start up

time depending on the size of the capacitors tied to the

REFOUT and COMP pins. This start up time is typically

12ms when 0.1μF capacitors are used. At initial power up,

the ﬁrst conversion result can be aborted or ignored. At

the completion of this ﬁrst conversion, the reference has

settled and all subsequent conversions are valid.

If the reference is put to sleep (program SLP = 1) the refer-

ence is powered down after the next conversion. This last

conversion result is valid. On a valid address acknowledge,

the reference is powered back up. In order to ensure the

reference output has settled before the next conversion,

the power up time can be extended by delaying the data

read 12ms. Once all 16 bits are read from the device, the

next conversion automatically begins. In the default opera-

tion, the reference remains powered up at the conclusion

of the conversion cycle.

Driving VIN+ and VIN–

The input drive requirements can best be analyzed using

the equivalent circuit of Figure 9. The input signal VSIG is

connected to the ADC input pins (IN+ and IN–) through an

equivalent source resistance RS. This resistor includes both

the actual generator source resistance and any additional

optional resistors connected to the input pins. Optional

input capacitors CIN are also connected to the ADC input

pins. This capacitor is placed in parallel with the input

parasitic capacitance CPAR. This parasitic capacitance

Figure 9. LTC2461/LTC2463 Input Drive Equivalent Circuit

ILEAK

RSW

15k

(TYP)

ICONV

CIN

IN+

(LTC2463)

(LTC2461)

VSIG+

VSIG–

CEQ

0.35pF

(TYP)

CPAR

–

24613 F09

ILEAK

RSW

15k

(TYP)

ICONV

CIN

IN–

(LTC2463)

VCC

CEQ

0.35pF

(TYP)

CPAR

–

includes elements from the printed circuit board (PCB)

and the associated input pin of the ADC. Depending on the

PCB layout, CPAR has typical values between 2pF and 15pF.

In addition, the equivalent circuit of Figure 9 includes the

converter equivalent internal resistor RSW and sampling

capacitor CEQ.

There are some immediate trade-offs in RS and CIN without

needing a full circuit analysis. Increasing RS and CIN can

give the following beneﬁts:

1) Due to the LTC2461/LTC2463’s input sampling algo-

rithm, the input current drawn by IN+, IN– or IN over

a conversion cycle is typically 50nA. A high RS • CIN

attenuates the high frequency components of the input

current, and RS values up to 1k result in <1LSB error.

2) The bandwidth from VSIG is reduced at the input pins

(IN+, IN– or IN). This bandwidth reduction isolates the

ADC from high frequency signals, and as such provides

simple antialiasing and input noise reduction.

3) Switching transients generated by the ADC are attenu-

ated before they go back to the signal source.

4) A large CIN gives a better AC ground at the input pins,

helping reduce reﬂections back to the signal source.

5) Increasing RS protects the ADC by limiting the current

during an outside-the-rails fault condition.

There is a limit to how large RS • CIN should be for a given

application. Increasing RS beyond a given point increases

the voltage drop across RS due to the input current,

LTC2461/LTC2463

24613fa

APPLICATIONS INFORMATION

to the point that signiﬁcant measurement errors exist.

Additionally, for some applications, increasing the RS • CIN

product too much may unacceptably attenuate the signal

at frequencies of interest.

For most applications, it is desirable to implement CIN as

a high-quality 0.1µF ceramic capacitor and to set RS ≤ 1k.

This capacitor should be located as close as possible to

the actual IN+, IN– or IN package pin. Furthermore, the

area encompassed by this circuit path, as well as the path

length, should be minimized.

In the case of a 2-wire sensor that is not remotely

grounded, it is desirable to split RS and place series

resistors in the ADC input line as well as in the sensor

ground return line, which should be tied to the ADC GND

pin using a star connection topology.

Figure 10 shows the measured LTC2463 INL vs Input

Voltage as a function of RS value with an input capacitor

CIN = 0.1µF.

In some cases, RS can be increased above these guidelines.

The input current is zero when the ADC is either in sleep

or I/O modes. Thus, if the time constant of the input RC

circuit t = RS • CIN, is of the same order of magnitude or

longer than the time periods between actual conversions,

then one can consider the input current to be reduced

correspondingly.

These considerations need to be balanced out by the input

signal bandwidth. The 3dB bandwidth ≈ 1/(2pRSCIN).

Finally, if the recommended choice for CIN is unacceptable

for the user’s speciﬁc application, an alternate strategy is to

eliminate CIN and minimize CPAR and RS. In practical terms,

this conﬁguration corresponds to a low impedance sensor

directly connected to the ADC through minimum length

traces. Actual applications include current measurements

through low value sense resistors, temperature measure-

ments, low impedance voltage source monitoring, and so

on. The resultant INL vs VIN is shown in Figure 11. The

measurements of Figure 11 include a capacitor CPAR cor-

responding to a minimum sized layout pad and a minimum

width input trace of about 1 inch length.

Signal Bandwidth, Transition Noise and Noise

Equivalent Input Bandwidth

The LTC2461/LTC2463 include a sinc1 type digital ﬁlter

with the ﬁrst notch located at f0 = 60Hz. As such, the

3dB input signal bandwidth is 26.54Hz. The calculated

LTC2461/LTC2463 input signal attenuation vs frequency

over a wide frequency range is shown in Figure 12. The

calculated LTC2461/LTC2463 input signal attenuation vs

frequency at low frequencies is shown in Figure 13. The

converter noise level is about 2.2µVRMS and can be mod-

eled by a white noise source connected at the input of a

noise-free converter.

On a related note, the LTC2463 uses two separate A/D

converters to digitize the positive and negative inputs.

Each of these A/D converters has 2.2µVRMS transition

noise. If one of the input voltages is within this small

transition noise band, then the output will ﬂuctuate one

bit, regardless of the value of the other input voltage. If

both of the input voltages are within their transition noise

bands, the output can ﬂuctuate 2 bits.

For a simple system noise analysis, the VIN drive circuit can

be modeled as a single-pole equivalent circuit character-

ized by a pole location fi and a noise spectral density ni.

If the converter has an unlimited bandwidth, or at least a

bandwidth substantially larger than fi, then the total noise

contribution of the external drive circuit would be:

Vn=nip/ 2•fi

Then, the total system noise level can be estimated as

the square root of the sum of (Vn2) and the square of the

LTC2461/LTC2463 noise ﬂoor (~2.2µV2).

LTC2461/LTC2463

24613fa

Figure 12. LTC2463 Input Signal Attentuation vs Frequency Figure 13. LTC2463 Input Signal Attenuation

vs Frequency (Low Frequencies)

APPLICATIONS INFORMATION

INPUT SIGNAL FREQUENCY (MHz)

INPUT SIGNAL ATTENUATION (dB)

–40

1.00 1.25 1.50

24613 F12

–60

–80

–20

–100

2.5 5.0 7.5

VCC = 5V

TA = 25°C

INPUT SIGNAL FREQUENCY (Hz)

INPUT SIGNAL ATTENUATIOIN (dB)

–20

–10

480

24613 F13

–30

–40

–25

–15

–5

–35

–45

–50 12060 240180 360 420 540

300 600

VCC = 5V

TA = 25°C

Figure 10. Measured INL vs Input Voltage (CIN = 0.1µF) Figure 11. Measured INL vs Input Voltage (CIN = 0)

DIFFERENTIAL INPUT VOLTAGE (V)

–1.25 –0.75 –0.25

INL (LSB)

24613 F10

–1

–2

–3 0.25 0.75 1.25

CIN = 0.1µF

VCC = 5V

TA = 25°C

RS = 10k

RS = 1k

RS = 0k

DIFFERENTIAL INPUT VOLTAGE (V)

–1.25 –0.75 –0.25

INL (LSB)

24613 F11

–1

–2

–3 0.25 0.75 1.25

CIN = 0

VCC = 5V

TA = 25°C

RS = 10k

RS = 1k

RS = 0k

LTC2461/LTC2463

24613fa

PACKAGE DESCRIPTION

DD Package

12-Lead Plastic DFN (3mm × 3mm)

(Reference LTC DWG # 05-08-1725 Rev A)

3.00 ±0.10

(4 SIDES)

NOTE:

1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD AND TIE BARS SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE

TOP AND BOTTOM OF PACKAGE

0.40 ± 0.10

BOTTOM VIEW—EXPOSED PAD

1.65 ± 0.10

0.75 ±0.05

R = 0.115

TYP

127

PIN 1

TOP MARK

(SEE NOTE 6)

0.200 REF

0.00 – 0.05

(DD12) DFN 0106 REV A

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

0.23 ± 0.05

0.25 ± 0.05

2.25 REF

2.38 ±0.05

1.65 ±0.05

2.10 ±0.05

0.70 ±0.05

3.50 ±0.05

PACKAGE

OUTLINE

PIN 1 NOTCH

R = 0.20 OR

0.25 × 45°

CHAMFER

2.38 ±0.10

2.25 REF

0.45 BSC

LTC2461/LTC2463

24613fa

PACKAGE DESCRIPTION

MS Package

12-Lead Plastic MSOP

(Reference LTC DWG # 05-08-1668 Rev Ø)

MSOP (MS12) 1107 REV Ø

0.53 ± 0.152

(.021 ± .006)

SEATING

PLANE

0.18

(.007)

1.10

(.043)

MAX

0.22 – 0.38

(.009 – .015)

TYP

0.86

(.034)

REF

0.650

(.0256)

BSC

12 11 10 9 8 7

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

0.254

(.010) 0° – 6° TYP

DETAIL “A”

GAUGE PLANE

5.23

(.206)

MIN

3.20 – 3.45

(.126 – .136)

0.889 ± 0.127

(.035 ± .005)

RECOMMENDED SOLDER PAD LAYOUT

0.42 ± 0.038

(.0165 ± .0015)

TYP

0.65

(.0256)

BSC

4.039 ± 0.102

(.159 ± .004)

(NOTE 3)

0.1016 ± 0.0508

(.004 ± .002)

1 2 3 4 5 6

3.00 ± 0.102

(.118 ± .004)

(NOTE 4)

0.406 ± 0.076

(.016 ± .003)

REF

4.90 ± 0.152

(.193 ± .006)

LTC2461/LTC2463

24613fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER

A 5/11 Added “Synchronizing the LTC2461/LTC2463 with the Global Address Call” to the Applications Information section 12-13

LTC2461/LTC2463

24613fa

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 l FAX: (408) 434-0507 l www.linear.com

 LINEAR TECHNOLOGY CORPORATION 2009

LT 0511 REV A • PRINTED IN USA

RELATED PARTS

PART NUMBER DESCRIPTION COMMENTS

LTC1860/LTC1861 12-Bit, 5V, 1-/2-Channel 250ksps SAR ADC in MSOP 850µA at 250ksps, 2µA at 1ksps, SO-8 and MSOP Packages

LTC1860L/LTC1861L 12-Bit, 3V, 1-/2-Channel 150ksps SAR ADC 450µA at 150ksps, 10µA at 1ksps, SO-8 and MSOP Packages

LTC1864/LTC1865 16-Bit, 5V, 1-/2-Channel 250ksps SAR ADC in MSOP 850µA at 250ksps, 2µA at 1ksps, SO-8 and MSOP Packages

LTC1864L/LTC1865L 16-bit, 3V, 1-/2-Channel 150ksps SAR ADC 450µA at 150ksps, 10µA at 1ksps, SO-8 and MSOP Packages

LTC2360 12-Bit, 100ksps SAR ADC 3V Supply, 1.5mW at 100ksps, TSOT 6-pin/8-pin Packages

LTC2440 24-Bit No Latency ΔΣ™

ADC 200nVRMS Noise, 4kHz Output Rate, 15ppm INL

LTC2480 16-Bit, Differential Input, No Latency ΔΣ ADC, with PGA,

Temp. Sensor, SPI

Easy-Drive Input Current Cancellation, 600nVRMS Noise,

Tiny 10-Lead DFN Package

LTC2481 16-Bit, Differential Input, No Latency ΔΣ ADC, with PGA,

Temp. Sensor, I2C

Easy-Drive Input Current Cancellation, 600nVRMS Noise,

Tiny 10-Lead DFN Package

LTC2482 16-Bit, Differential Input, No Latency ΔΣ ADC, SPI Easy-Drive Input Current Cancellation, 600nVRMS Noise,

Tiny 10-Lead DFN Package

LTC2483 16-Bit, Differential Input, No Latency ΔΣ ADC, I2CEasy-Drive Input Current Cancellation, 600nVRMS Noise,

Tiny 10-Lead DFN Package

LTC2484 24-Bit, Differential Input, No Latency ΔΣ ADC, SPI with

Temp. Sensor

Easy-Drive Input Current Cancellation, 600nVRMS Noise,

Tiny 10-Lead DFN Package

LTC2485 24-Bit, Differential Input, No Latency ΔΣ ADC, I2C with

Temp. Sensor

Easy-Drive Input Current Cancellation, 600nVRMS Noise,

Tiny 10-Lead DFN Package

LTC6241 Dual, 18MHz, Low Noise, Rail-to-Rail Op Amp 550nVP-P Noise, 125µV Offset Max

LTC2450 Easy-to-Use, Ultra-Tiny 16-Bit ADC, SPI, 0V to 5.5V

Input Range 2 LSB INL, 50nA Sleep current, Tiny 2mm × 2mm DFN-6 Package,

30Hz Output Rate

LTC2450-1 Easy-to-Use, Ultra-Tiny 16-Bit ADC, SPI, 0V to 5.5V

Input Range 2 LSB INL, 50nA Sleep Current, Tiny 2mm × 2mm DFN-6 Package,

60Hz Output Rate

LTC2451 Easy-to-Use, Ultra-Tiny 16-Bit ADC, I2C, 0V to 5.5V

Input Range 2 LSB INL, 50nA Sleep Current, Tiny 3mm × 2mm DFN-8 or TSOT

Package, Programmable 30Hz/60Hz Output Rates

LTC2452 Easy-to-Use, Ultra-Tiny 16-Bit Differential ADC, SPI,

±5.5V Input Range 2 LSB INL, 50nA Sleep Current, Tiny 3mm × 2mm DFN-8 or TSOT

Package

LTC2453 Easy-to-Use, Ultra-Tiny 16-Bit Differential ADC, I2C,

±5.5V Input Range 2 LSB INL, 50nA Sleep Current, Tiny 3mm × 2mm DFN-8 or TSOT

Package

LTC2460 16-Bit, ΔΣ SPI ADC with 10ppm Max Reference Single-Ended, Tiny 12-Lead 3mm × 3mm DFN and MSOP Packages

LTC2462 16-Bit, ΔΣ SPI ADC with 10ppm Max Reference Differential Input, Tiny 12-Lead 3mm × 3mm DFN and MSOP Packages

No Latency ΔΣ is a trademark of Linear Technology Corporation.

0.1µF

VCC

IN+

IN–

24613 TA02

10µF

0.1µF

7, 11, 48

121

0.1µF

1k 5k

5SCK/SCL

MOSI/SDA

MISO/SDO

GND

1µF

VCC

µC

VCC

IN+

REFOUT

REF–

VCC

GND

COMP

IN–

LTC2463

SCL

SDA 3

0.1µF

VCC

TYPICAL APPLICATION