DATASHEET
SYSTEM PERIPHERAL CLOCK SOURCE ICS650-01
IDT™ / ICS™
SYSTEM PERIPHERAL CLOCK SOURCE 1
ICS650-01 REV H 051310
Description
The ICS650-01 is a low-cost, low-jitter, high-performance
clock synthesizer for system peripheral applications. Using
analog/digital Phase-Locked Loop (PLL) techniques, the
device accepts a parallel resonant 14.31818 MHz crystal
input to produce up to eight output clocks. The device
provides clocks for PCI, SCSI, Fast Ethernet, Ethernet,
USB, and AC97. The user can select one of three USB
frequencies and also one of two AC97 audio frequencies.
The OE pin puts all outputs into a high impedance state for
board level testing. All frequencies are generated with less
than one ppm error, meeting the demands of SCSI and
Ethernet clocking.
Features
•Packaged in 20-pin SSOP (QSOP)
•Pb (lead) free package
•Operating voltage of 3.3 V or 5 V
•Less than one ppm synthesis error in all clocks
•Inexpensive 14.31818 MHz crystal or clock input
•Provides Ethernet and Fast Ethernet clocks
•Provides SCSI clocks
•Provides PCI clocks
•Selectable AC97 audio clock
•Selectable USB clock
•OE pin tri-states the outputs for testing
•Selectable frequencies on three clocks
•Duty cycle of 40/60
•Advanced, low-power CMOS process
•Industrial temperature range available
Block Diagram
Clock
Synthesis
Circuitry USB Clock
Processor
Clocks
14.31818 MHz
Crystal or Clock
Audio Clock
20 MHz
4
OE (all outputs)
14.31818 MHz
Crystal
Oscillator
X1/ICLK
X2
PSEL1:0
ASEL
USEL
VDD
3
2
GND
2
ICS650-01
SYSTEM PERIPHERAL CLOCK SOURCE CLOCK SYNTHESIZER
IDT™ / ICS™
SYSTEM PERIPHERAL CLOCK SOURCE 2
ICS650-01 REV H 051310
Pin Assignment
USB Clock (MHz)
Processor Clock (MHz)
Audio Clock (MHz)
0 = connect directly to ground
1 = connect directly to VDD
M = leave unconnected (floating)
Pin Descriptions
USEL UCLK
012
M24
148
13
4
12
5
11
VDD
8
9
10
VDD
20M 14.318M
OE
ACLK PCLK1
17
16
PCLK4
3
X1/ICLK
VDD PCLK3
18 PCLK2
1
USEL
X2 PSEL0
20 PSEL1
19
14
2
7
GND
UCLK
ASEL
GND
156
20 pin (150 mil) SSOP
PSEL1 PSEL0 PCLK1 PCLK2, 3 PCLK4
0 0 25 50 18.75
0 M TEST TEST TEST
0 1 TEST TEST TEST
M 0 40 80 20
M M 33.3334 66.6667 25
M 1 20 40 25
1 0 20 33.3334 25
1 M 20 66.6667 25
1 1 Stops low all clocks except 20M
ASEL ACLK
0 49.152
M 24.576
1 12.288
Pin
Number
Pin
Name
Pin
Type
Pin Description
1 USEL Input UCLK select pin. Determines frequency of USB clock per table above.
2 X2 XO Crystal connection. Connect to parallel mode 14.31818 MHz crystal.
Leave open for clock.
3 X1/ICLK XI Crystal connection. Connect to parallel mode 14.31818 MHz crystal or
clock.
4 VDD Power Connect to VDD. Must be same value as other VDD. Decouple with pin 6.
5 VDD Power Connect to VDD. Must be same value as other VDD.
6 GND Power Connect to ground.
7 UCLK Output USB clock output per table above.
8 20M Output Fixed 20 MHz output for Ethernet. Only clock that runs when
PSEL1=PSEL0=1.
9 ACLK Output AC97 audio clock output per table above.
10 PCLK4 Output PCLK output number 4 per table above.
ICS650-01
SYSTEM PERIPHERAL CLOCK SOURCE CLOCK SYNTHESIZER
IDT™ / ICS™
SYSTEM PERIPHERAL CLOCK SOURCE 3
ICS650-01 REV H 051310
External Components
The ICS650-01 requires a minimum number of external
components for proper operation.
Decoupling Capacitor
Decoupling capacitors of 0.01µF must be connected
between each VDD and GND (pins 4 and 6, pins 16 and 14),
as close to the device as possible. For optimum device
performance, the decoupling capacitor should be mounted
on the component side of the PCB. Avoid the use of vias in
the decoupling circuit.
Series Termination Resistor
When the PCB trace between the clock outputs and the
loads are over 1 inch, series termination should be used. To
series terminate a 50Ω trace (a commonly used trace
impedance) place a 33Ω resistor in series with the clock line,
as close to the clock output pin as possible. The nominal
impedance of the clock output is 20Ω.
Crystal Information
The crystal used should be a fundamental mode (do not use
third overtone), parallel resonant, 300 ppm or better (to
meet Ethernet specs). Crystal capacitors should be
connected from pins X1 to ground and X2 to ground to
optimize the initial accuracy. The value of these capacitors
is given by the following equation:
Crystal caps (pF) = (CL - 12) x 2
In the equation, CL is the crystal load capacitance. So, for a
crystal with a 16 pF load capacitance, two 8 pF capacitors
should be used. If a clock input is used, drive it into X1 and
leave X2 unconnected.
11 OE Input Output enable. Tri-states all outputs when low.
12 PCLK1 Output PCLK output number 1 per table above.
13 14.318M Output 14.31818 MHz Buffered reference clock output.
14 GND Power Connect to ground.
15 ASEL Input ACLK select pin. Determines frequency of Audio clock per table above.
16 VDD Power Connect to VDD. Must be same value as other VDD. Decouple with pin 14.
17 PCLK3 Output PCLK output number 3 per table above.
18 PCLK2 Output PCLK output number 2 per table above.
19 PSEL0 Input Processor select pin #0. Determines frequencies on PCLKs 1-4 per table
above.
20 PSEL1 Input Processor select pin #1. Determines frequencies on PCLKs 1-4 per table
above.
Pin
Number
Pin
Name
Pin
Type
Pin Description
ICS650-01
SYSTEM PERIPHERAL CLOCK SOURCE CLOCK SYNTHESIZER
IDT™ / ICS™
SYSTEM PERIPHERAL CLOCK SOURCE 4
ICS650-01 REV H 051310
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS650-01. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these
or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Recommended Operation Conditions
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V ±5% (or 5 V unless noted), Ambient Temperature 0 to +70°C
Note 1: With all clocks at highest frequencies.
Item Rating
Supply Voltage, VDD 7 V
All Inputs and Outputs -0.5 V to VDD+0.5 V
Ambient Operating Temperature 0 to +70°C
Storage Temperature -65 to +150°C
Junction Temperature 125°C
Soldering Temperature 260°C
Parameter Min. Typ. Max. Units
Ambient Operating Temperature 0 +70 °C
Power Supply Voltage (measured in respect to GND) +3.0 +3.3 +5.5 V
Parameter Symbol Conditions Min. Typ. Max. Units
Operating Voltage VDD 3.0 5.5 V
Supply Current IDD At 5 V, No load, Note 1 50 mA
Supply Current IDD At 3.3 V, No load,
Note 1
30 mA
Input High Voltage VIH Select inputs, OE 2 V
Input Low Voltage VIL Select inputs, OE 0.8 V
Output High Voltage VOH VDD = 3.3 V,
IOH = -8 mA
2.4 V
Output High Voltage VOH VDD = 3.3 V or 5 V,
IOH = -8 mA
VDD-0.4 V
Output Low Voltage VOL VDD = 3.3 V,
IOL = 8mA
0.4 V
Short Circuit Current IOS VDD = 3.3 V,
each output
±50 mA
Input Capacitance Except X1 7 pF
ICS650-01
SYSTEM PERIPHERAL CLOCK SOURCE CLOCK SYNTHESIZER
IDT™ / ICS™
SYSTEM PERIPHERAL CLOCK SOURCE 5
ICS650-01 REV H 051310
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V ±5% (or 5 V unless noted), Ambient Temperature 0 to +70° C
Note 1: Measured with 15 pF load
Thermal Characteristics
Marking Diagram—ICS650R-01LF Marking Diagram—ICS650R-01ILF
Notes:
1. ###### is the lot code.
2. YYWW is the last two digits of the year, and the week number that the part was assembled.
3. “LF” denotes Pb (lead) free package.
4. “I” denotes industrial grade device.
5. Bottom marking: (origin) = country of origin if not USA.
Parameter Symbol Conditions Min. Typ. Max. Units
Input Frequency 14.31818 MHz
Output Clocks Accuracy
(synthesis error)
All clocks 1 ppm
Output Rise Time tOR 0.8 to 2.0 V, Note 1 1.5 ns
Output Fall Time tOF 2.0 to 0.8 V, Note 1 1.5 ns
Output Clock Duty Cycle At VDD/2 40 50 60 %
One Sigma Jitter except ACLK 75 ps
ACLK 170 ps
Absolute Clock Period Jitter PCLK, UCLK, 20M -500 500 ps
Parameter Symbol Conditions Min. Typ. Max. Units
Thermal Resistance Junction to
Ambient
θJA Still air 135 °C/W
θJA 1 m/s air flow 93 °C/W
θJA 3 m/s air flow 78 °C/W
Thermal Resistance Junction to Case θJC 60 °C/W
10
20 11
1
650R-01LF
######
YYWW
10
20 11
1
650R-01ILF
######
YYWW
ICS650-01
SYSTEM PERIPHERAL CLOCK SOURCE CLOCK SYNTHESIZER
IDT™ / ICS™
SYSTEM PERIPHERAL CLOCK SOURCE 6
ICS650-01 REV H 051310
Package Outline and Package Dimensions (20-pin SSOP, 150 Mil. Body)
Package dimensions are kept current with JEDEC Publication No. 95
Ordering Information
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes
no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No
other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications
such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT
does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
Part / Order Number Marking Shipping Packaging Package Temperature
650R-01LF see page 6 Tubes 20-pin SSOP 0 to +70° C
650R-01LFT Tape and Reel 20-pin SSOP 0 to +70° C
650R-01ILF Tubes 20-pin SSOP -40 to 85° C
650R-01ILFT Tape and Reel 20-pin SSOP -40 to 85° C
INDEX
AREA
1 2
20
D
E1 E
SEATING
PLANE
A
1
A
A
2
e
- C -
b
.10 (.004) C
c
L
Millimeters Inches
Symbol Min Max Min Max
A 1.35 1.75 0.053 0.069
A1 0.10 0.25 0.004 0.010
A2 -- 1.50 -- 0.059
b 0.20 0.30 0.008 0.012
c 0.18 0.25 0.007 0.010
D 8.55 8.75 0.337 0.344
E 5.80 6.20 0.228 0.244
E1 3.80 4.00 0.150 0.157
e .635 Basic .025 Basic
L 0.40 1.27 0.016 0.050
α0°8°0°8°
ICS650-01
SYSTEM PERIPHERAL CLOCK SOURCE CLOCK SYNTHESIZER
IDT™ / ICS™
SYSTEM PERIPHERAL CLOCK SOURCE 7
ICS650-01 REV H 051310
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
Printed in USA
Corporate Headquarters
Integrated Device Technology, Inc.
www.idt.com
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
For Tech Support
www.idt.com/go/clockhelp
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
ICS650-01
SYSTEM PERIPHERAL CLOCK SOURCE CLOCK SYNTHESIZER
