© 2000 Fairchild Semiconductor Corporation DS009528 www.fairchildsemi.com
May 1988
Revised October 2000
74F381 4-Bit Arithmetic Logic Unit
74F381
4-Bit Arithmetic Logic Unit
General Description
The 7 4F 3 81 p er f or ms t h ree ar i t h me ti c an d th r ee l o gi c op er -
ations on two 4-bit words, A and B. Two additional select
input codes force the function outputs LOW or HIGH. Carry
propagate and gener ate outputs are provid ed for use with
the 74F182 carry lookahead generator for high-speed
expansion to longer word lengths. For ripple expansion,
refer to the 74F382 ALU data sheet.
Features
■Low input loading minimizes drive requirements
■Performs six arithmetic and logic functions
■Selectable LOW (clear) and HIGH (preset) functions
■Carry gen er ate an d pr opa gat e out puts for use with carr y
lookahe ad gen era tor
Ordering Code:
Devices also available in Tape and R eel. Speci fy by appending the s uffix let t er “X” to the o rdering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Order Number Package Number Package Description
74F381SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F381SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F381PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
www.fairchildsemi.com 2
74F381
Unit Loading/Fan Out
Functional Description
Signals applied to the Select inputs S0–S2 determine the
mode of operation, as indicated in the Function Select
Table. An extensive listing of input and output levels is
shown in the Truth Table. The circuit performs the arith-
metic functions f or either active HIGH or active LOW o per-
ands, with output levels in the same convention. In the
Subtract operating modes, it is necessary to force a carry
(HIGH for active HIGH operands, LOW for active LOW
operands) into the Cn input of the least significant package.
The Carry Generate (G) and Carry Propagate (P) outputs
supp ly input signals to the 74F182 carry look ahead gener -
ator for exp ansion to longe r word length, as sh own in Fig-
ure 2. Note that an 74F382 ALU is used for the most
significant package. Typical delays for Figure 2 are given in
Figu re 1.
Function Select Table
H = HIGH Voltage Lev el
L = LOW Voltage Level
FIGURE 1. 16-Bit Delay Tabulation
FIGURE 2. 16-Bit Lookahead Carry ALU Expansion
Pin Names Description U.L. Input IIH/IIL
HIGH/LOW Output IOH/IOL
A0–A3A Operand Inputs 1.0/3.0 20 µA/−1.8 mA
B0–B3B Operand Inputs 1.0/3.0 20 µA/−1.8 mA
S0–S2Function Select Inputs 1.0/1.0 20 µA/−0.6 mA
CnCarry Input 1.0/4.0 20 µA/−2.4 mA
GCarry Generate Output (Active LOW) 50/33.3 −1 mA/20 mA
PCarry Propagate Output (Active LOW) 50/33.3 −1 mA/20 mA
F0–F3Function Outputs 50/33.3 −1 mA/20 mA
Select Operation
S0S1S2
LLLClear
H L L B Minus A
L H L A Minus B
HHLA Plus B
LLHA
⊕B
HLHA
+ B
LHHAB
HHHPreset
Path Segment Toward Output
FC
n + 4, OVR
Ai or Bi to P 7.2 ns 7.2 ns
Pi to Cn + ('F1 82) 6.2 ns 6.2 ns
Cn to F 8.1 ns —
Cn or Cn + 4, OVR —8.0 ns
Total Delay 21.5 ns 21.4 ns
3 www.fairchildsemi.com
74F381
Truth Table
H = HIGH Voltage Level
L = LOW Voltage L ev el
X = Immaterial
Inputs Outputs
Function S0S1S2CnAnBnF0F1F2F3G P
CLEAR LLLXXXLLLLLL
LLLHHHHHL
LLHLHHHLL
LHLLLLLHH
B Minus A HLLLHHHHHHHL
HLLLLLLHL
HLHHHHHLL
HHLHLLLHH
HHHLLLLHL
LLLHHHHHL
LLHLLLLHH
LHLLHHHLL
A Minus B LHLLHHHHHHHL
HLLLLLLHL
HLHHLLLHH
HHLHHHHLL
HHHLLLLHL
LLLLLLLHH
LLHHHHHHL
LHLHHHHHL
A Plus B H H L L H H L H H H L L
HLLHLLLHH
HLHLLLLHL
HHLLLLLHL
HHHHHHHLL
XLLLLLLHH
XLHHHHHHH
A ⊕ B LLHXHLHHHHHL
XHHLLLLLL
XLLLLLLHH
XLHHHHHHH
A + B HLHXHLHHHHHH
XHHHHHHHL
XLLLLLLLL
XLHLLLLHH
AB LHHXHLLLLLLL
XHHHHHHHL
XLLHHHHHH
XLHHHHHHH
PRESET H H H X H L H H H H H H
XHHHHHHHL
www.fairchildsemi.com 4
74F381
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagatio n delays.
5 www.fairchildsemi.com
74F381
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: Eith er v oltage lim it or c urrent limit is sufficie nt to protect inputs.
DC Electrical Characteristics
Storage Temperature −65°C to +150°C
Ambient Temper atu re und er Bias −55°C to +125°C
Junction Temperature under Bias −55°C to +150°C
VCC Pin Potential to Ground Pin −0.5V to +7.0V
Input Voltage (Note 2) −0.5V to +7.0V
Input Current (Note 2) −30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with VCC = 0V)
Standa rd Outp ut −0.5V to VCC
3-STATE Output −0.5V to +5.5V
Current Applied to Output
in LOW State (Max) twice the rated IOL (mA)
Free Air Ambient Temperature 0°C to +70°C
Supply Voltage +4.5V to +5.5V
Symbol Parameter Min Typ Max Units VCC Conditions
VIH Input HIGH Voltage 2.0 V Recognized as a HIGH Signal
VIL Input LOW Voltage 0.8 V Recognized as a LOW Signal
VCD Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA
VOH Output HIGH 10% VCC 2.5 VMin
IOH = −1 mA
Voltage 5% VCC 2.7 IOH = −1 mA
VOL Output LOW Voltage 10% VCC 0.5 V Min IOL = 20 mA
IIH Input HIGH 5.0 µAV
IN = 2.7 V
Current
IBVI Input HIGH Current 7.0 µAMaxV
IN = 7.0 V
Breakdown Test
ICEX Output HIGH 50 µAMaxV
OUT = VCC
Leakage Current
VID Input Leakage 4.75 V 0.0 IID = 1.9 µA
Test All Other Pins Grounded
IOD Output Leakage 3.75 µA0.0
VIOD = 150 mV
Circuit Current All Other Pins Grounded
IIL Input LOW Current −0.6 mA Max VIN = 0.5V (Sn)
−1.8 mA Max VIN = 0.5V (An, Bn)
−2.4 mA Max VIN = 0.5V (Cn)
IOS Output Short-Circuit Current −60 −150 mA Max VOUT = 0V
ICC Power Supply Current 59 89 mA Max
www.fairchildsemi.com 6
74F381
AC Electrical Characteristics
Symbol Parameter
TA = +25°CT
A = 0°C to +70°C
Units
VCC = +5.0V VCC = +5.0V
CL = 50 pF CL = 50 pF
Min Typ Max Min Max
tPLH Propagation Delay 2.5 8.1 12.0 2.5 13.0 ns
tPHL Cn to Fi2.5 5.7 8.0 2.5 9.0
tPLH Propagation Delay 4.0 10.4 15.0 4.0 16.0 ns
tPHL Any A or B to Any F 3.5 8.2 11.0 3.5 12.0
tPLH Propagation Delay 4.5 8.3 20.5 4.5 21.5 ns
tPHL Si to Fi4.0 8.2 15.0 4.0 16.0
tPLH Propagation Delay 3.5 6.4 10.0 3.5 11.0 ns
tPHL Ai or Bi to G 3.5 6.8 10.0 3.0 11.0
tPLH Propagation Delay 2.5 7.2 10.5 2.5 11.5 ns
tPHL Ai or Bi to P 3.5 6.5 9.5 3.5 10.5
tPLH Propagation Delay 4.0 7.8 12.0 4.0 13.0 ns
tPHL Si to G or P 4.5 10.2 13.5 4.5 14.5
7 www.fairchildsemi.com
74F381
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M20B
www.fairchildsemi.com 8
74F381
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Sma ll Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
9 www.fairchildsemi.com
74F381 4-Bit Arithmetic Logic Unit
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N20A
Fairchild does not assume an y responsibility fo r use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life suppor t de vices o r syst ems are dev ic es or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instruct ions fo r use pr ovi de d in the l abe ling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A crit ical componen t in any com ponen t of a life s uppor t
device or system whose failure to perform can be rea-
sonabl y e xpec ted to cause th e fa i lure of the l ife s upport
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
