8-BIT OTPROM FAMILY (Am2764A, Am27128A, Am27256) DISTINCTIVE CHARACTERISTICS @ Fast access times as low as 200 ns @ Low-power dissipation @ Both interactive and new Flashrite* programming algo- rithms available Single +5-V power supply @ TTL-compatible inputs and outputs @ +10% power-supply tolerance available @ Programming voltage12.5 V GENERAL DESCRIPTION The Am2764A, Am27128A, and the Am27256 are One- Time Programmable Read-Only Memories (OTPROMs) and are organized as 8 bits per word. The plastic OTPROMs are ideal for volume production. First, because they can be inventoried unprogrammed and used with current-level software revisions; second, there is no win- dow to be covered to prevent light from changing data this could eliminate a manufacturing step and increase the reliability of the system; and third, they are compatible with auto insertion equipment. All standard OTPROMs of- fer access times of 250 ns, allowing operation with high- speed microprocessors without any Wait states. Some of AMD's OTPROMs have access times of as fast as 200 ns. To eliminate bus contention on a multiple-bus microproces- sor system, ali AMD OTPROMs offer separate output enable (OE) and chip enable (CE) controls. All signals are TTL levels, including programming signals. Bit locations may be programmed singly, in blocks, or at random. To reduce programming time, AMDs OTPROMs may be programmed using the Flashrite programming al- gorithm, which offers several fold improvement in program- ming time. BLOCK DIAGRAM DaTA OUTPUTS O= Vee Od9- 0a, O= GND Te o te Ltt OE =} OUTPUT ENABLE |= FJ Pom coe EMBL ce PROG LOGIC OUTPUT BUFFERS DECOOER : -GATING aooness |} ___t beramwanel WPUTS: . ef DECODER : CELL MATRIX 4 +] 6b000231 PRODUCT SELECTOR GUIDE Family Part No. Am2764A, Am27128A, Am27256 Ordering Part No.: +5% Veco 2764A-2 2764A 2764A-4 Tolerance 27128A-2 27128A 2712BA-4 27256-2 27256 27256-4 +10% Voc 2764A-20 2764A-25 Tolerance 27128A-20 27128A-25 27256-20 27256-25 tacc (ns) 200 250 450 tce (ns) 200 250 450 toe (ns) 75 100 150 *Flashrite is a trademark of Advanced Micro Devices, inc. Publication # Bey, Amendment 08159 A /0 6-31 Issue Date: May 1986 ATINVA WOUdLO Lia-8CONNECTION DIAGRAMS Top View wove 1" 28 Vo Ai2z(j2 27 [] (NOTE 5) 473 26 [J] (NOTE 4) AglL]4 2 Ag AsC]5 24[7) Ag A,l]6 allay AgC]7 22] (NOTE 3) AoC]s 2117) Ago Ailes 20 [7] (NOTE 2) AopL_J10 19 [7] DQ? pag lj11 18 [7] Dg pa, (12 17[F) Das DQ, 7] 13 16[) DQ, GND [14 15] DQ3 CD009420 Am2764A | Am27128A | Am27256 Notes: 1 Vpp Vpp Vpp 2 CE TE/PGM 3 OE OE OE 4 NC Aig Aig 5 BGM PGM Ais 6-32LOGIC SYMBOLS Am2764A 13 Ao ~ Aig DQ - 0Q7 et CE 1 FGM il OF p> L$002360 Am27256 Am27128A Ao ~ Aig Dap - Daz p> L$002370 Ag ~ Ata CE/PGM DQy - 07 cp LS002380 6-33ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: A. Device Number B. Speed Option (if applicable) C. Package Type D. Temperature Range E. Optional Processing AM2764A a2 Pp L. OPTIONAL PROCESSING Blank = Standard processing D. TEMPERATURE RANGE C =Commercial (0 to + 70C) C. PACKAGE TYPE P = 28-Pin Plastic DIP (PD 028) J = 32-Pin Rectangular Plastic Leaded Chip Carrier (PL 032)* A. DEVICE NUMBER/DESCRIPTION 8-Bit OTPROM Family Am2764A = 8Kx8 OTPROM Am27128A = 16K x8 OTPROM Am27256 = 32Kx8 OTPROM Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations, to check on newly released valid combinations, and to obtain additional data on AMD's standard military grade products. *Preliminary. Subject to Change. B. SPEED OPTION See Product Selector Guide Valid Combinations +5% Vcc Tolerance AM2764A-2 AM2764A AM2764A-4 AM27128A-2 AM27128A PC, JC AM27128A-4 AM27256-2 AM27256 AM27256-4 +10% Voc Tolerance AM2764A-20 AM2764A-25 AM2?7128A-20 AM27128A-25 PC, JC AM27256-20 AM27256-25 6-34FUNCTIONAL DESCRIPTION Programming the 8-Bit OTPROMs Upon delivery, or after each erasure, the OTPROM has all bits in the "1", or HIGH state. Zeros (''Os'') are loaded into the OTPROM through the procedure of programming. The programming mode is entered when a voltage greater than 12.0, but less than 13.3 V, is applied to the Vpp pin and PGM (CE/PGM for 256K) is low. The data to be programmed is applied 8 bits in parallel to the Data I/O (DQp,) pins. The flowcharts (Figures 1 and 2) show AMD's Flashrite pro- gramming and interactive programming algorithms. The Flashrite programming algorithm improves the programming time by several folds as compared to the interactive algorithm. The AMD Flashrite programming algorithm reduces program- ming time by using initial 100 ys pulses followed by a byte verification to determine whether the byte has been success- fully programmed. If the data does not verify, an additional pulse is applied for a maximum of 25 pulses. This process is repeated while sequencing through each address of the OTPROM. The Flashrite programming algorithm is programmed and verified at Vcc = 6.25 V and Vpp = 13.0 V. After the final address is completed, all bytes are compared to the original data with Vcc = Vpp = 5.25 V. In addition to the Flashrite programming algorithm, OTPROMs are also compatible with AMD's interactive programming algorithm (see Figure 1). The programming mode is entered when a voltage greater than 12.0 V but less than 13.3 V is applied to the Vpp pin. The AMD interactive algorithm uses short (1 ms) program pulses by giving each address only as many pulses as necessary to program the data. After each pulse is applied to a given address, data in that address is verified. If the data does not verify, an additional pulse is applied for a maximum of 25 pulses. This process is repeated while sequencing through each address of the OTPROM. Programming and verification are done at Voc = 6.0 V +5%. The overprogram section of the algorithm programs the entire array by cycling through each address and applying an additional 2-ms program pulse. This section is done at Voc = 5.0 V 45%, After the final address is completed, the entire OTPROM is verified at Voc = 5.0 V +5%, Auto Select Mode The Auto Select mode allows the reading out of a binary code from an OTPROM that will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional in the 25C +5C ambient-temperature range required when programming the OTPROMs. To activate this mode, the programming equipment must force 12.0 V to +0.5 V on address line Ag. Two identifier bytes may then be sequenced from the device outputs by toggling address line Ag from Vi, to Vi. All other address lines must be held at Vij, during Auto Select mode. Byte 0 (Ao = Vi_, DQ9 - DQ7) represents the manufacturer code, and byte 1 (Ag = Vin, DQg - DQ7), the device identifier code. These identifier bytes are given in Table 2. All identifiers for manufacturer and device codes will possess odd parity, with the most significant bit (MSB), DQ7, defined as the parity bit. Read Mode AMD OTPROMs have two control functions, both of which must be logically satisfied in order to obtain data at the outputs. Chip Enable (CE) is the power control and should be used for device selection. Output Enable (OE) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that addresses are stable, address access time (tacc) is equal to the delay from CE to output (tcE). Data is available at the outputs tog after the falling edge of OE, assuming that TE has been LOW and addresses have been stable for at least tacc- tog. Standby Mode AMD OTPROMs have a standby mode which reduces the active power dissipation up to 80%. The OTPROM is placed in the standby mode by applying a TTL HIGH signal to the CE input. When in standby mode, the outputs are in a high- impedance state, independent of the OE input. Output OR-Tieing To accomodate multiple memory connections, a two-line control function is provided to allow for: 1) low-memory power dissipation, and 2) assurance that output-bus contention will not occur. It is recommended that CE be decoded and used as the primary device-selecting function, while OF be made a com- mon connection to all devices in the array, and connected to the Read line from the system control bus. This assures that all deselected memory devices are in their low-power standby mode and that the output pins are only active when data is desired from a particular memory device. Program Inhibit Programming of multiple OTPROMs in parallel with different data is also easily accomplished. Except for CE or PGM, all like inputs (including GE and Vpp) of the parallel OTPROMs may be common. A TTL LOW-level program pulse applied to the PGM (CE/PGM for 256K) input with Vpp between 12.75 V and 13.25 V and CE LOW, will program that OTPROM. A HIGH-level CE or PGM input inhibits the other OTPROMs from being programmed. Program Verify A verify should be performed on the programmed bits to determine that they were correctly programmed. Data for all the OTPROMs should be verified tog after the falling edge of OE, Vpp must be between 12.75 V and 13.25 V for all OTPROMs. System Applications During the switch between active and standby conditions, transient current peaks are produced on the rising and falling edges of Chip Enable. The magnitude of these transient current peaks is dependent on the output capacitance loading of the device. A 0.1-uF ceramic capacitor (high-frequency, low-inherent inductance) should be used on each device between Vcc and GND to minimize transient effects. In addition, to overcome the voltage drop caused by the induc- tive effects of the printed circuit-board traces on OTPROM arrays, a 4.7-uF bulk electrolytic capacitor should be used between Vcc and GND for each eight devices. The location of the capacitor should be close to where the power supply is connected to the array. 6-35FUNCTION TABLES TABLE 1. Am2764A and 27128A MODE SELECT PINS MODE CE | OE | PGM{ Ag | Vpp | OUTPUTS Read L L H x Voc DoutT Output Disable L H H x Voc Hi-Z Standby H x xX X Voc Hi-Z Program L x L x Vep Din Program Verify L L H x Vpp Dout Program Inhibit H x x x Vpp Hi-Z Auto Select L L H VH Voc Code TABLE 2. Am27256 MODE SELECT PINS| GE, MODE PGM | OF Ag | Veep OUTPUTS Read L L Xx Voc Dout Output Disable L H x Voc Hi-Z Standby H X x Voc Hi-Z Program L H x Vpp DIN Program Verify H L x Vpp Dout Program Inhibit H H Xx Vpp Hi-Z Auto Select L L VH Voc Code Key: L = LOW H = HIGH X= Can be either LOW or HIGH Vu = 12.0 V +0.5 V 6-36ABSOLUTE MAXIMUM RATINGS Storage Temperature ............ cc cecceeeeee eee -65 to + 150C Ambient Temperature with Power Applied .-65 to + 135C Supply Voitage with respect to Ground on all Inputs except Ag and Vpp....... +6.50 to 0.6 V $13.50 to -0.6 V Fees cere eeueeeueeneeeeeeateenereeees +13.50 to -0.6 V Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent device failure. Functionality at or above these |imits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. OPERATING RANGES Commercial (C) Devices Temperature (TC).........cceccesseesauseeeseuseees 0 to +70C Supply Voltage (VCC) .......ccceeceeecseeenees (Notes 1 & 2) Notes: 1. For -2, blank, and -4 versions, Vcc = + 4.75 to +525 V. 2. For -20 and -25 versions, Vcc = + 4.50 to +5.50 V. Operating ranges define those limits between which the functionality of the device is guaranteed. DC CHARACTERISTICS over operating range unless otherwise specified (Notes 1, 2, & 4)* Parameter Parameter Symbol Description Test Conditions Min. Max. Units Vou Output HIGH Voltage lon =-400 pA 2.4 v VoL Output LOW Voltage lol = 2.1 mA 0.45 v Viv Input HIGH Voltage 2.0 Voc +1 v Vit Input LOW Voltage -0.1 +0.8 v hy Input Load Current Vin=0 to +5.5 V 10.0 uA ILo Output Leakage Current Vout =0 to -5.5 V 10.0 BA CE = Vin \ Vec Standby Current (Note 6 , 25 mA ICC1 cc y ( ) OE = Vi. Voc Active Current 75 for Am2764A lece Voc Active Current OE = CE= Vic mA for Am27128A 100 and Am27256 Vpp Read Current = Ipp1 (Notes 1 & 5) Vpp = 5.5 V 5 mA Notes: See notes following the Capacitance table on next page. *See the last page of this spec for Group A Subgroup Testing information.CAPACITANCE (Notes 2 & 3) Parameter Parameter Symbol Description Test Conditions Typ. Max. Units CIN Input Capacitance Vin=0 V 4 7 pF Cout Output Capacitance VouT =0 V 8 12 pF Notes: Vcc must be applied simultaneously or before Vpp, and removed simultaneously or after Voc. 1. 2. Typical values are for nominal supply voltages. 3. This parameter is only sampled and not 100% tested. 4. Caution: The OTPROMSs must not be removed from or inserted into a socket or board when Vpp or Vcc is applied. 5. Vpp may be connected to Vcc directly except during programming. The supply would then be the sum of Icc and Ipp. 6. Iccy Max. is 40 mA for -4 devices. KEY TO SWITCHING WAVEFORMS SWITCHING TEST CIRCUITS WAVEFORM INPUTS ouTPuts MUST BE WILL BE STEADY STEADY DEVICE WILL BE UNDER MAY CHANGE CHANGING TE: WW FROMHTOL EROMH TOL st WILL BE MAY CHANGE ih FROML TOH Hanes, WOM DON'T CARE; CHANGING; ANY CHANGE STATE PERMITTED UNKNOWN CENTER HHE DOES NOT LINE 1S HIGH TC003191 APPLY IMPEDANCE OFF STATE KS000010 SWITCHING TEST WAVEFORMS 24V 2.0 20 TEST POINTS < oa 0.8 o4v INPUT ouTeuT WFOO09500 AC Testing: Inputs are driven at 2.4 V for a logic 1 and 0.45 V for a logic 0. Input pulse rise and fall times are <20 ns. 6-38SWITCHING CHARACTERISTICS over operating range unless otherwise specified" (Notes 1 & 3) =-2, -20 Blank, -25 4 Parameter Parameter Test No. Symbol Description Conditions (Note 4) Min, | Max. | Min. | Max. | Min. | Max. | Units 1 tacc nadress to Output | CE = OE = Vin 200 250 450 | ns elay Chip Enable to 2 tce Output Delay 200 250 450 ns Output Enable to 3 tog Output Delay 75 100 150 ns tor Output Enable HIGH 4 {Note 2) to Output Float 9 60 0 60 0 80 ns Output Hold from tOH Addresses, CE, or 5 (Note 2) | OE, whichever Q 9 9 ns occured first Notes: 1. Voc must be applied simultaneously or before Vpp, and removed simultaneously or after Vpp. . This parameter is only sampled and not 100% tested. . Caution: The AMD 8-bit OTPROM Family must not be removed from or inserted into a socket or board when Vpp or Vcc is applied. 4. Output Load: 1 TTL gate and C, = 100 pF, Input Rise and Fall Times: <20 ns, Input Pulse Levels: 0.45 to 2.4 V, Timing Measurement Reference Level Inputs: 1 V and 2 V Outputs: 0.8 V and 2 V. See the last page of this spec for Group A Subgroup Testing information. on SWITCHING WAVEFORMS 24 1 ee ee ADDRESSES AopReSSES 08 oa 0.48 ee oe ee Lf be. 'ace | (NOTE 1) ono HI-Z Hi-Z OuTPUT VALIO i output WA 2 Notes: 1. OE may be delayed up to tacc-tog after the falling edge of OF without impact on tacc. 2. tor is specified from OE or CE, whichever occurs first. tog we 'OF wl hf (NOTE 1) rc (NOTE 2} | WFO001321 6-39PROGRAMMING This section covers Identifier bytes, Interactive Programming Flowchart, and Programming DC and AC Switching Programming Characteristics. START ADDRESS = FIRST LOCATION Veo = 6.0V Vee = 13.0 V PROGRAMONE 1 ms PULSE INCREMENT X INTERACTIVE SECTION YES PASS LAST ADDRESS? Y ES ADDRESS = FIRST LOCATION Veco = 5.0 V Vee = 13.0 V PROGRAM ONE 2.0 ms PULSE INCREMENT ADDRESS LAST ADDRESS? YES Vec = Vep = 5.0V 45% INCREMENT ADDRESS OVERPROGRAM SECTION VERIFY SECTION DEVICE FAILED VERIFY ALL BYTE PASS DEVICE PASSED PF000251 Figure 1. interactive Programming Flow Chart 6-40INTER, START ADORESS = FIRST LOCATION Veco = 625V Vee = 13.0 V CTIVE SECTION VERIFY SECTION INCREMENT ADDRESS Figure 2. PROGRAM ONE 100 ms PULSE INCREMENT X LAST ADDRESS? Voc = Vpp = 5.25 V DEVICE FAILED PASS DEVICE PASSED PF001725 Flashrite Programming Flow Chart 6-41TABLE 3. IDENTIFIER BYTES Pins Hex identifier Ag | DQ7 | DGg | DQs | DQ, | DQ3 | DQ2 | DQ; DQo | Data Manufacturer Code Vit 0 0 0 0 0 0 0 1 01 Am2764A Device Code Vin 0 0 0 0 1 0 0 0 08 Am27128A Device Code Vin 1 0 0 0 1 0 0 1 89 Am27256 Device Code ViH 0 0 0 0 0 1 0 0 04 Notes: 1. Ag = 12.0 V +0.5 V 2. AH other Address Lines = CE = OE = Vi_ 3. For Am2764A, PGM = Vin 4. For Am27256, A14 = Don't Care INTERACTIVE PROGRAMMING ALGORITHM DC PROGRAMMING CHARACTERISTICS Parameter Parameter Symboi Description Test Conditions Min. Max. Units lu Input Current (All Inputs) Vin = ViL or Vin 10.0 BA Vit Input LOW Level (All Inputs) -0.1 0.8 v VIH Input HIGH Level 2.0 Voc+1 Vv VoL Output LOW Voltage during Verity lo. = 2.1 mA 45 Vv VOH Output LOW Voltage during Verify lon =-400 yA 2.4 v loca Voc Supply Current ee 7s mA (Program and Verify) and An27256 400 lpp3 Vpp Supply Current (Program) ce Vibes /PGM 30 mA Vio tee 15 | 125 V Vep Interactive Programming Algorithm 12.0 13.3 v Flashrite Programming Algorithm 12.75 13.25 v Voc Interactive Programming Algorithm 5.75 6.25 v Flashrite Programming Algorithm 6.0 6.5 v 6-42PROGRAMMING AC CHARACTERISTICS (Notes 1, 2, 3, and 4) Parameter Parameter No. Symbols Description Min. Max. Units 1 tas Address Setup Time 2 US 2 toes OE Setup Time 2 us 3 tps Data Setup Time 2 us 4 taH Address Hold Time 2 us 5 toH Data Hold Time 2 4S 6 tor Chip Enable to Output Float Delay 0 130 us 7 tves Vpp Setup Time 2.0 ys 8 tvcs Voc Setup Time 2 uS PGM Initial Program Pulse Width (Interactive) 95 1.05 ms 9 Pw PGM Initial Program Pulse Width (Flashrite) 95 105 us 10 topw PGM Overprogram Pulse Width (Note 3,5) 1.95 2.05 ms 11 tces CE Setup Time 2 us 12 toe Data Valid from OE 150 ns Notes: 1. Ta = +25C +5C; see DC Programming Characteristics for Vcc and Vpp voltages. 2. 3. 4. 5. voltage transients which may damage the device. Voc must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. When programming the OTPROM family, a 0.1-uF capacitor is required across Vpp and ground to suppress spurious Programming characteristics are guidelines which must be followed. They are not 100% tested to worst-case limits. Interactive programming algorithm only. 6-43INTERACTIVE PROGRAMMING ALGORITHM WAVEFORMS Am2764A and Am27128A (Notes 1 and 2) PROGRAM WN STABLE DATA OUT VALIO WFO000552 Am27256 (Notes 1 and 3) PROGRAM Pecan DATA DATA IN STABLE DATA OUT VALID 5 WFO000582 Notes: 1. The input timing reference level is 0.8 V for Vi_ and 2 V for ViH. 2. toe and tp are characteristics of the device, but must be accommodated by the programmer. 3. tog and tprp are characteristics of the device, but must be accommodated by the programmer. 6-44GROUP A SUBGROUP TESTING DC CHARACTERISTICS Parameter Symbol Subgroups* Vou 1,2,3 VoL ViH Vit N wo Slot worpalaolwolwo]a loca 'pP4 Ipp2 Cin Cout Cina Cina 4 *For DC Programming Characteristics, only Subgroup 1 applies. 8 ajafotfalo/ajafaja PLA LAT YN NIN YEP INI NIN SWITCHING CHARACTERISTICS Parameter No. Symbol Subgroups 1 tacc 9, 10, 11 2 tce 9, 10, 11 3 toe 9, 10, 11 4 tor 9 5 toH 9 MILITARY BURN-IN Military burn-in is in accordance with the current revision of MIL-STD-883, Test Method 1015, Conditions A through E. Test conditions are selected at AMD's option. 6-45