PIC18F/LF1XK50
DS41350D-page 416 Preliminary 2010 Microchip Technology Inc.
Time-out in Various Situations (table) ..............................283
Timer0 ..............................................................................101
Associated Registers ...............................................103
Operation ................................................................. 102
Overflow Interrupt ....................................................103
Prescaler ..................................................................103
Prescaler Assignment (PSA Bit) ..............................103
Prescaler Select (T0PS2:T0PS0 Bits) .....................103
Prescaler. See Prescaler, Timer0.
Reads and Writes in 16-Bit Mode ............................ 102
Source Edge Select (T0SE Bit) ................................ 102
Source Select (T0CS Bit) ......................................... 102
Specifications ...........................................................388
Switching Prescaler Assignment ..............................103
Timer1 ..............................................................................105
16-Bit Read/Write Mode ........................................... 107
Associated Registers ...............................................110
Interrupt .................................................................... 108
Operation ................................................................. 106
Oscillator .......................................................... 105, 107
Oscillator Layout Considerations ............................. 108
Overflow Interrupt ....................................................105
Resetting, Using the CCP Special Event Trigger ..... 108
Specifications ...........................................................388
TMR1H Register ...................................................... 105
TMR1L Register ....................................................... 105
Use as a Real-Time Clock .......................................109
Timer2 ..............................................................................111
Associated Registers ...............................................112
Interrupt .................................................................... 112
Operation ................................................................. 111
Output ......................................................................112
Timer3 ..............................................................................113
16-Bit Read/Write Mode ........................................... 115
Associated Registers ...............................................116
Operation ................................................................. 114
Oscillator .......................................................... 113, 115
Overflow Interrupt ............................................ 113, 115
Special Event Trigger (CCP) .................................... 116
TMR3H Register ...................................................... 113
TMR3L Register ....................................................... 113
Timing Diagrams
A/D Conversion ........................................................390
Acknowledge Sequence .......................................... 174
Asynchronous Reception ......................................... 190
Asynchronous Transmission .................................... 187
Asynchronous Transmission (Back to Back) ........... 187
Auto Wake-up Bit (WUE) During Normal Operation 201
Auto Wake-up Bit (WUE) During Sleep ................... 201
Automatic Baud Rate Calculator .............................. 199
Baud Rate Generator with Clock Arbitration ............ 168
BRG Reset Due to SDA Arbitration During
Start Condition .................................................177
Brown-out Reset (BOR) ........................................... 386
Bus Collision During a Repeated Start Condition
(Case 1) ...........................................................178
Bus Collision During a Repeated Start Condition
(Case 2) ...........................................................179
Bus Collision During a Start Condition (SCL = 0) .... 177
Bus Collision During a Stop Condition (Case 1) ...... 180
Bus Collision During a Stop Condition (Case 2) ...... 180
Bus Collision During Start Condition (SDA only) ..... 176
Bus Collision for Transmit and Acknowledge ........... 175
CLKOUT and I/O ...................................................... 385
Clock Synchronization .............................................161
Clock Timing ............................................................ 381
Clock/Instruction Cycle .............................................. 33
Comparator Output .................................................. 225
Enhanced Capture/Compare/PWM (ECCP) ............ 389
Fail-Safe Clock Monitor (FSCM) ................................ 27
First Start Bit Timing ................................................ 169
Full-Bridge PWM Output .......................................... 126
Half-Bridge PWM Output ................................. 124, 132
I2C Bus Data ............................................................ 396
I2C Bus Start/Stop Bits ............................................ 395
I2C Master Mode (7 or 10-Bit Transmission) ........... 172
I2C Master Mode (7-Bit Reception) .......................... 173
I2C Slave Mode (10-Bit Reception, SEN = 0) .......... 156
I2C Slave Mode (10-Bit Reception, SEN = 1) .......... 163
I2C Slave Mode (10-Bit Transmission) .................... 157
I2C Slave Mode (7-bit Reception, SEN = 0) ............ 154
I2C Slave Mode (7-Bit Reception, SEN = 1) ............ 162
I2C Slave Mode (7-Bit Transmission) ...................... 155
I2C Slave Mode General Call Address Sequence
(7 or 10-Bit Address Mode) ............................ 164
I2C Stop Condition Receive or Transmit Mode ........ 174
Internal Oscillator Switch Timing ............................... 23
PWM Auto-shutdown
Auto-restart Enabled ........................................ 131
Firmware Restart ............................................. 130
PWM Direction Change ........................................... 127
PWM Direction Change at Near 100% Duty Cycle .. 128
PWM Output (Active-High) ...................................... 122
PWM Output (Active-Low) ....................................... 123
Repeat Start Condition ............................................ 170
Reset, WDT, OST and Power-up Timer .................. 386
Send Break Character Sequence ............................ 202
Slave Synchronization ............................................. 145
Slow Rise Time (MCLR Tied to VDD,
VDD Rise > TPWRT) .......................................... 285
SPI Master Mode (CKE = 1, SMP = 1) .................... 393
SPI Mode (Master Mode) ......................................... 144
SPI Mode (Slave Mode, CKE = 0) ........................... 146
SPI Mode (Slave Mode, CKE = 1) ........................... 146
SPI Slave Mode (CKE = 0) ...................................... 394
SPI Slave Mode (CKE = 1) ...................................... 394
Synchronous Reception (Master Mode, SREN) ...... 206
Synchronous Transmission ..................................... 204
Synchronous Transmission (Through TXEN) .......... 204
Time-out Sequence on POR w/PLL Enabled
(MCLR Tied to VDD) ........................................ 285
Time-out Sequence on Power-up (MCLR
Not Tied to VDD, Case 1) ................................. 284
Time-out Sequence on Power-up (MCLR
Not Tied to VDD, Case 2) ................................. 284
Time-out Sequence on Power-up (MCLR
Tied to VDD, VDD Rise < TPWRT) ..................... 284
Timer0 and Timer1 External Clock .......................... 388
Transition for Entry to Sleep Mode .......................... 239
Transition for Wake from Sleep (HSPLL) ................ 239
Transition Timing for Entry to Idle Mode .................. 240
Transition Timing for Wake from Idle to Run Mode . 240
USART Synchronous Receive (Master/Slave) ........ 392
USART Synchronous Transmission (Master/Slave) 392
Timing Diagrams and Specifications
A/D Conversion Requirements ................................ 390
PLL Clock ................................................................ 384
Timing Parameter Symbology ......................................... 380
Timing Requirements
I2C Bus Data ............................................................ 397