GIGABIT PRODUCTS BRIEF NOV3111 /NOV3211 /NOV3311 SINGLE PORT SERDES FOR 1.25Gbps ETHERNET & 1.06Gbps FIBRE CHANNEL 1. GENERAL DESCRIPTION Novanet Semiconductor's Gigabit PHY solutions are based on the company's proprietary Hi-PHY clock and data recovery technology. Novanet Semiconductor's solutions for Gigabit applications use digital, process independent CMOS technologies and are available for vertical and horizontal integration. SerDes for 1.25Gbps Ethernet & 1.06Gbps Fibre Channel The NOV3111, NOV3211 and NOV3311 provide low-cost, lowpower physical layer solutions for 1.25Gbps Ethernet, 1.06Gbps Fibre Channel or proprietary link interfaces. They incorporate a transmitter and receiver function onto a single IC and facilitate high speed serial transmission of data over Fiber Optic, Coax or Twinax interfaces. These Gigabit SerDes products conform to the requirements of the IEEE 802.3z Gigabit Ethernet specification and the ANSI X3T11 Fibre Channel specification. PRODUCT FEATURES INCLUDE: q Compliant with IEEE 802.3z Gigabit Ethernet standard q Compliant with ANSI X3T11 Fibre Channel specification q Supports 1.25Gbps Gigabit Ethernet and 1.06Gbps Fibre Channel line rate and half rate operation q Proprietary Hi-PHY clock and data recovery q 10-bit parallel data TTL compatible I/O q Low power consumption q q Drives Twinax cable directly 2.5/3.3 Volt, 0.25 CMOS technology APPLICATIONS q Gigabit Ethernet Switches and NICS q Ethernet Switches providing Gigabit uplinks q Fibre Channel Switches, Hubs and NICs q High speed proprietary interfaces q High speed backplane interconnect GIGABIT PRODUCTS BRIEF Single Port SerDes Block Diagram The SerDes port transmitter and receiver provide serialization and deserialization functions for block encoded data to implement Gigabit rate interfaces. The sequence of operation of a Gigabit SerDes port is as follows: Transmitter 1. 10 bit parallel input 2. Parallel-to-serial conversion 3. Serial PECL output Receiver 1. Clock and data recovery from serial input 2. Serial-to-parallel conversion 3. Frame detection (comma detect) 4. 10-bit parallel output Loopback Local loopback for off-line testing and diagnostics LCK_REF TX+ TX[0:9] EWRAP RBC1 RX[0:9] EN_CDET COM_DET SIG_DET Output Mux TX PLL & CLK_GEN TBC RBC0 Parallel To Serial INPUT LATCH 1/2 TX- RATSEL Receive PLL & Clock Recovery Serial To Paralel & Byte Sync RX+ Input Mux Signal Detect RX-