4-51
File Number
2286.3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
http://www.intersil.com or 407-727-9207 |Copyright © Intersil Corporation 1999
IRFD9220
0.6A, 200V, 1.500 Ohm, P-Channel Power
MOSFET
This P-Channel enhancement mode silicon gate power field
effect transistor is an advanced power MOSFET designed,
tested, and guaranteed to withstand a specified level of
energy in the breakdown avalanche mode of operation. All of
these power MOSFETs are designed for applications such
as switching regulators, switching convertors, motor drivers,
relay drivers, and drivers for high power bipolar switching
transistors requiring high speed and low gate drive power.
These types can be operated directly from integrated
circuits.
Formerly developmental type TA17502.
Features
• 0.6A, 200V
•r
DS(ON) = 1.500Ω
• Single Pulse Avalanche Energy Rated
• SOA is Power Dissipation Limited
• Nanosecond Switching Speeds
• Linear Transfer Characteristics
• High Input Impedance
Symbol
Packaging
HEXDIP
Ordering Information
PART NUMBER PACKAGE BRAND
IRFD9220 HEXDIP IRFD9220
NOTE: When ordering, use the entire part number.
G
D
S
SOURCE
GATE
DRAIN
Data Sheet July 1999
4-52
Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified IRFD9220 UNITS
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS -200 V
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDGR -200 V
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID-0.6 A
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM -4.8 A
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS ±20 V
Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD1.0 W
Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.008 W/oC
Single Pulse Avalanche Energy Rating (Note 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS 290 mJ
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG -55 to 150 oC
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T
L
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tpkg 300
260
oC
oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 125oC
Electrical Specifications TC = 25oC, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Drain to Source Breakdown Voltage BVDSS ID = -250µA, VGS = 0V, (Figure 9) -200 - - V
Gate to Threshold Voltage VGS(TH) VGS = VDS, ID = -250µA -2.0 - -4.0 V
Zero Gate Voltage Drain Current IDSS VDS = Rated BVDSS, VGS = 0V - - -25 µA
VDS = 0.8 x Rated BVDSS, VGS = 0V, TC = 125oC - - -250 µA
On-State Drain Current (Note 2) ID(ON) VDS > ID(ON) x rDS(ON)MAX, VGS = -10V -0.6 - - A
Gate to Source Leakage Current IGSS VGS = ±20V - - ±500 nA
On Resistance (Note 2) rDS(ON) ID = -0.3A, VGS = -10V, (Figures 7, 8) - 1.000 1.500 Ω
Forward Transconductance (Note 2) gfs VDS < 50V, ID = -0.3A, (Figure 11) 0.6 1.0 - S
Turn-On Delay Time td(ON) VDD = 0.5 x Rated BVDSS, ID≈ 0.6A, RG = 9.1Ω
VGS = -10V, (Figures 16, 17)
RL = 165Ωfor VDD = 100V
MOSFET Switching Times are Essentially Indepen-
dent of Operating Temperature.
-1540ns
Rise Time tr-2550ns
Turn-Off Delay Time td(OFF) - 80 120 ns
Fall Time tf-5075ns
Total Gate Charge
(Gate to Source + Gate to Drain) Qg(TOT) VGS = -10V, ID = -0.6A, VDS = 0.8 x Rated BVDSS,
IG(REF) = 1.5mA, (Figures 13, 18, 19)
Gate Charge is Essentially Independent of Operating
Temperature
-1622nC
Gate to Source Charge Qgs -10-nC
Gate to Drain “Miller” Charge Qgd -4-nC
Input Capacitance CISS VDS = -25V, VGS = 0V, f = 1MHz, (Figure 10) - 350 - pF
Output Capacitance COSS - 100 - pF
Reverse Transfer Capacitance CRSS -30-pF
Internal Drain Inductance LDMeasured From the Drain
Lead, 2.0mm (0.08in) From
Header to Center of Die
Modified MOSFET
Symbol Showing the In-
ternal Devices
Inductances
- 4.0 - nH
Internal Source Inductance LSMeasured From the Source
Lead, 0.2mm (0.08in) From
Header to Source Bonding
Pad
- 6.0 - nH
Thermal Resistance Junction to Ambient RθJA Typical Socket Mount - - 120 oC/W
LS
LD
G
D
S
IRFD9220
4-53
Source to Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Continuous Source to Drain Current ISD ModifiedMOSFETSymbol
Showing the Integral Re-
verse P-N Junction Diode
- - -0.6 A
Pulse Source to Drain Current
(Note 3) ISDM - - -4.8 A
Source to Drain Diode Voltage (Note 2) VSD TC = 25oC, ISD = -0.6A, VGS = 0V (Figure 12) - - -1.5 V
Reverse Recovery Time trr TJ = 150oC, ISD = -0.6A, dISD/dt = 100A/µs - 150 - ns
Reverse Recovery Charge QRR TJ = 150oC, ISD = -0.6A, dISD/dt = 100A/µs - 0.5 - µC
NOTES:
2. Pulse test: pulse width ≤ 300µs, duty cycle ≤2%.
3. Repetitive rating: pulse width limited by maximum junction temperature.
4. VDD = 25V, starting TJ= 25oC, L = 1210mH, RG= 25Ω, Peak IAS = 0.6A (Figures 14, 15).
Typical Performance Curves
Unless Otherwise Specified
FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT
TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
AMBIENT TEMPERATURE
FIGURE 3. FORWARD BIAS SAFE OPERATING AREA FIGURE 4. OUTPUT CHARACTERISTICS
G
D
S
TA, AMBIENT TEMPERATURE (oC)
POWER DISSIPATION MULTIPLIER
00 25 50 75 100 150
0.2
0.4
0.6
0.8
1.0
1.2
125
-0.2
0
25 50 75
IDS, DRAIN TO SOURCE CURRENT (A)
TA, AMBIENT TEMPERATURE (oC)
-0.6
100
-0.4
125 150
-0.2 -1.0 -10 -100 -500
-10
-1.0
-0.1
-0.01
-0.002
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
10µs
100µs
1ms
10ms
100ms
DC
SINGLE PULSE
TC = 25oC
OPERATION IN THIS AREA
IS LIMITED BY rDS(ON)
TJ = MAX RATED
ID, DRAIN CURRENT (A)
0 -10 -20 -30 -40
-1
-2
-3
-4
-5
-50
-9V VGS = -7V
VGS = -6V
VGS = -5V
VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS = -4V
0
VGS = -8V
-10V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX.
IRFD9220
4-54
FIGURE 5. SATURATION CHARACTERISTICS FIGURE 6. TRANSFER CHARACTERISTICS
NOTE: Effect of 2.0µs pulse is minimal.
FIGURE 7. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT FIGURE 8. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 9. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE FIGURE 10. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
Typical Performance Curves
Unless Otherwise Specified (Continued)
0
-1
0-1 -2 -3 -5
-2
-3
IDS, DRAIN TO SOURCE CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
-4
-4
-5
VGS = -10V
VGS = -9V
PULSE DURATION = 80µs
VGS = -4V
VGS = -5V
VGS = -6V
VGS = -8V
VGS = -7V
DUTY CYCLE = 0.5% MAX.
-5
-4
-3
-2
-1
00 -2-4 -6-8-10
VGS, GATE TO SOURCE VOLTAGE (V)
IDS(ON), DRAIN TO SOURCE CURRENT (A)
TJ = 125oC
TJ = 25oC
TJ = -55oC
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDS ≥ID(ON) x rDS(ON) MAX
0-1 -2 -3 -4
rDS(ON), DRAIN TO SOURCE
ID, DRAIN CURRENT (A) -5
1.0
0
0.5
VGS = -20V
2.0µs PULSE TEST
1.5
VGS = -10V
ON RESISTANCE (Ω)
NORMALIZED DRAIN TO SOURCE
-2.5
-1.5
-1.0
-0.5
0-40 0 40
TJ, JUNCTION TEMPERATURE (oC)
120 160
-2.0
80
ON RESISTANCE
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX.
VGS = -10V, ID = -0.3A
1.15
1.00
0.95
0.90
0.85
-80 -40 0 40
TJ, JUNCTION TEMPERATURE (oC)
NORMALIZED DRAIN TO SOURCE
80 120 160
1.05
1.10
BREAKDOWN VOLTAGE
ID = 250µA500
100
00-20 -50
C, CAPACITANCE (pF)
300
VDS, DRAIN TO SOURCE VOLTAGE (V)
400
200
CISS
COSS
CRSS
-10 -30 -40
CISS = CGS + CGD
CRSS = CGD
COSS = CDS + CGD
VGS = 0V, f = 1MHz
IRFD9220
4-55
FIGURE 11. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 12. SOURCE TO DRAIN DIODE VOLTAGE
FIGURE 13. GATE TO SOURCE VOLTAGE vs GATE CHARGE
Test Circuits and Waveforms
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
Typical Performance Curves
Unless Otherwise Specified (Continued)
4
3
2
1
00 -1-2-3-4-5
ID, DRAIN CURRENT (A)
gfs, TRANSCONDUCTANCE (S)
TJ = -55oC
TJ = 25oC
TJ = 125oC
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX.
VDS ≥ ID(ON) x rDS(ON)MAX
-0.4 -1.0 -1.2 -1.6 -1.8-0.6 VSD, SOURCE TO DRAIN VOLTAGE (V)
-0.8 -1.4
-0.1
-1.0
-10
ISD, DRAIN CURRENT (A)
-100
TJ = 25oC
TJ = 150oC
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX.
0
-5
-10
0481216
Qg(TOT) , TOTAL GATE CHARGE (nC)
VGS, GATE TO SOURCE (V)
ID = -3.6A
20
-15
-20
VDS = -40V
VDS = -100V
VDS = -160V
tP
0.01Ω
L
IAS
+
-
VDS
VDD
RG
DUT
VARY tP TO OBTAIN
REQUIRED PEAK IAS
0V
VGS
VDD
VDS
BVDSS
tP
IAS
tAV
0
IRFD9220
4-56
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is gr anted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see w eb site http://www.intersil.com
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FIGURE 16. SWITCHING TIME TEST CIRCUIT FIGURE 17. RESISTIVE SWITCHING WAVEFORMS
FIGURE 18. GATE CHARGE TEST CIRCUIT FIGURE 19. GATE CHARGE WAVEFORMS
Test Circuits and Waveforms
(Continued)
VGS
RL
RG
DUT
+
-VDD
td(ON)
tr
90%
10%
VDS 90%
tf
td(OFF)
tOFF
90%
50%
50%
10%
PULSE WIDTH
VGS
tON
10%
0
0
0.3µF
12V
BATTERY 50kΩ
+VDS
S
DUT
D
G
IG(REF)
0
(ISOLATED
-VDS
0.2µF
CURRENT
REGULATOR
ID CURRENT
SAMPLING
IG CURRENT
SAMPLING
SUPPLY)
RESISTOR RESISTOR
DUT
Qg(TOT)
Qgd
Qgs
VDS
0
VGS
VDD
0
IG(REF)
IRFD9220
