Features
Single 2.3V - 3.6V or 2.7V - 3.6V Supply
Serial Peripheral Interface (SPI) Compatible
Supports SPI Modes 0 and 3
66 MHz Maximum Operating Frequency
Clock-to-Output (tV) of 6 ns Maximum
Flexible, Optimized Erase Architecture for Code + Data Storage Applications
Uniform 4-Kbyte Block Erase
Uniform 32-Kbyte Block Erase
Uniform 64-Kbyte Block Erase
Full Chip Erase
Individual Sector Protection with Global Protect/Unprotect Feature
Four Sectors of 64 Kbytes Each
Hardware Controlled Locking of Protected Sectors via WP Pin
128-Byte Programmable OTP Security Register
Flexible Programming
Byte/Page Program (1 to 256 Bytes)
Fast Program and Erase Times
1.0 ms Typical Page Program (256 Bytes) Time
50 ms Typical 4-Kbyte Block Erase Time
250 ms Typical 32-Kbyte Block Erase Time
450 ms Typical 64-Kbyte Block Erase Time
Automatic Checking and Reporting of Erase/Program Failures
JEDEC Standard Manufacturer and Device ID Read Methodology
Low Power Dissipation
7 mA Active Read Current (Typical at 20 MHz)
15 μA Deep Power-Down Current (Typical)
Endurance: 100,000 Program/Erase Cycles
Data Retention: 20 Years
Complies with Full Industrial Temperature Range
Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options
8-lead SOIC (150-mil Wide)
8-pad Ultra Thin DFN (5 x 6 x 0.6 mm)
1. Description
The AT25DF021 is a serial interface Flash memory device designed for use in a wide
variety of high-volume consumer based applications in which program code is shad-
owed from Flash memory into embedded or external RAM for execution. The flexible
erase architecture of the AT25DF021, with its erase granularity as small as 4 Kbytes,
makes it ideal for data storage as well, eliminating the need for additional data storage
EEPROM devices.
2-Megabit
2.3-volt or
2.7-volt
Minimum
SPI Serial Flash
Memory
AT25DF021
(Not Recommended
for New Designs)
3677F–DFLASH–5/2013
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AT25DF021
The physical sectoring and the erase block sizes of the AT25DF021 have been optimized to
meet the needs of today's code and data storage applications. By optimizing the size of the
physical sectors and erase blocks, the memory space can be used much more efficiently.
Because certain code modules and data storage segments must reside by themselves in their
own protected sectors, the wasted and unused memory space that occurs with large sectored
and large block erase Flash memory devices can be greatly reduced. This increased memory
space efficiency allows additional code routines and data storage segments to be added while
still maintaining the same overall device density.
The AT25DF021 also offers a sophisticated method for protecting individual sectors against
erroneous or malicious program and erase operations. By providing the ability to individually pro-
tect and unprotect sectors, a system can unprotect a specific sector to modify its contents while
keeping the remaining sectors of the memory array securely protected. This is useful in applica-
tions where program code is patched or updated on a subroutine or module basis, or in
applications where data storage segments need to be modified without running the risk of errant
modifications to the program code segments. In addition to individual sector protection capabili-
ties, the AT25DF021 incorporates Global Protect and Global Unprotect features that allow the
entire memory array to be either protected or unprotected all at once. This reduces overhead
during the manufacturing process since sectors do not have to be unprotected one-by-one prior
to initial programming.
The device also contains a specialized OTP (One-Time Programmable) Security Register that
can be used for purposes such as unique device serialization, system-level Electronic Serial
Number (ESN) storage, locked key storage, etc.
Specifically designed for use in 2.5-volt or 3-volt systems, the AT25DF021 supports read, pro-
gram, and erase operations with a supply voltage range of 2.3V to 3.6V or 2.7V to 3.6V. No
separate voltage is required for programming and erasing.
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AT25DF021
2. Pin Descriptions and Pinouts
Table 2-1. Pin Descriptions
Symbol Name and Function
Asserted
State Type
CS
CHIP SELECT: Asserting the CS pin selects the device. When the CS pin is deasserted, the
device will be deselected and normally be placed in standby mode (not Deep Power-Down
mode), and the SO pin will be in a high-impedance state. When the device is deselected,
data will not be accepted on the SI pin.
A high-to-low transition on the CS pin is required to start an operation, and a low-to-high
transition is required to end an operation. When ending an internally self-timed operation
such as a program or erase cycle, the device will not enter the standby mode until the
completion of the operation.
Low Input
SCK
SERIAL CLOCK: This pin is used to provide a clock to the device and is used to control the
flow of data to and from the device. Command, address, and input data present on the SI pin
is always latched in on the rising edge of SCK, while output data on the SO pin is always
clocked out on the falling edge of SCK.
- Input
SI
SERIAL INPUT: The SI pin is used to shift data into the device. The SI pin is used for all data
input including command and address sequences. Data on the SI pin is always latched in on
the rising edge of SCK.
Data present on the SI pin will be ignored whenever the device is deselected (CS is
deasserted).
- Input
SO
SERIAL OUTPUT: The SO pin is used to shift data out from the device. Data on the SO pin
is always clocked out on the falling edge of SCK.
The SO pin will be in a high-impedance state whenever the device is deselected (CS is
deasserted).
- Output
WP
WRITE PROTECT: The WP pin controls the hardware locking feature of the device. Please
refer to “Protection Commands and Features” on page 12 for more details on protection
features and the WP pin.
The WP pin is internally pulled-high and may be left floating if hardware controlled protection
will not be used. However, it is recommended that the WP pin also be externally connected
to VCC whenever possible.
Low Input
HOLD
HOLD: The HOLD pin is used to temporarily pause serial communication without
deselecting or resetting the device. While the HOLD pin is asserted, transitions on the SCK
pin and data on the SI pin will be ignored, and the SO pin will be in a high-impedance state.
The CS pin must be asserted, and the SCK pin must be in the low state in order for
a Hold condition to start. A Hold condition pauses serial communication only and
does not have an effect on internally self-timed operations such as a program or
erase cycle. Please refer to “Hold” on page 29 for additional details on the Hold
operation.
The HOLD pin is internally pulled-high and may be left floating if the Hold function will not be
used. However, it is recommended that the HOLD pin also be externally connected to VCC
whenever possible.
Low Input
VCC
DEVICE POWER SUPPLY: The VCC pin is used to supply the source voltage to the device.
Operations at invalid VCC voltages may produce spurious results and should not be
attempted.
- Power
GND GROUND: The ground reference for the power supply. GND should be connected to the
system ground. - Power
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AT25DF021
3. Block Diagram
Figure 3-1. Block Diagram
4. Memory Array
To provide the greatest flexibility, the memory array of the AT25DF021 can be erased in four lev-
els of granularity including a full chip erase. In addition, the array has been divided into physical
sectors of uniform size, of which each sector can be individually protected from program and
erase operations. The size of the physical sectors is optimized for both code and data storage
applications, allowing both code and data segments to reside in their own isolated regions. The
Memory Architecture Diagram illustrates the breakdown of each erase level as well as the
breakdown of each physical sector.
Figure 2-1. 8-SOIC Top View Figure 2-2. 8-UDFN (Top View)
1
2
3
4
8
7
6
5
CS
SO
WP
GND
VCC
HOLD
SCK
SI
CS
SO
WP
GND
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
FLASH
MEMORY
ARRAY
Y-GATING
CS
SCK
SO
SI
Y-DECODER
ADDRESS LATCH
X-DECODER
I/O BUFFERS
AND LATCHES
CONTROL AND
PROTECTION LOGIC
SRAM
DATA BUFFER
WP
INTERFACE
CONTROL
AND
LOGIC
HOLD
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AT25DF021
Figure 4-1. Memory Architecture Diagram
Internal Sectoring for 64KB 32KB 4KB 1-256 Byte
Sector Protection Block Erase Block Erase Block Erase Page Program
Function (D8h Command) (52h Command) (20h Command) (02h Command)
4KB 03FFFFh 03F000h 256 Bytes 03FFFFh 03FF00h
4KB 03EFFFh 03E000h 256 Bytes 03FEFFh 03FE00h
4KB 03DFFFh 03D000h 256 Bytes 03FDFFh 03FD00h
4KB 03CFFFh 03C000h 256 Bytes 03FCFFh 03FC00h
4KB 03BFFFh 03B000h 256 Bytes 03FBFFh 03FB00h
4KB 03AFFFh 03A000h 256 Bytes 03FAFFh 03FA00h
4KB 039FFFh 039000h 256 Bytes 03F9FFh 03F900h
4KB 038FFFh 038000h 256 Bytes 03F8FFh 03F800h
4KB 037FFFh 037000h 256 Bytes 03F7FFh 03F700h
4KB 036FFFh 036000h 256 Bytes 03F6FFh 03F600h
4KB 035FFFh 035000h 256 Bytes 03F5FFh 03F500h
4KB 034FFFh 034000h 256 Bytes 03F4FFh 03F400h
4KB 033FFFh 033000h 256 Bytes 03F3FFh 03F300h
4KB 032FFFh 032000h 256 Bytes 03F2FFh 03F200h
4KB 031FFFh 031000h 256 Bytes 03F1FFh 03F100h
4KB 030FFFh 030000h 256 Bytes 03F0FFh 03F000h
4KB 02FFFFh 02F000h 256 Bytes 03EFFFh 03EF00h
4KB 02EFFFh 02E000h 256 Bytes 03EEFFh 03EE00h
4KB 02DFFFh 02D000h 256 Bytes 03EDFFh 03ED00h
4KB 02CFFFh 02C000h 256 Bytes 03ECFFh 03EC00h
4KB 02BFFFh 02B000h 256 Bytes 03EBFFh 03EB00h
4KB 02AFFFh 02A000h 256 Bytes 03EAFFh 03EA00h
4KB 029FFFh 029000h 256 Bytes 03E9FFh 03E900h
4KB 028FFFh 028000h 256 Bytes 03E8FFh 03E800h
4KB 027FFFh 027000h
4KB 026FFFh 026000h
4KB 025FFFh 025000h
4KB 024FFFh 024000h 256 Bytes 0017FFh 001700h
4KB 023FFFh 023000h 256 Bytes 0016FFh 001600h
4KB 022FFFh 022000h 256 Bytes 0015FFh 001500h
4KB 021FFFh 021000h 256 Bytes 0014FFh 001400h
4KB 020FFFh 020000h 256 Bytes 0013FFh 001300h
256 Bytes 0012FFh 001200h
256 Bytes 0011FFh 001100h
256 Bytes 0010FFh 001000h
4KB 00FFFFh 00F000h 256 Bytes 000FFFh 000F00h
4KB 00EFFFh 00E000h 256 Bytes 000EFFh 000E00h
4KB 00DFFFh 00D000h 256 Bytes 000DFFh 000D00h
4KB 00CFFFh 00C000h 256 Bytes 000CFFh 000C00h
4KB 00BFFFh 00B000h 256 Bytes 000BFFh 000B00h
4KB 00AFFFh 00A000h 256 Bytes 000AFFh 000A00h
4KB 009FFFh 009000h 256 Bytes 0009FFh 000900h
4KB 008FFFh 008000h 256 Bytes 0008FFh 000800h
4KB 007FFFh 007000h 256 Bytes 0007FFh 000700h
4KB 006FFFh 006000h 256 Bytes 0006FFh 000600h
4KB 005FFFh 005000h 256 Bytes 0005FFh 000500h
4KB 004FFFh 004000h 256 Bytes 0004FFh 000400h
4KB 003FFFh 003000h 256 Bytes 0003FFh 000300h
4KB 002FFFh 002000h 256 Bytes 0002FFh 000200h
4KB 001FFFh 001000h 256 Bytes 0001FFh 000100h
4KB 000FFFh 000000h 256 Bytes 0000FFh 000000h
64KB
(Sector 2) 64KB
64KB
(Sector 3)
Range
64KB
32KB
32KB
Block Erase Detail
32KB
32KB
Pa
g
e Pro
g
ram Detail
Page AddressBlock Address
Range
64KB
(Sector 0)
32KB
32KB
64KB
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AT25DF021
5. Device Operation
The AT25DF021 is controlled by a set of instructions that are sent from a host controller, com-
monly referred to as the SPI Master. The SPI Master communicates with the AT25DF021 via the
SPI bus which is comprised of four signal lines: Chip Select (CS), Serial Clock (SCK), Serial
Input (SI), and Serial Output (SO).
The SPI protocol defines a total of four modes of operation (mode 0, 1, 2, or 3) with each mode
differing in respect to the SCK polarity and phase and how the polarity and phase control the
flow of data on the SPI bus. The AT25DF021 supports the two most common modes, SPI
Modes 0 and 3. The only difference between SPI Modes 0 and 3 is the polarity of the SCK signal
when in the inactive state (when the SPI Master is in standby mode and not transferring any
data). With SPI Modes 0 and 3, data is always latched in on the rising edge of SCK and always
output on the falling edge of SCK.
Figure 5-1. SPI Mode 0 and 3
6. Commands and Addressing
A valid instruction or operation must always be started by first asserting the CS pin. After the CS
pin has been asserted, the host controller must then clock out a valid 8-bit opcode on the SPI
bus. Following the opcode, instruction dependent information such as address and data bytes
would then be clocked out by the host controller. All opcode, address, and data bytes are trans-
ferred with the most-significant bit (MSB) first. An operation is ended by deasserting the CS pin.
Opcodes not supported by the AT25DF021 will be ignored by the device and no operation will be
started. The device will continue to ignore any data presented on the SI pin until the start of the
next operation (CS pin being deasserted and then reasserted). In addition, if the CS pin is deas-
serted before complete opcode and address information is sent to the device, then no operation
will be performed and the device will simply return to the idle state and wait for the next
operation.
Addressing of the device requires a total of three bytes of information to be sent, representing
address bits A23-A0. Since the upper address limit of the AT25DF021 memory array is
03FFFFh, address bits A23-A18 are always ignored by the device.
SCK
CS
SI
SO
MSB LSB
MSB LSB
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AT25DF021
Table 6-1. Command Listing
Command Opcode
Clock
Frequency
Address
Bytes
Dummy
Bytes
Data
Bytes
Read Commands
Read Array 0Bh 0000 1011 Up to 66 MHz 3 1 1+
03h 0000 0011 Up to 33 MHz 3 0 1+
Program and Erase Commands
Block Erase (4 Kbytes) 20h 0010 0000 Up to 66 MHz 3 0 0
Block Erase (32 Kbytes) 52h 0101 0010 Up to 66 MHz 3 0 0
Block Erase (64 Kbytes) D8h 1101 1000 Up to 66 MHz 3 0 0
Chip Erase 60h 0110 0000 Up to 66 MHz 0 0 0
C7h 1100 0111 Up to 66 MHz 0 0 0
Byte/Page Program (1 to 256 Bytes) 02h 0000 0010 Up to 66 MHz 3 0 1+
Protection Commands
Write Enable 06h 0000 0110 Up to 66 MHz 0 0 0
Write Disable 04h 0000 0100 Up to 66 MHz 0 0 0
Protect Sector 36h 0011 0110 Up to 66 MHz 3 0 0
Unprotect Sector 39h 0011 1001 Up to 66 MHz 3 0 0
Global Protect/Unprotect Use Write Status Register Command
Read Sector Protection Registers 3Ch 0011 1100 Up to 66 MHz 3 0 1+
Security Commands
Program OTP Security Register 9Bh 1001 1011 Up to 66 MHz 3 0 1+
Read OTP Security Register 77h 0111 0111 Up to 66 MHz 3 2 1+
Status Register Commands
Read Status Register 05h 0000 0101 Up to 66 MHz 0 0 1+
Write Status Register 01h 0000 0001 Up to 66 MHz 0 0 1
Miscellaneous Commands
Read Manufacturer and Device ID 9Fh 1001 1111 Up to 66 MHz 0 0 1 to 4
Deep Power-Down B9h 1011 1001 Up to 66 MHz 0 0 0
Resume from Deep Power-Down ABh 1010 1011 Up to 66 MHz 0 0 0
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AT25DF021
7. Read Commands
7.1 Read Array
The Read Array command can be used to sequentially read a continuous stream of data from
the device by simply providing the clock signal once the initial starting address has been speci-
fied. The device incorporates an internal address counter that automatically increments on every
clock cycle.
Two opcodes (0Bh and 03h) can be used for the Read Array command. The use of each
opcode depends on the maximum clock frequency that will be used to read data from the
device. The 0Bh opcode can be used at any clock frequency up to the maximum specified by
fCLK, and the 03h opcode can be used for lower frequency read operations up to the maximum
specified by fRDLF.
To perform the Read Array operation, the CS pin must first be asserted and the appropriate
opcode (0Bh or 03h) must be clocked into the device. After the opcode has been clocked in, the
three address bytes must be clocked in to specify the starting address location of the first byte to
read within the memory array. Following the three address bytes, an additional dummy byte
needs to be clocked into the device if the 0Bh opcode is used for the Read Array operation.
After the three address bytes (and the dummy byte if using opcode 0Bh) have been clocked in,
additional clock cycles will result in data being output on the SO pin. The data is always output
with the MSB of a byte first. When the last byte (03FFFFh) of the memory array has been read,
the device will continue reading back at the beginning of the array (000000h). No delays will be
incurred when wrapping around from the end of the array to the beginning of the array.
Deasserting the CS pin will terminate the read operation and put the SO pin into a high-imped-
ance state. The CS pin can be deasserted at any time and does not require that a full byte of
data be read.
Figure 7-1. Read Array - 0Bh Opcode
Figure 7-2. Read Array - 03h Opcode
SCK
CS
SI
SO
MSB MSB
2310
00001011
675410119812 394243414037 3833 36353431 3229 30 44 47 484645
OPCODE
AAAA AAAA A
MSB
XXXXXXXX
MSB MSB
DDDDDDDDDD
ADDRESS BITS A23-A0 DON'T CARE
DATA BYTE 1
HIGH-IMPEDANCE
SCK
CS
SI
SO
MSB MSB
2310
00000011
675410119812 373833 36353431 3229 30 39 40
OPCODE
AAAA AAAA A
MSB MSB
DDDDDDDDDD
ADDRESS BITS A23-A0
DATA BYTE 1
HIGH-IMPEDANCE
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3677F–DFLASH–5/2013
AT25DF021
8. Program and Erase Commands
8.1 Byte/Page Program
The Byte/Page Program command allows anywhere from a single byte of data to 256 bytes of
data to be programmed into previously erased memory locations. An erased memory location is
one that has all eight bits set to the logical “1” state (a byte value of FFh). Before a Byte/Page
Program command can be started, the Write Enable command must have been previously
issued to the device (see “Write Enable” on page 12) to set the Write Enable Latch (WEL) bit of
the Status Register to a logical “1” state.
To perform a Byte/Page Program command, an opcode of 02h must be clocked into the device
followed by the three address bytes denoting the first byte location of the memory array to begin
programming at. After the address bytes have been clocked in, data can then be clocked into the
device and will be stored in an internal buffer.
If the starting memory address denoted by A23-A0 does not fall on an even 256-byte page
boundary (A7-A0 are not all 0), then special circumstances regarding which memory locations to
be programmed will apply. In this situation, any data that is sent to the device that goes beyond
the end of the page will wrap around back to the beginning of the same page. For example, if the
starting address denoted by A23-A0 is 0000FEh, and three bytes of data are sent to the device,
then the first two bytes of data will be programmed at addresses 0000FEh and 0000FFh while
the last byte of data will be programmed at address 000000h. The remaining bytes in the page
(addresses 000001h through 0000FDh) will not be programmed and will remain in the erased
state (FFh). In addition, if more than 256 bytes of data are sent to the device, then only the last
256 bytes sent will be latched into the internal buffer.
When the CS pin is deasserted, the device will take the data stored in the internal buffer and pro-
gram it into the appropriate memory array locations based on the starting address specified by
A23-A0 and the number of data bytes sent to the device. If less than 256 bytes of data were sent
to the device, then the remaining bytes within the page will not be programmed and will remain
in the erased state (FFh). The programming of the data bytes is internally self-timed and should
take place in a time of tPP or tBP if only programming a single byte.
The three address bytes and at least one complete byte of data must be clocked into the device
before the CS pin is deasserted, and the CS pin must be deasserted on even byte boundaries
(multiples of eight bits); otherwise, the device will abort the operation and no data will be pro-
grammed into the memory array. In addition, if the address specified by A23-A0 points to a
memory location within a sector that is in the protected state (see “Protect Sector” on page 13),
then the Byte/Page Program command will not be executed, and the device will return to the idle
state once the CS pin has been deasserted. The WEL bit in the Status Register will be reset
back to the logical “0” state if the program cycle aborts due to an incomplete address being sent,
an incomplete byte of data being sent, the CS pin being deasserted on uneven byte boundaries,
or because the memory location to be programmed is protected.
While the device is programming, the Status Register can be read and will indicate that the
device is busy. For faster throughput, it is recommended that the Status Register be polled
rather than waiting the tBP or tPP time to determine if the data bytes have finished programming.
At some point before the program cycle completes, the WEL bit in the Status Register will be
reset back to the logical “0” state.
The device also incorporates an intelligent programming algorithm that can detect when a byte
location fails to program properly. If a programming error arises, it will be indicated by the EPE
bit in the Status Register.
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AT25DF021
Figure 8-1. Byte Program
Figure 8-2. Page Program
8.2 Block Erase
A block of 4, 32, or 64 Kbytes can be erased (all bits set to the logical “1” state) in a single oper-
ation by using one of three different opcodes for the Block Erase command. An opcode of 20h is
used for a 4-Kbyte erase, an opcode of 52h is used for a 32-Kbyte erase, and an opcode of D8h
is used for a 64-Kbyte erase. Before a Block Erase command can be started, the Write Enable
command must have been previously issued to the device to set the WEL bit of the Status Reg-
ister to a logical “1” state.
To perform a Block Erase, the CS pin must first be asserted and the appropriate opcode (20h,
52h, or D8h) must be clocked into the device. After the opcode has been clocked in, the three
address bytes specifying an address within the 4-, 32-, or 64-Kbyte block to be erased must be
clocked in. Any additional data clocked into the device will be ignored. When the CS pin is deas-
serted, the device will erase the appropriate block. The erasing of the block is internally self-
timed and should take place in a time of tBLKE.
Since the Block Erase command erases a region of bytes, the lower order address bits do not
need to be decoded by the device. Therefore, for a 4-Kbyte erase, address bits A11-A0 will be
ignored by the device and their values can be either a logical “1” or “0”. For a 32-Kbyte erase,
address bits A14-A0 will be ignored, and for a 64-Kbyte erase, address bits A15-A0 will be
ignored by the device. Despite the lower order address bits not being decoded by the device, the
complete three address bytes must still be clocked into the device before the CS pin is deas-
serted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits);
otherwise, the device will abort the operation and no erase operation will be performed.
SCK
CS
SI
SO
MSB MSB
2310
00000010
675410119812 3937 3833 36353431 3229 30
OPCODE
HIGH-IMPEDANCE
AAAA AAAA A
MSB
DDDDDDDD
ADDRESS BITS A23-A0 DATA IN
SCK
CS
SI
SO
MSB MSB
2310
00000010
6754983937 3833 36353431 3229 30
OPCODE
HIGH-IMPEDANCE
AA AAAA
MSB
DDDDDDDD
ADDRESS BITS A23-A0 DATA IN BYTE 1
MSB
DDDDDDDD
DATA IN BYTE n
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AT25DF021
If the address specified by A23-A0 points to a memory location within a sector that is in the pro-
tected state, then the Block Erase command will not be executed, and the device will return to
the idle state once the CS pin has been deasserted.
The WEL bit in the Status Register will be reset back to the logical “0” state if the erase cycle
aborts due to an incomplete address being sent, the CS pin being deasserted on uneven byte
boundaries, or because a memory location within the region to be erased is protected.
While the device is executing a successful erase cycle, the Status Register can be read and will
indicate that the device is busy. For faster throughput, it is recommended that the Status Regis-
ter be polled rather than waiting the tBLKE time to determine if the device has finished erasing. At
some point before the erase cycle completes, the WEL bit in the Status Register will be reset
back to the logical “0” state.
The device also incorporates an intelligent erase algorithm that can detect when a byte location
fails to erase properly. If an erase error occurs, it will be indicated by the EPE bit in the Status
Register.
Figure 8-3. Block Erase
8.3 Chip Erase
The entire memory array can be erased in a single operation by using the Chip Erase command.
Before a Chip Erase command can be started, the Write Enable command must have been pre-
viously issued to the device to set the WEL bit of the Status Register to a logical “1” state.
Two opcodes, 60h and C7h, can be used for the Chip Erase command. There is no difference in
device functionality when utilizing the two opcodes, so they can be used interchangeably. To
perform a Chip Erase, one of the two opcodes (60h or C7h) must be clocked into the device.
Since the entire memory array is to be erased, no address bytes need to be clocked into the
device, and any data clocked in after the opcode will be ignored. When the CS pin is deasserted,
the device will erase the entire memory array. The erasing of the device is internally self-timed
and should take place in a time of tCHPE.
The complete opcode must be clocked into the device before the CS pin is deasserted, and the
CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, no
erase will be performed. In addition, if any sector of the memory array is in the protected state,
then the Chip Erase command will not be executed, and the device will return to the idle state
once the CS pin has been deasserted. The WEL bit in the Status Register will be reset back to
the logical “0” state if the CS pin is deasserted on uneven byte boundaries or if a sector is in the
protected state.
SCK
CS
SI
SO
MSB MSB
2310
CCCCCCCC
675410119812 3129 3027 2826
OPCODE
AAAA AAAA A A A A
ADDRESS BITS A23-A0
HIGH-IMPEDANCE
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AT25DF021
While the device is executing a successful erase cycle, the Status Register can be read and will
indicate that the device is busy. For faster throughput, it is recommended that the Status Regis-
ter be polled rather than waiting the tCHPE time to determine if the device has finished erasing. At
some point before the erase cycle completes, the WEL bit in the Status Register will be reset
back to the logical “0” state.
The device also incorporates an intelligent erase algorithm that can detect when a byte location
fails to erase properly. If an erase error occurs, it will be indicated by the EPE bit in the Status
Register.
Figure 8-4. Chip Erase
9. Protection Commands and Features
9.1 Write Enable
The Write Enable command is used to set the Write Enable Latch (WEL) bit in the Status Regis-
ter to a logical “1” state. The WEL bit must be set before a Byte/Page Program, erase, Protect
Sector, Unprotect Sector, Program OTP Security Register, or Write Status Register command
can be executed. This makes the issuance of these commands a two step process, thereby
reducing the chances of a command being accidentally or erroneously executed. If the WEL bit
in the Status Register is not set prior to the issuance of one of these commands, then the com-
mand will not be executed.
To issue the Write Enable command, the CS pin must first be asserted and the opcode of 06h
must be clocked into the device. No address bytes need to be clocked into the device, and any
data clocked in after the opcode will be ignored. When the CS pin is deasserted, the WEL bit in
the Status Register will be set to a logical “1”. The complete opcode must be clocked into the
device before the CS pin is deasserted, and the CS pin must be deasserted on an even byte
boundary (multiples of eight bits); otherwise, the device will abort the operation and the state of
the WEL bit will not change.
Figure 9-1. Write Enable
SCK
CS
SI
SO
MSB
2310
CCCCCCCC
6754
OPCODE
HIGH-IMPEDANCE
SCK
CS
SI
SO
MSB
2310
00000110
6754
OPCODE
HIGH-IMPEDANCE
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9.2 Write Disable
The Write Disable command is used to reset the Write Enable Latch (WEL) bit in the Status Reg-
ister to the logical “0” state. With the WEL bit reset, all Byte/Page Program, erase, Protect
Sector, Unprotect Sector, Program OTP Security Register, and Write Status Register com-
mands will not be executed. Other conditions can also cause the WEL bit to be reset; for more
details, refer to the WEL bit section of the Status Register description.
To issue the Write Disable command, the CS pin must first be asserted and the opcode of 04h
must be clocked into the device. No address bytes need to be clocked into the device, and any
data clocked in after the opcode will be ignored. When the CS pin is deasserted, the WEL bit in
the Status Register will be reset to a logical “0”. The complete opcode must be clocked into the
device before the CS pin is deasserted, and the CS pin must be deasserted on an even byte
boundary (multiples of eight bits); otherwise, the device will abort the operation and the state of
the WEL bit will not change.
Figure 9-2. Write Disable
9.3 Protect Sector
Every physical 64-Kbyte sector of the device has a corresponding single-bit Sector Protection
Register that is used to control the software protection of a sector. Upon device power-up, each
Sector Protection Register will default to the logical “1” state indicating that all sectors are pro-
tected and cannot be programmed or erased.
Issuing the Protect Sector command to a particular sector address will set the corresponding
Sector Protection Register to the logical “1” state. The following table outlines the two states of
the Sector Protection Registers.
Before the Protect Sector command can be issued, the Write Enable command must have been
previously issued to set the WEL bit in the Status Register to a logical “1”. To issue the Protect
Sector command, the CS pin must first be asserted and the opcode of 36h must be clocked into
the device followed by three address bytes designating any address within the sector to be pro-
tected. Any additional data clocked into the device will be ignored. When the CS pin is
deasserted, the Sector Protection Register corresponding to the physical sector addressed by
A23-A0 will be set to the logical “1” state, and the sector itself will then be protected from
SCK
CS
SI
SO
MSB
2310
00000100
6754
OPCODE
HIGH-IMPEDANCE
Table 9-1. Sector Protection Register Values
Value Sector Protection Status
0 Sector is unprotected and can be programmed and erased.
1 Sector is protected and cannot be programmed or erased. This is the default state.
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program and erase operations. In addition, the WEL bit in the Status Register will be reset back
to the logical “0” state.
The complete three address bytes must be clocked into the device before the CS pin is deas-
serted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits);
otherwise, the device will abort the operation. When the device aborts the Protect Sector opera-
tion, the state of the Sector Protection Register will be unchanged, and the WEL bit in the Status
Register will be reset to a logical “0”.
As a safeguard against accidental or erroneous protecting or unprotecting of sectors, the Sector
Protection Registers can themselves be locked from updates by using the SPRL (Sector Protec-
tion Registers Locked) bit of the Status Register (please refer to the Status Register description
for more details). If the Sector Protection Registers are locked, then any attempts to issue the
Protect Sector command will be ignored, and the device will reset the WEL bit in the Status Reg-
ister back to a logical “0” and return to the idle state once the CS pin has been deasserted.
Figure 9-3. Protect Sector
9.4 Unprotect Sector
Issuing the Unprotect Sector command to a particular sector address will reset the correspond-
ing Sector Protection Register to the logical “0” state (see Table 9-1 for Sector Protection
Register values). Every physical sector of the device has a corresponding single-bit Sector Pro-
tection Register that is used to control the software protection of a sector.
Before the Unprotect Sector command can be issued, the Write Enable command must have
been previously issued to set the WEL bit in the Status Register to a logical “1”. To issue the
Unprotect Sector command, the CS pin must first be asserted and the opcode of 39h must be
clocked into the device. After the opcode has been clocked in, the three address bytes designat-
ing any address within the sector to be unprotected must be clocked in. Any additional data
clocked into the device after the address bytes will be ignored. When the CS pin is deasserted,
the Sector Protection Register corresponding to the sector addressed by A23-A0 will be reset to
the logical “0” state, and the sector itself will be unprotected. In addition, the WEL bit in the Sta-
tus Register will be reset back to the logical “0” state.
The complete three address bytes must be clocked into the device before the CS pin is deas-
serted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits);
otherwise, the device will abort the operation, the state of the Sector Protection Register will be
unchanged, and the WEL bit in the Status Register will be reset to a logical “0”.
As a safeguard against accidental or erroneous locking or unlocking of sectors, the Sector Pro-
tection Registers can themselves be locked from updates by using the SPRL (Sector Protection
SCK
CS
SI
SO
MSB MSB
2310
00110110
675410119812 3129 3027 2826
OPCODE
AAAA AAAA A A A A
ADDRESS BITS A23-A0
HIGH-IMPEDANCE
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3677F–DFLASH–5/2013
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Registers Locked) bit of the Status Register (please refer to the Status Register description for
more details). If the Sector Protection Registers are locked, then any attempts to issue the
Unprotect Sector command will be ignored, and the device will reset the WEL bit in the Status
Register back to a logical “0” and return to the idle state once the CS pin has been deasserted.
Figure 9-4. Unprotect Sector
9.5 Global Protect/Unprotect
The Global Protect and Global Unprotect features can work in conjunction with the Protect Sec-
tor and Unprotect Sector functions. For example, a system can globally protect the entire
memory array and then use the Unprotect Sector command to individually unprotect certain sec-
tors and individually reprotect them later by using the Protect Sector command. Likewise, a
system can globally unprotect the entire memory array and then individually protect certain sec-
tors as needed.
Performing a Global Protect or Global Unprotect is accomplished by writing a certain combina-
tion of data to the Status Register using the Write Status Register Byte 1 command (see “Write
Status Register” on page 25 for command execution details). The Write Status Register com-
mand is also used to modify the SPRL (Sector Protection Registers Locked) bit to control
hardware and software locking.
To perform a Global Protect, the appropriate WP pin and SPRL conditions must be met, and the
system must write a logical “1” to bits 5, 4, 3, and 2 of the first byte of the Status Register. Con-
versely, to perform a Global Unprotect, the same WP and SPRL conditions must be met but the
system must write a logical “0” to bits 5, 4, 3, and 2 of the first byte of the Status Register. Table
9-2 details the conditions necessary for a Global Protect or Global Unprotect to be performed.
SCK
CS
SI
SO
MSB MSB
2310
00111001
675410119812 3129 3027 2826
OPCODE
AAAA AAAA A A A A
ADDRESS BITS A23-A0
HIGH-IMPEDANCE
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Essentially, if the SPRL bit of the Status Register is in the logical “0” state (Sector Protection
Registers are not locked), then writing a 00h to the first byte of the Status Register will perform a
Global Unprotect without changing the state of the SPRL bit. Similarly, writing a 7Fh to the first
byte of the Status Register will perform a Global Protect and keep the SPRL bit in the logical “0”
state. The SPRL bit can, of course, be changed to a logical “1” by writing an FFh if software-lock-
ing or hardware-locking is desired along with the Global Protect.
If the desire is to only change the SPRL bit without performing a Global Protect or Global Unpro-
tect, then the system can simply write a 0Fh to the first byte of the Status Register to change the
Table 9-2. Valid SPRL and Global Protect/Unprotect Conditions
WP
State
Current
SPRL
Value
New Write Status
Register Byte 1
Data
Protection Operation
New
SPRL
Value
Bit
7 6 5 4 3 2 1 0
00
0 x 0 0 0 0 x x
0 x 0 0 0 1 x x
×
0 x 1 1 1 0 x x
0 x 1 1 1 1 x x
1 x 0 0 0 0 x x
1 x 0 0 0 1 x x
×
1 x 1 1 1 0 x x
1 x 1 1 1 1 x x
Global Unprotect – all Sector Protection Registers reset to 0
No change to current protection.
No change to current protection.
No change to current protection.
Global Protect – all Sector Protection Registers set to 1
Global Unprotect – all Sector Protection Registers reset to 0
No change to current protection.
No change to current protection.
No change to current protection.
Global Protect – all Sector Protection Registers set to 1
0
0
0
0
0
1
1
1
1
1
0 1 x x x x x x x x
No change to the current protection level. All sectors currently
protected will remain protected and all sectors currently unprotected
will remain unprotected.
The Sector Protection Registers are hard-locked and cannot be
changed when the WP pin is LOW and the current state of SPRL is 1.
Therefore, a Global Protect/Unprotect will not occur. In addition, the
SPRL bit cannot be changed (the WP pin must be HIGH in order to
change SPRL back to a 0).
10
0 x 0 0 0 0 x x
0 x 0 0 0 1 x x
×
0 x 1 1 1 0 x x
0 x 1 1 1 1 x x
1 x 0 0 0 0 x x
1 x 0 0 0 1 x x
×
1 x 1 1 1 0 x x
1 x 1 1 1 1 x x
Global Unprotect – all Sector Protection Registers reset to 0
No change to current protection.
No change to current protection.
No change to current protection.
Global Protect – all Sector Protection Registers set to 1
Global Unprotect – all Sector Protection Registers reset to 0
No change to current protection.
No change to current protection.
No change to current protection.
Global Protect – all Sector Protection Registers set to 1
0
0
0
0
0
1
1
1
1
1
11
0 x 0 0 0 0 x x
0 x 0 0 0 1 x x
×
0 x 1 1 1 0 x x
0 x 1 1 1 1 x x
1 x 0 0 0 0 x x
1 x 0 0 0 1 x x
×
1 x 1 1 1 0 x x
1 x 1 1 1 1 x x
No change to the current protection level. All sectors
currently protected will remain protected, and all sectors
currently unprotected will remain unprotected.
The Sector Protection Registers are soft-locked and cannot
be changed when the current state of SPRL is 1. Therefore,
a Global Protect/Unprotect will not occur. However, the
SPRL bit can be changed back to a 0 from a 1 since the WP
pin is HIGH. To perform a Global Protect/Unprotect, the
Write Status Register command must be issued again after
the SPRL bit has been changed from a 1 to a 0.
0
0
0
0
0
1
1
1
1
1
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SPRL bit from a logical “1” to a logical “0” provided the WP pin is deasserted. Likewise, the sys-
tem can write an F0h to change the SPRL bit from a logical “0” to a logical “1” without affecting
the current sector protection status (no changes will be made to the Sector Protection
Registers).
When writing to the first byte of the Status Register, bits 5, 4, 3, and 2 will not actually be modi-
fied but will be decoded by the device for the purposes of the Global Protect and Global
Unprotect functions. Only bit 7, the SPRL bit, will actually be modified. Therefore, when reading
the first byte of the Status Register, bits 5, 4, 3, and 2 will not reflect the values written to them
but will instead indicate the status of the WP pin and the sector protection status. Please refer to
“Read Status Register” on page 22 and Table 11-1 on page 22 for details on the Status Register
format and what values can be read for bits 5, 4, 3, and 2.
9.6 Read Sector Protection Registers
The Sector Protection Registers can be read to determine the current software protection status
of each sector. Reading the Sector Protection Registers, however, will not determine the status
of the WP pin.
To read the Sector Protection Register for a particular sector, the CS pin must first be asserted
and the opcode of 3Ch must be clocked in. Once the opcode has been clocked in, three address
bytes designating any address within the sector must be clocked in. After the last address byte
has been clocked in, the device will begin outputting data on the SO pin during every subse-
quent clock cycle. The data being output will be a repeating byte of either FFh or 00h to denote
the value of the appropriate Sector Protection Register.
Deasserting the CS pin will terminate the read operation and put the SO pin into a high-imped-
ance state. The CS pin can be deasserted at any time and does not require that a full byte of
data be read.
In addition to reading the individual Sector Protection Registers, the Software Protection Status
(SWP) bits in the Status Register can be read to determine if all, some, or none of the sectors
are software protected (refer to “Read Status Register” on page 22 for more details).
Figure 9-5. Read Sector Protection Register
Table 9-3. Read Sector Protection Register - Output Data
Output Data Sector Protection Register Value
00h Sector Protection Register value is 0 (sector is unprotected).
FFh Sector Protection Register value is 1 (sector is protected).
SCK
CS
SI
SO
MSB MSB
2310
00111100
675410119812 373833 36353431 3229 30 39 40
OPCODE
AAAA AAAA A
MSB MSB
DDDDDDDDDD
ADDRESS BITS A23-A0
DATA BYTE
HIGH-IMPEDANCE
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9.7 Protected States and the Write Protect (WP) Pin
The WP pin is not linked to the memory array itself and has no direct effect on the protection sta-
tus or lockdown status of the memory array. Instead, the WP pin, in conjunction with the SPRL
(Sector Protection Registers Locked) bit in the Status Register, is used to control the hardware
locking mechanism of the device. For hardware locking to be active, two conditions must be met-
the WP pin must be asserted and the SPRL bit must be in the logical “1” state.
When hardware locking is active, the Sector Protection Registers are locked and the SPRL bit
itself is also locked. Therefore, sectors that are protected will be locked in the protected state,
and sectors that are unprotected will be locked in the unprotected state. These states cannot be
changed as long as hardware locking is active, so the Protect Sector, Unprotect Sector, and
Write Status Register commands will be ignored. In order to modify the protection status of a
sector, the WP pin must first be deasserted, and the SPRL bit in the Status Register must be
reset back to the logical “0” state using the Write Status Register command. When resetting the
SPRL bit back to a logical “0”, it is not possible to perform a Global Protect or Global Unprotect
at the same time since the Sector Protection Registers remain soft-locked until after the Write
Status Register command has been executed.
If the WP pin is permanently connected to GND, then once the SPRL bit is set to a logical “1”,
the only way to reset the bit back to the logical “0” state is to power-cycle the device. This allows
a system to power-up with all sectors software protected but not hardware locked. Therefore,
sectors can be unprotected and protected as needed and then hardware locked at a later time
by simply setting the SPRL bit in the Status Register.
When the WP pin is deasserted, or if the WP pin is permanently connected to VCC, the SPRL bit
in the Status Register can still be set to a logical “1” to lock the Sector Protection Registers. This
provides a software locking ability to prevent erroneous Protect Sector or Unprotect Sector com-
mands from being processed. When changing the SPRL bit to a logical “1” from a logical “0”, it is
also possible to perform a Global Protect or Global Unprotect at the same time by writing the
appropriate values into bits 5, 4, 3, and 2 of the first byte of the Status Register.
Tables 9-4 and 9-5 detail the various protection and locking states of the device.
Note: 1. “n” represents a sector number
Table 9-4. Sector Protection Register States
WP
Sector Protection Register
n(1)
Sector
n(1)
X
(Don't Care)
0 Unprotected
1 Protected
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10. Security Commands
10.1 Program OTP Security Register
The device contains a specialized OTP (One-Time Programmable) Security Register that can be
used for purposes such as unique device serialization, system-level Electronic Serial Number
(ESN) storage, locked key storage, etc. The OTP Security Register is independent of the main
Flash memory array and is comprised of a total of 128 bytes of memory divided into two por-
tions. The first 64 bytes (byte locations 0 through 63) of the OTP Security Register are allocated
as a one-time user-programmable space. Once these 64 bytes have been programmed, they
cannot be erased or reprogrammed. The remaining 64 bytes of the OTP Security Register (byte
locations 64 through 127) are factory programmed by Adesto® and will contain a unique value
for each device. The factory programmed data is fixed and cannot be changed.
The user-programmable portion of the OTP Security Register does not need to be erased before
it is programmed. In addition, the Program OTP Security Register command operates on the
entire 64-byte user-programmable portion of the OTP Security Register at one time. Once the
user-programmable space has been programmed with any number of bytes, the user-program-
mable space cannot be programmed again; therefore, it is not possible to only program the first
two bytes of the register and then program the remaining 62 bytes at a later time.
Before the Program OTP Security Register command can be issued, the Write Enable command
must have been previously issued to set the WEL bit in the Status Register to a logical “1”. To
program the OTP Security Register, the CS pin must first be asserted and an opcode of 9Bh
must be clocked into the device followed by the three address bytes denoting the first byte
Table 9-5. Hardware and Software Locking
WP SPRL Locking SPRL Change Allowed Sector Protection Registers
0 0 Can be modified from 0 to 1
Unlocked and modifiable using the
Protect and Unprotect Sector commands.
Global Protect and Unprotect can also be
performed.
01
Hardware
Locked Locked
Locked in current state. Protect and
Unprotect Sector commands will be
ignored. Global Protect and Unprotect
cannot be performed.
1 0 Can be modified from 0 to 1
Unlocked and modifiable using the
Protect and Unprotect Sector commands.
Global Protect and Unprotect can also be
performed.
11
Software
Locked Can be modified from 1 to 0
Locked in current state. Protect and
Unprotect Sector commands will be
ignored. Global Protect and Unprotect
cannot be performed.
Table 10-1. OTP Security Register
Security Register
Byte Number
0 1 . . . 62 63 64 65 . . . 126 127
One-Time User Programmable Factory Programmed by Adesto
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AT25DF021
location of the OTP Security Register to begin programming at. Since the size of the user-pro-
grammable portion of the OTP Security Register is 64 bytes, the upper order address bits do not
need to be decoded by the device. Therefore, address bits A23-A6 will be ignored by the device
and their values can be either a logical “1” or “0”. After the address bytes have been clocked in,
data can then be clocked into the device and will be stored in the internal buffer.
If the starting memory address denoted by A23-A0 does not start at the beginning of the OTP
Security Register memory space (A5-A0 are not all 0), then special circumstances regarding
which OTP Security Register locations to be programmed will apply. In this situation, any data
that is sent to the device that goes beyond the end of the 64-byte user-programmable space will
wrap around back to the beginning of the OTP Security Register. For example, if the starting
address denoted by A23-A0 is 00003Eh, and three bytes of data are sent to the device, then the
first two bytes of data will be programmed at OTP Security Register addresses 00003Eh and
00003Fh while the last byte of data will be programmed at address 000000h. The remaining
bytes in the OTP Security Register (addresses 000001h through 00003Dh) will not be pro-
grammed and will remain in the erased state (FFh). In addition, if more than 64 bytes of data are
sent to the device, then only the last 64 bytes sent will be latched into the internal buffer.
When the CS pin is deasserted, the device will take the data stored in the internal buffer and pro-
gram it into the appropriate OTP Security Register locations based on the starting address
specified by A23-A0 and the number of data bytes sent to the device. If less than 64 bytes of
data were sent to the device, then the remaining bytes within the OTP Security Register will not
be programmed and will remain in the erased state (FFh). The programming of the data bytes is
internally self-timed and should take place in a time of tOTPP.
The three address bytes and at least one complete byte of data must be clocked into the device
before the CS pin is deasserted, and the CS pin must be deasserted on even byte boundaries
(multiples of eight bits); otherwise, the device will abort the operation and the user-programma-
ble portion of the OTP Security Register will not be programmed. The WEL bit in the Status
Register will be reset back to the logical “0” state if the OTP Security Register program cycle
aborts due to an incomplete address being sent, an incomplete byte of data being sent, the CS
pin being deasserted on uneven byte boundaries, or because the user-programmable portion of
the OTP Security Register was previously programmed.
While the device is programming the OTP Security Register, the Status Register can be read
and will indicate that the device is busy. For faster throughput, it is recommended that the Status
Register be polled rather than waiting the tOTPP time to determine if the data bytes have finished
programming. At some point before the OTP Security Register programming completes, the
WEL bit in the Status Register will be reset back to the logical “0” state.
If the device is powered-down during the OTP Security Register program cycle, then the con-
tents of the 64-byte user programmable portion of the OTP Security Register cannot be
guaranteed and cannot be programmed again.
The Program OTP Security Register command utilizes the internal 256-buffer for processing.
Therefore, the contents of the buffer will be altered from its previous state when this command is
issued.
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Figure 10-1. Program OTP Security Register
10.2 Read OTP Security Register
The OTP Security Register can be sequentially read in a similar fashion to the Read Array oper-
ation up to the maximum clock frequency specified by fCLK. To read the OTP Security Register,
the CS pin must first be asserted and the opcode of 77h must be clocked into the device. After
the opcode has been clocked in, the three address bytes must be clocked in to specify the start-
ing address location of the first byte to read within the OTP Security Register. Following the
three address bytes, two dummy bytes must be clocked into the device before data can be
output.
After the three address bytes and the dummy bytes have been clocked in, additional clock
cycles will result in OTP Security Register data being output on the SO pin. When the last byte
(00007Fh) of the OTP Security Register has been read, the device will continue reading back at
the beginning of the register (000000h). No delays will be incurred when wrapping around from
the end of the register to the beginning of the register.
Deasserting the CS pin will terminate the read operation and put the SO pin into a high-imped-
ance state. The CS pin can be deasserted at any time and does not require that a full byte of
data be read.
Figure 10-2. Read OTP Security Register
SCK
CS
SI
SO
MSB MSB
2310
10011011
6754983937 3833 36353431 3229 30
OPCODE
HIGH-IMPEDANCE
AA AAAA
MSB
DDDDDDDD
ADDRESS BITS A23-A0 DATA IN BYTE 1
MSB
DDDDDDDD
DATA IN BYTE n
SCK
CS
SI
SO
MSB MSB
2310
01110111
675410119812 3336353431 3229 30
OPCODE
AAAA AAAAAXXX
MSB MSB
DDDDDDDDDD
ADDRESS BITS A23-A0
MSB
XXXXXX
DON'T CARE
DATA BYTE 1
HIGH-IMPEDANCE
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11. Status Register Commands
11.1 Read Status Register
The Status Register can be read to determine the device’s ready/busy status, as well as the sta-
tus of many other functions such as Hardware Locking and Software Protection. The Status
Register can be read at any time, including during an internally self-timed program or erase
operation.
To read the Status Register, the CS pin must first be asserted and the opcode of 05h must be
clocked into the device. After the opcode has been clocked in, the device will begin outputting
Status Register data on the SO pin during every subsequent clock cycle. After the last bit (bit 0)
of the Status Register has been clocked out, the sequence will repeat itself starting again with bit
7 as long as the CS pin remains asserted and the clock pin is being pulsed. The data in the Sta-
tus Register is constantly being updated, so each repeating sequence will output new data.
Deasserting the CS pin will terminate the Read Status Register operation and put the SO pin
into a high-impedance state. The CS pin can be deasserted at any time and does not require
that a full byte of data be read.
Notes: 1. Only bit 7 of the Status Register will be modified when using the Write Status Register command.
2. R/W = Readable and writable
R = Readable only
Table 11-1. Status Register Format
Bit(1) Name Type(2) Description
7 SPRL Sector Protection Registers Locked R/W 0 Sector Protection Registers are unlocked (default).
1 Sector Protection Registers are locked.
6 RES Reserved for future use R 0 Reserved for future use.
5 EPE Erase/Program Error R 0 Erase or program operation was successful.
1 Erase or program error detected.
4 WPP Write Protect (WP) Pin Status R 0WP is asserted.
1WP is deasserted.
3:2 SWP Software Protection Status R
00 All sectors are software unprotected (all Sector
Protection Registers are 0).
01
Some sectors are software protected. Read
individual Sector Protection Registers to determine
which sectors are protected.
10 Reserved for future use.
11 All sectors are software protected (all Sector
Protection Registers are 1 – default).
1 WEL Write Enable Latch Status R 0 Device is not write enabled (default).
1 Device is write enabled.
0 RDY/BSY Ready/Busy Status R 0 Device is ready.
1 Device is busy with an internal operation.
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11.1.1 SPRL Bit
The SPRL bit is used to control whether the Sector Protection Registers can be modified or not.
When the SPRL bit is in the logical “1” state, all Sector Protection Registers are locked and can-
not be modified with the Protect Sector and Unprotect Sector commands (the device will ignore
these commands). In addition, the Global Protect and Global Unprotect features cannot be per-
formed. Any sectors that are presently protected will remain protected, and any sectors that are
presently unprotected will remain unprotected.
When the SPRL bit is in the logical “0” state, all Sector Protection Registers are unlocked and
can be modified (the Protect Sector and Unprotect Sector commands, as well as the Global Pro-
tect and Global Unprotect features, will be processed as normal). The SPRL bit defaults to the
logical “0” state after device power-up. The Reset command has no effect on the SPRL bit.
The SPRL bit can be modified freely whenever the WP pin is deasserted. However, if the WP pin
is asserted, then the SPRL bit may only be changed from a logical “0” (Sector Protection Regis-
ters are unlocked) to a logical “1” (Sector Protection Registers are locked). In order to reset the
SPRL bit back to a logical “0” using the Write Status Register command, the WP pin will have to
first be deasserted.
The SPRL bit is the only bit of the Status Register that can be user modified via the Write Status
Register command.
11.1.2 EPE Bit
The EPE bit indicates whether the last erase or program operation completed successfully or
not. If at least one byte during the erase or program operation did not erase or program properly,
then the EPE bit will be set to the logical “1” state. The EPE bit will not be set if an erase or pro-
gram operation aborts for any reason such as an attempt to erase or program a protected
region, or if the WEL bit is not set prior to an erase or program operation. The EPE bit will be
updated after every erase and program operation.
11.1.3 WPP Bit
The WPP bit can be read to determine if the WP pin has been asserted or not.
11.1.4 SWP Bits
The SWP bits provide feedback on the software protection status for the device. There are three
possible combinations of the SWP bits that indicate whether none, some, or all of the sectors
have been protected using the Protect Sector command or the Global Protect feature. If the
SWP bits indicate that some of the sectors have been protected, then the individual Sector Pro-
tection Registers can be read with the Read Sector Protection Registers command to determine
which sectors are in fact protected.
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3677F–DFLASH–5/2013
AT25DF021
11.1.5 WEL Bit
The WEL bit indicates the current status of the internal Write Enable Latch. When the WEL bit is
in the logical “0” state, the device will not accept any Byte/Page Program, erase, Protect Sector,
Unprotect Sector, Program OTP Security Register, or Write Status Register commands. The
WEL bit defaults to the logical “0” state after a device power-up or reset operation. In addition,
the WEL bit will be reset to the logical “0” state automatically under the following conditions:
Write Disable operation completes successfully
Write Status Register operation completes successfully or aborts
Protect Sector operation completes successfully or aborts
Unprotect Sector operation completes successfully or aborts
Program OTP Security Register operation completes successfully or aborts
Byte/Page Program operation completes successfully or aborts
Block Erase operation completes successfully or aborts
Chip Erase operation completes successfully or aborts
Hold condition aborts
If the WEL bit is in the logical “1” state, it will not be reset to a logical “0” if an operation aborts
due to an incomplete or unrecognized opcode being clocked into the device before the CS pin is
deasserted. In order for the WEL bit to be reset when an operation aborts prematurely, the entire
opcode for a Byte/Page Program, erase, Protect Sector, Unprotect Sector, Program OTP Secu-
rity Register, or Write Status Register command must have been clocked into the device.
11.1.6 RDY/BSY Bit
The RDY/BSY bit is used to determine whether or not an internal operation, such as a program
or erase, is in progress. To poll the RDY/BSY bit to detect the completion of a program or erase
cycle, new Status Register data must be continually clocked out of the device until the state of
the RDY/BSY bit changes from a logical “1” to a logical “0”.
Figure 11-1. Read Status Register
SCK
CS
SI
SO
MSB
2310
00000101
675410119812 212217 20191815 1613 14 23 24 28 29272625 30
OPCODE
MSB MSB
DDDDDD DDDD
MSB
DDDDDDDD D DDD D D
ST
DATA
ATUS REGISTERST
DATA
ATUS REGISTER ST
DATA
ATUS REGISTER
HIGH-IMPEDANCE
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AT25DF021
11.2 Write Status Register
The Write Status Register command is used to modify the SPRL bit of the Status Register
and/or to perform a Global Protect or Global Unprotect operation. Before the Write Status Regis-
ter command can be issued, the Write Enable command must have been previously issued to
set the WEL bit in the Status Register to a logical “1”.
To issue the Write Status Register command, the CS pin must first be asserted and the opcode
of 01h must be clocked into the device followed by one byte of data. The one byte of data con-
sists of the SPRL bit value, a don’t care bit, four data bits to denote whether a Global Protect or
Unprotect should be performed, and two additional don’t care bits (see Table 11-2). Any addi-
tional data bytes that are sent to the device will be ignored. When the CS pin is deasserted, the
SPRL bit in the Status Register will be modified, and the WEL bit in the Status Register will be
reset back to a logical “0”. The values of bits 5, 4, 3, and 2 and the state of the SPRL bit before
the Write Status Register command was executed (the prior state of the SPRL bit) will determine
whether or not a Global Protect or Global Unprotect will be performed. Please refer to “Global
Protect/Unprotect” on page 15 for more details.
The complete one byte of data must be clocked into the device before the CS pin is deasserted,
and the CS pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise,
the device will abort the operation, the state of the SPRL bit will not change, no potential Global
Protect or Unprotect will be performed, and the WEL bit in the Status Register will be reset back
to the logical “0” state.
If the WP pin is asserted, then the SPRL bit can only be set to a logical “1”. If an attempt is made
to reset the SPRL bit to a logical “0” while the WP pin is asserted, then the Write Status Register
Byte command will be ignored, and the WEL bit in the Status Register will be reset back to the
logical “0” state. In order to reset the SPRL bit to a logical “0”, the WP pin must be deasserted.
Figure 11-2. Write Status Register
Table 11-2. Write Status Register Format
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SPRL X Global Protect/Unprotect X X
SCK
CS
SI
SO
MSB
2310
0000000
6754
OPCODE
10 119814151312
1
MSB
DXDDDDXX
STATUS REGISTER IN
HIGH-IMPEDANCE
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AT25DF021
12. Other Commands and Functions
12.1 Read Manufacturer and Device ID
Identification information can be read from the device to enable systems to electronically query
and identify the device while it is in system. The identification method and the command opcode
comply with the JEDEC standard for “Manufacturer and Device ID Read Methodology for SPI
Compatible Serial Interface Memory Devices”. The type of information that can be read from the
device includes the JEDEC defined Manufacturer ID, the vendor specific Device ID, and the ven-
dor specific Extended Device Information.
Since not all Flash devices are capable of operating at very high clock frequencies, applications
should be designed to read the identification information from the devices at a reasonably low
clock frequency to ensure that all devices to be used in the application can be identified properly.
Once the identification process is complete, the application can then increase the clock fre-
quency to accommodate specific Flash devices that are capable of operating at the higher clock
frequencies.
To read the identification information, the CS pin must first be asserted and the opcode of 9Fh
must be clocked into the device. After the opcode has been clocked in, the device will begin out-
putting the identification data on the SO pin during the subsequent clock cycles. The first byte
that will be output will be the Manufacturer ID followed by two bytes of Device ID information.
The fourth byte output will be the Extended Device Information String Length, which will be 00h
indicating that no Extended Device Information follows. After the Extended Device Information
String Length byte is output, the SO pin will go into a high-impedance state; therefore, additional
clock cycles will have no affect on the SO pin and no data will be output. As indicated in the
JEDEC standard, reading the Extended Device Information String Length and any subsequent
data is optional.
Deasserting the CS pin will terminate the Manufacturer and Device ID read operation and put
the SO pin into a high-impedance state. The CS pin can be deasserted at any time and does not
require that a full byte of data be read.
Table 12-1. Manufacturer and Device ID Information
Byte No. Data Type Value
1 Manufacturer ID 1Fh
2 Device ID (Part 1) 43h
3 Device ID (Part 2) 00h
4 Extended Device Information String Length 00h
Table 12-2. Manufacturer and Device ID Details
Data Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Hex
Value Details
Manufacturer ID
JEDEC Assigned Code
1Fh JEDEC Code: 0001 1111 (1Fh for Adesto)
00011111
Device ID (Part 1)
Family Code Density Code
43h Family Code: 010 (AT25DF/26DFxxx series)
Density Code: 00011 (2-Mbit)
01000011
Device ID (Part 2)
Sub Code Product Version Code
00h Sub Code: 000 (Standard series)
Product Version: 00000 (Initial version)
00000000
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AT25DF021
Figure 12-1. Read Manufacturer and Device ID
12.2 Deep Power-Down
During normal operation, the device will be placed in the standby mode to consume less power
as long as the CS pin remains deasserted and no internal operation is in progress. The Deep
Power-Down command offers the ability to place the device into an even lower power consump-
tion state called the Deep Power-Down mode.
When the device is in the Deep Power-Down mode, all commands including the Read Status
Register command will be ignored with the exception of the Resume from Deep Power-Down
command. Since all commands will be ignored, the mode can be used as an extra protection
mechanism against program and erase operations.
Entering the Deep Power-Down mode is accomplished by simply asserting the CS pin, clocking
in the opcode of B9h, and then deasserting the CS pin. Any additional data clocked into the
device after the opcode will be ignored. When the CS pin is deasserted, the device will enter the
Deep Power-Down mode within the maximum time of tEDPD.
The complete opcode must be clocked in before the CS pin is deasserted, and the CS pin must
be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort
the operation and return to the standby mode once the CS pin is deasserted. In addition, the
device will default to the standby mode after a power-cycle.
The Deep Power-Down command will be ignored if an internally self-timed operation such as a
program or erase cycle is in progress. The Deep Power-Down command must be reissued after
the internally self-timed operation has been completed in order for the device to enter the Deep
Power-Down mode.
SCK
CS
SI
SO
60
9Fh
87 38
OPCODE
1Fh 43h 00h 00h
MANUFACTURER ID DEVICE ID
BYTE 1
DEVICE ID
BYTE 2
EXTENDED
DEVICE
INFORMATION
STRING LENGTH
HIGH-IMPEDANCE
14 1615 22 2423 30 3231
Note: Each transition shown for SI and SO represents one byte (8 bits)
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3677F–DFLASH–5/2013
AT25DF021
Figure 12-2. Deep Power-Down
12.3 Resume from Deep Power-Down
In order to exit the Deep Power-Down mode and resume normal device operation, the Resume
from Deep Power-Down command must be issued. The Resume from Deep Power-Down com-
mand is the only command that the device will recognized while in the Deep Power-Down mode.
To resume from the Deep Power-Down mode, the CS pin must first be asserted and opcode of
ABh must be clocked into the device. Any additional data clocked into the device after the
opcode will be ignored. When the CS pin is deasserted, the device will exit the Deep Power-
Down mode within the maximum time of tRDPD and return to the standby mode. After the device
has returned to the standby mode, normal command operations such as Read Array can be
resumed.
If the complete opcode is not clocked in before the CS pin is deasserted, or if the CS pin is not
deasserted on an even byte boundary (multiples of eight bits), then the device will abort the
operation and return to the Deep Power-Down mode.
Figure 12-3. Resume from Deep Power-Down
SCK
CS
SI
SO
MSB
I
CC
2310
10111001
6754
OPCODE
HIGH-IMPEDANCE
Standby Mode Current
Active Current
Deep Power-Down Mode Current
tEDPD
SCK
CS
SI
SO
MSB
ICC
2310
10101011
6754
OPCODE
HIGH-IMPEDANCE
Deep Power-Down Mode Current
Active Current
Standby Mode Current
t
RDPD
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AT25DF021
12.4 Hold
The HOLD pin is used to pause the serial communication with the device without having to stop
or reset the clock sequence. The Hold mode, however, does not have an affect on any internally
self-timed operations such as a program or erase cycle. Therefore, if an erase cycle is in prog-
ress, asserting the HOLD pin will not pause the operation, and the erase cycle will continue until
it is finished.
The Hold mode can only be entered while the CS pin is asserted. The Hold mode is activated
simply by asserting the HOLD pin during the SCK low pulse. If the HOLD pin is asserted during
the SCK high pulse, then the Hold mode won’t be started until the beginning of the next SCK low
pulse. The device will remain in the Hold mode as long as the HOLD pin and CS pin are
asserted.
While in the Hold mode, the SO pin will be in a high-impedance state. In addition, both the SI pin
and the SCK pin will be ignored. The WP pin, however, can still be asserted or deasserted while
in the Hold mode.
To end the Hold mode and resume serial communication, the HOLD pin must be deasserted
during the SCK low pulse. If the HOLD pin is deasserted during the SCK high pulse, then the
Hold mode won’t end until the beginning of the next SCK low pulse.
If the CS pin is deasserted while the HOLD pin is still asserted, then any operation that may
have been started will be aborted, and the device will reset the WEL bit in the Status Register
back to the logical “0” state.
Figure 12-4. Hold Mode
SCK
CS
HOLD
Hold HoldHold
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AT25DF021
13. System Considerations
In an effort to continue our goal of maintaining world-class quality leadership, Adesto has been
performing extensive testing on the AT25DF021 that would not normally be done with a Serial
Flash device. The testing that has been performed on the AT25DF021 involved extensive, non-
stop reading of the memory array on pre-conditioned devices. The pre-conditioning of the
devices, which entailed erasing and programming the entire memory array 10,000 times, was
done to simulate a customer environment and to exercise the memory cells to a certain degree.
The non-stop reading of the devices was done in three levels of granularity, with the first level
involving a continuous, looped read of 256 bytes (a single page) of memory, the second level
involving a continuous, looped-read of a 4-Kbyte (16 pages) portion of memory, and the third
level entailing non-stop reading of the entire memory array. Read operations were performed at
both +25°C and +125°C and with a supply voltage of 3.7V, which exceeds the specified data-
sheet operating voltage range.
The results of all of the extensive tests indicate that the contents of a portion of memory being
read continuously could be altered after 800,000,000 read operations only if that portion of the
memory was not erased or reprogrammed at all during the 800,000,000 read operations. If that
portion of memory was reprogrammed at some point, then it would take another 800,000,000
read operations after reprogramming before the contents could potentially be altered. For exam-
ple, if the Serial Flash is being used for boot code storage, then it would take 800,000,000 boot
operations before that boot code may become altered, provided that the boot code was not
updated or reprogrammed. If an application was to read the entire memory array non-stop at a
clock frequency of 10MHz, it would take over 5 years to reach 800,000,000 read operations.
Adesto firmly believes that this extended testing result should not be a cause for concern. We
also believe that most, if not all, applications will never read the same portion of memory
800,000,000 times throughout the life of the application without ever updating that portion of
memory.
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AT25DF021
14. Electrical Specifications
14.1 Absolute Maximum Ratings*
Temperature under Bias................................ -55C to +125C*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Storage Temperature..................................... -65C to +150C
All Input Voltages
(including NC Pins)
with Respect to Ground .....................................-0.6V to +4.1V
All Output Voltages
with Respect to Ground .............................-0.6V to VCC + 0.5V
14.2 DC and AC Operating Range
AT25DF021
(2.3V Version)
AT25DF021
(2.7V Version)
Operating Temperature (Case) Ind. -40C to 85C -40C to 85C
VCC Power Supply 2.3V to 3.6V 2.7V to 3.6V
14.3 DC Characteristics
Symbol Parameter Condition Min Typ Max Units
ISB Standby Current CS, WP, HOLD = VCC,
all inputs at CMOS levels 25 50 μA
IDPD Deep Power-down Current CS, WP, HOLD = VCC,
all inputs at CMOS levels 15 25 μA
ICC1 Active Current, Read Operation
f = 66 MHz; IOUT = 0 mA;
CS = VIL, VCC = Max 11 16
mA
f = 66 MHz; IOUT = 0 mA;
CS = VIL, VCC = Max 10 15
f = 50 MHz; IOUT = 0 mA;
CS = VIL, VCC = Max 914
f = 33 MHz; IOUT = 0 mA;
CS = VIL, VCC = Max 812
f = 20 MHz; IOUT = 0 mA;
CS = VIL, VCC = Max 710
ICC2 Active Current, Program Operation CS = VCC, VCC = Max 12 18 mA
ICC3 Active Current, Erase Operation CS = VCC, VCC = Max 14 20 mA
ILI Input Leakage Current VIN = CMOS levels 1 μA
ILO Output Leakage Current VOUT = CMOS levels 1 μA
VIL Input Low Voltage 0.3 x VCC V
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AT25DF021
VIH Input High Voltage 0.7 x VCC V
VOL Output Low Voltage IOL = 1.6 mA; VCC = Min 0.4 V
VOH Output High Voltage IOH = -100 μA; VCC = Min VCC - 0.2V V
14.4 AC Characteristics - Maximum Clock Frequencies
Symbol Parameter
AT25DF021
(2.3V Version)
AT25DF021
(2.7V Version)
UnitsMin Max Min Max
fCLK
Maximum Clock Frequency for All Operations
(excluding 03h opcode) 50 66 MHz
fRDLF
Maximum Clock Frequency for 03h Opcode
(Read Array – Low Frequency) 33 33 MHz
14.5 AC Characteristics – All Other Parameters
Symbol Parameter
AT25DF021
(2.3V Version)
AT25DF021
(2.7V Version)
UnitsMin Max Min Max
tCLKH Clock High Time 8.0 6.4 ns
tCLKL Clock Low Time 8.0 6.4 ns
tCLKR(1) Clock Rise Time, Peak-to-Peak (Slew Rate) 0.1 0.1 V/ns
tCLKF(1) Clock Fall Time, Peak-to-Peak (Slew Rate) 0.1 0.1 V/ns
tCSH Chip Select High Time 50 50 ns
tCSLS Chip Select Low Setup Time (relative to Clock) 5 5 ns
tCSLH Chip Select Low Hold Time (relative to Clock) 5 5 ns
tCSHS Chip Select High Setup Time (relative to Clock) 5 5 ns
tCSHH Chip Select High Hold Time (relative to Clock) 5 5 ns
tDS Data In Setup Time 2 2 ns
tDH Data In Hold Time 3 3 ns
tDIS(1) Output Disable Time 7 6 ns
tV(2) Output Valid Time 7 6 ns
tOH Output Hold Time 0 0 ns
tHLS HOLD Low Setup Time (relative to Clock) 5 5 ns
tHLH HOLD Low Hold Time (relative to Clock) 5 5 ns
tHHS HOLD High Setup Time (relative to Clock) 5 5 ns
tHHH HOLD High Hold Time (relative to Clock) 5 5 ns
tHLQZ(1) HOLD Low to Output High-Z 7 6 ns
tHHQX(1) HOLD High to Output Low-Z 7 6 ns
14.3 DC Characteristics (Continued)
Symbol Parameter Condition Min Typ Max Units
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AT25DF021
Notes: 1. Not 100% tested (value guaranteed by design and characterization).
2. 15 pF load at frequencies above 66 MHz, 30 pF otherwise.
3. Only applicable as a constraint for the Write Status Register command when SPRL = 1.
Note: 1. Maximum values indicate worst-case performance after 100,000 erase/program cycles.
2. Not 100% tested (value guaranteed by design and characterization).
tWPS(1)(3) Write Protect Setup Time 20 20 ns
tWPH(1)(3) Write Protect Hold Time 100 100 ns
tSECP(1) Sector Protect Time (from Chip Select High) 20 20 ns
tSECUP(1) Sector Unprotect Time (from Chip Select High) 20 20 ns
tEDPD(1) Chip Select High to Deep Power-Down 3 3 μs
tRDPD(1) Chip Select High to Standby Mode 30 30 μs
14.6 Program and Erase Characteristics
Symbol Parameter Min Typ Max Units
tPP(1) Page Program Time (256 Bytes) 1.0 5.0 ms
tBP Byte Program Time 7 μs
tBLKE(1) Block Erase Time
4 Kbytes 50 200
ms32 Kbytes 250 600
64 Kbytes 450 950
tCHPE(1)(2) Chip Erase Time 2.0 3.5 sec
tOTPP(1) OTP Security Register Program Time 200 500 μs
tWRSR(2) Write Status Register Time 200 ns
14.7 Power-up Conditions
Symbol Parameter Min Max Units
tVCSL Minimum VCC to Chip Select Low Time 1.2 ms
tPUW Power-up Device Delay Before Program or Erase Allowed 10 ms
VPOR Power-on Reset Voltage 1.5 2.2 V
14.5 AC Characteristics – All Other Parameters (Continued)
Symbol Parameter
AT25DF021
(2.3V Version)
AT25DF021
(2.7V Version)
UnitsMin Max Min Max
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AT25DF021
14.8 Input Test Waveforms and Measurement Levels
14.9 Output Test Load
AC
DRIVING
LEVELS
AC
MEASUREMENT
LEVEL
0.1VCC
VCC/2
0.9VCC
tR, tF < 2 ns (10% to 90%)
DEVICE
UNDER
TEST 15 pF (frequencies above 66 MHz)
or
30pF
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3677F–DFLASH–5/2013
AT25DF021
15. AC Waveforms
Figure 15-1. Serial Input Timing
Figure 15-2. Serial Output Timing
Figure 15-3. WP Timing for Write Status Register Command When SPRL = 1
CS
SI
SCK
SO
MSB
HIGH-IMPEDANCE
MSBLSB
tCSLS
tCLKH tCLKL tCSHS
tCSHH
tDS tDH
tCSLH
tCSH
CS
SI
SCK
SO
tV
tCLKH tCLKL tDIS
tV
tOH
WP
SI
SCK
SO
000
HIGH-IMPEDANCE
MSBX
tWPS tWPH
CS
LSB OF
WRITE STATUS REGISTER
DATA BYTE
MSB OF
WRITE STATUS REGISTER
OPCODE
MSB OF
NEXT OPCODE
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3677F–DFLASH–5/2013
AT25DF021
Figure 15-4. HOLD Timing – Serial Input
Figure 15-5. HOLD Timing – Serial Output
CS
SI
SCK
SO
tHHH tHLS
tHLH tHHS
HOLD
HIGH-IMPEDANCE
CS
SI
SCK
SO
tHHH tHLS
tHLQZ
tHLH tHHS
HOLD
tHHQX
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AT25DF021
16. Ordering Information
16.1 Ordering Code Detail
Note: The shipping carrier option code is not marked on the devices.
AT25D 0 2 SSH B1FF
Designator
Product Family
Device Density
02 = 2-megabit
Interface
1 = Serial
Package Option
SS = 8-lead, 0.150" wide SOIC
M = 8-pad 5 x 6 x 0.6 mm UDFN
Device Grade
H = Green, NiPdAu lead finish, industrial
temperature range (–40°C to +85°C)
Shipping Carrier Option
B = Bulk (tubes)
Y = Bulk (trays)
T = Tape and reel
Operating Voltage
Blank = 2.7V minimum (2.7V to 3.6V)
F = 2.3V minimum (2.3V to 3.6V)
16.2 Green Package Options (Pb/Halide-free/RoHS Compliant)
Ordering Code Package Lead Finish Operating Voltage
Max. Freq.
(MHz) Operation Range
AT25DF021-SSH-B
AT25DF021-SSH-T 8S1
NiPdAu 2.7V to 3.6V 70
Industrial
(-40°C to +85°C)
AT25DF021-MH-Y
AT25DF021-MH-T 8MA1
AT25DF021-SSHF-B
AT25DF021-SSHF-T 8S1
NiPdAu 2.3V to 3.6V 50
AT25DF021-MHF-Y
AT25DF021-MHF-T 8MA1
Package Type
8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)
8MA1 8-pad, 5 x 6 x 0.6 mm, Thermally Enhanced Ultra Thin Dual Flat No Lead Package (UDFN)
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AT25DF021
17. Packaging Information
17.1 8S1 – JEDEC SOIC
DRAWING NO. REV. TITLE GPC
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A1 0.10 0.25
A 1.35 – 1.75
b 0.31 – 0.51
C 0.17 0.25
D 4.80 5.05
E1 3.81 3.99
E 5.79 – 6.20
e 1.27 BSC
L 0.40 – 1.27
Ø
Ø
Ø
E
1
N
TOP VIEW
C
E1
END VIEW
A
b
L
A1
e
D
SIDE VIEW
Package Drawing Contact:
contact@adestotech.com
8S1 G
6/22/11
Notes: This drawing is for general information only.
Refer to JEDEC Drawing MS-012, Variation AA
for proper dimensions, tolerances, datums, etc.
8S1, 8-lead (0.150” Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC) SWB
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17.2 8MA1 – UDFN
TITLE DRAWING NO.GPC REV.
Package Drawing Contact:
contact@adestotech.com 8MA1 YFG D
8MA1, 8-pad (5 x 6 x 0.6 mm Body), Thermally
Enhanced Plastic Ultra Thin Dual Flat No Lead
Package (UDFN)
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX N O T E
A 0.45 0.55 0.60
A1 0.00 0.02 0.05
b 0.35 0.40 0.48
C 0.152 REF
D 4.90 5.00 5.10
D2 3.80 4.00 4.20
E 5.90 6.00 6.10
E2 3.20 3.40 3.60
e 1.27
L 0.50 0.60 0.75
y 0.00 0.08
K 0.20 – –
4/15/08
Pin 1 ID
TOP VIEW
E
D
A1
A
SIDE VIEW
y
C
BOTTOM VIEW
E2
D2
L
b
e
1
2
3
4
8
7
6
5
Pin #1 Notch
(0.20 R)
0.45
K
Pin #1
Cham f e r
(C 0.35)
Option A
(Option B)
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18. Revision History
Revision Level – Release Date History
A – February 2008 Initial release
B – May 2008
Changed Deep Power-Down current specifications
– Changed typical value from 4 μA to 8 μA
– Changed maximum value from 8 μA to 15 μA
Changed typical 64 KB Block Erase time from 400 ms to 450 ms
Changed typical Chip Erase time from 1.5s to 2.0s
Changed tVCSL time from 1.0 ms minimum to 1.2 ms minimum
Changed VPOR maximum from 2.5V to 2.2V
C – September 2008
Removed “Preliminary” designation from datasheet
Changed maximum clock frequency from 70 MHz to 66 MHz
Changed maximum Standby Current value from 35 μA to 50 μA
Changed Deep Power-Down Current specifications
– Changed typical value from 8 μA to 15 μA
– Changed maximum value from 15 μA to 25 μA
D – April 2009 Added System Considerations section
E – November 2012 Update to Adesto
F – May 2013 Added “Not Recommended for New Designs”. Updated logo, and
copyright date.
Corporate Office
California | USA
Adesto Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: (+1) 408.400.0578
Email: contact@adestotech.com
© 2013 Adesto Technologies. All rights reserved. / Rev.: 3677F–DFLASH–5/2013
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Company in connection with the sale of Adesto products, expressly or by implication. Adesto's products are not authorized for use as critical components in life support devices or systems.
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