1
2
3
4
8
7
6
5
R
RE
DE
D
VCC
B
A
GND
D OR P PACKAGE
(TOP VIEW)
1
2
3
46
7
A
B
R
RE
DE
D
LOGIC DIAGRAM
(POSITIVE LOGIC)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0 20 40 60 80 100 120
- Differential Output Voltage - V
DIFFERENTIAL OUTPUT VOLTAGE
vs
DIFFERENTIAL OUTPUT CURRENT
VO
IOD - Differential Output Current - mA
60 Ω Load
Line
30 Ω Load
Line
TA = 25°C
DE at VCC
D at VCC
VCC = 5 V
SN65HVD05, SN65HVD06
SN75HVD05, SN65HVD07
SN75HVD06, SN75HVD07
www.ti.com
SLLS533E –MAY 2002–REVISED AUGUST 2009
HIGH OUTPUT RS-485 TRANSCEIVERS
Check for Samples: SN65HVD05,SN65HVD06,SN75HVD05,SN65HVD07,SN75HVD06,SN75HVD07
1FEATURES DESCRIPTION
•Minimum Differential Output Voltage of 2.5 V The SN65HVD05, SN75HVD05, SN65HVD06,
Into a 54-ΩLoad SN75HVD06, SN65HVD07, and SN75HVD07
•Open-Circuit, Short-Circuit, and Idle-Bus combine a 3-state differential line driver and
Failsafe Receiver differential line receiver. They are designed for
•1/8th Unit-Load Option Available (Up to 256 balanced data transmission and interoperate with
ANSI TIA/EIA-485-A and ISO 8482E
Nodes on the Bus) standard-compliant devices. The driver is designed to
•Bus-Pin ESD Protection Exceeds 16 kV HBM provide a differential output voltage greater than that
•Driver Output Slew Rate Control Options required by these standards for increased noise
•Electrically Compatible With ANSI margin. The drivers and receivers have active-high
and active-low enables respectively, which can be
TIA/EIA-485-A Standard externally connected together to function as direction
•Low-Current Standby Mode: 1 µA Typical control.
•Glitch-Free Power-Up and Power-Down The driver differential outputs and receiver differential
Protection for Hot-Plugging Applications inputs connect internally to form a differential input/
•Pin Compatible With Industry Standard output (I/O) bus port that is designed to offer
SN75176 minimum loading to the bus whenever the driver is
disabled or not powered. These devices feature wide
APPLICATIONS positive and negative common-mode voltage ranges,
making them suitable for party-line applications.
•Data Transmission Over Long or Lossy Lines
or Electrically Noisy Environments
•Profibus Line Interface
•Industrial Process Control Networks
•Point-of-Sale (POS) Networks
•Electric Utility Metering
•Building Automation
•Digital Motor Control
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright ©2002–2009, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN65HVD05, SN65HVD06
SN75HVD05, SN65HVD07
SN75HVD06, SN75HVD07
SLLS533E –MAY 2002–REVISED AUGUST 2009
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION(1)
MARKED AS
DRIVER PLASTIC SMALL
SIGNALING UNIT OUTPUT SLOPE TAPART NUMBER(2) DUAL-IN-LINE OUTLINE
RATE LOAD CONTROL PACKAGE IC (SOIC)
(PDIP) PACKAGE
40 Mbps 1/2 No SN65HVD05D SN65HVD05P 65HVD05 VP05
10 Mbps 1/8 Yes –40°C to 85°C SN65HVD06D SN65HVD06P 65HVD06 VP06
1 Mbps 1/8 Yes SN65HVD07D SN65HVD07P 65HVD07 VP07
40 Mbps 1/2 No SN75HVD05D SN75HVD05P 75HVD05 VN05
10 Mbps 1/8 Yes 0°C to 70°C SN75HVD06D SN75HVD06P 75HVD06 VN06
1 Mbps 1/8 Yes SN75HVD07D SN75HVD07P 75HVD07 VN07
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) The D package is available taped and reeled. Add an R suffix to the device type (i.e., SN65HVD05DR).
PACKAGE DISSIPATION RATINGS
(See Figure 12 and Figure 13)TA≤25°C DERATING FACTOR(1) TA= 70°C TA= 85°C
PACKAGE POWER RATING ABOVE TA= 25°C POWER RATING POWER RATING
D(2) 710 mW 5.7 mW/°C 455 mW 369 mW
D(3) 1282 mW 10.3 mW/°C 821 mW 667 mW
P 1000 mW 8.0 m W/°C 640 mW 520 mW
(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
(2) Tested in accordance with the Low-K thermal metric definitions of EIA/JESD51-3
(3) Tested in accordance with the High-K thermal metric definitions of EIA/JESD51-7
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1) (2)
SN65HVD05, SN65HVD06, SN65HVD07
SN75HVD05, SN75HVD06, SN75HVD07
Supply voltage range, VCC –0.3 V to 6 V
Voltage range at A or B –9 V to 14 V
Input voltage range at D, DE, R or RE –0.5 V to VCC + 0.5 V
Voltage input range, transient pulse, A and B, through 100 Ω(see Figure 11)–50 V to 50 V
Receiver output current, IO–11 mA to 11mA
A, B, and GND 16 kV
Human body model(3)
Electrostatic discharge All pins 4 kV
Charged-device model(4) All pins 1 kV
Continuous total power dissipation See Dissipation Rating Table
(1) Stresses beyond those listed under "absolute maximum ratings”may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under"recommended operating
conditions”is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
(3) Tested in accordance with JEDEC Standard 22, Test Method A114-A.
(4) Tested in accordance with JEDEC Standard 22, Test Method C101.
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Product Folder Link(s): SN65HVD05 SN65HVD06 SN75HVD05 SN65HVD07 SN75HVD06 SN75HVD07
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SN75HVD05, SN65HVD07
SN75HVD06, SN75HVD07
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SLLS533E –MAY 2002–REVISED AUGUST 2009
RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT
Supply voltage, VCC 4.5 5.5 V
Voltage at any bus terminal (separately or common mode) VIor VIC –7(1) 12 V
High-level input voltage, VIH D, DE, RE 2 V
Low-level input voltage, VIL D, DE, RE 0.8 V
Differential input voltage, VID (see Figure 7)–12 12 V
Driver –100
High-level output current, IOH mA
Receiver –8
Driver 100
Low-level output current, IOL mA
Receiver 8
SN65HVD05
SN65HVD06 –40 85 °C
SN65HVD07
Operating free-air temperature, TASN75HVD05
SN75HVD06 0 70 °C
SN75HVD07
(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
DRIVER ELECTRICAL CHARACTERISTICS
over operating free-air temperature range unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
VIK Input clamp voltage II=–18 mA –1.5 V
No Load VCC
|VOD| Differential output voltage RL= 54 Ω, See Figure 4 2.5 V
Vtest =–7 V to 12 V, See Figure 2 2.2
Change in magnitude of differential output
Δ|VOD| See Figure 4 and Figure 2 –0.2 0.2 V
voltage
VOC(SS) Steady-state common-mode output voltage 2.2 3.3 V
See Figure 3
Change in steady-state common-mode
ΔVOC(SS) –0.1 0.1 V
output voltage HVD05 600
Peak-to-peak common-mode
VOC(PP) HVD06 See Figure 3 500 mV
output voltage HVD07 900
IOZ High-impedance output current See receiver input currents
D–100 0
IIInput current μA
DE 0 100
IOS Short-circuit output current –7 V ≤VO≤12 V –250 250 mA
C(diff) Differential output capacitance VID = 0.4 sin (4E6πt) + 0.5 V, DE at 0 V 16 pF
RE at VCC,Receiver disabled
D and DE at VCC, 9 15 mA
and driver enabled
No load
RE at VCC, Receiver disabled
ICC Supply current D at VCC DE at 0 V, and driver disabled 1 5 μA
No load (standby)
RE at 0 V, Receiver enabled
D and DE at VCC, 9 15 mA
and driver enabled
No load
(1) All typical values are at 25°C and with a 5-V supply.
Copyright ©2002–2009, Texas Instruments Incorporated Submit Documentation Feedback 3
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SN65HVD05, SN65HVD06
SN75HVD05, SN65HVD07
SN75HVD06, SN75HVD07
SLLS533E –MAY 2002–REVISED AUGUST 2009
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DRIVER SWITCHING CHARACTERISTICS
over operating free-air temperature range unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
HVD05 6.5 11
tPLH Propagation delay time, low-to-high-level output HVD06 27 40 ns
HVD07 250 400
HVD05 6.5 11
tPHL Propagation delay time, high-to-low-level output HVD06 27 40 ns
HVD07 250 400
HVD05 2.7 3.6 6
trDifferential output signal rise time HVD06 18 28 55 ns
HVD07 150 300 450
RL= 54 Ω, CL= 50 pF,
See Figure 4
HVD05 2.7 3.6 6
tfDifferential output signal fall time HVD06 18 28 55 ns
HVD07 150 300 450
HVD05 2
tsk(p) Pulse skew (|tPHL - tPLH|) HVD06 2.5 ns
HVD07 10
HVD05 3.5
tsk(pp) (2) Part-to-part skew HVD06 14 ns
HVD07 100
HVD05 25
Propagation delay time,
tPZH1 HVD06 45 ns
high-impedance-to-high-level output HVD07 250
RE at 0 V, RL= 110 Ω,
See Figure 5
HVD05 25
Propagation delay time,
tPHZ HVD06 60 ns
high-level-to-high-impedance output HVD07 250
HVD05 15
Propagation delay time, high-impedance-to-low-level
tPZL1 HVD06 45 ns
output HVD07 200
RE at 0 V, RL= 110 Ω,
See Figure 6
HVD05 14
Propagation delay time, low-level-to-high-impedance
tPLZ HVD06 90 ns
output HVD07 550
RL= 110Ω, RE at 3 V,
tPZH2 Propagation delay time, standby-to-high-level output 6 μs
See Figure 5
RL= 110 Ω, RE at 3 V,
tPZL2 Propagation delay time, standby-to-low-level output 6 μs
See Figure 6
(1) All typical values are at 25°C and with a 5-V supply.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
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Product Folder Link(s): SN65HVD05 SN65HVD06 SN75HVD05 SN65HVD07 SN75HVD06 SN75HVD07
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SN75HVD05, SN65HVD07
SN75HVD06, SN75HVD07
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SLLS533E –MAY 2002–REVISED AUGUST 2009
RECEIVER ELECTRICAL CHARACTERISTICS
over operating free-air temperature range unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
Positive-going input
VIT+ IO=–8 mA –0.01
threshold voltage V
Negative-going input
VIT- IO= 8 mA –0.2
threshold voltage
Hysteresis voltage
Vhys 35 mV
(VIT+ - VIT-)
VIK Enable-input clamp voltage II=–18 mA –1.5 V
VOH High-level output voltage VID = 200 mV, IOH =–8 mA, See Figure 7 4 V
VOL Low-level output voltage VID = -200 mV, IOL = 8 mA, See Figure 7 0.4 V
High-impedance-state
IOZ VO= 0 or VCC RE at VCC –1 1 μA
output current VAor VB= 12 V 0.23 0.5
VAor VB= 12 V, VCC = 0 V 0.3 0.5
HVD05 Other inputat 0 V mA
VAor VB=–7 V –0.4 0.13
VAor VB=–7 V, VCC = 0 V –0.4 0.15
IIBus input current VAor VB= 12 V 0.06 0.1
VAor VB= 12 V, VCC = 0 V 0.08 0.13
HVD06 Other inputat 0 V mA
HVD07 VAor VB=–7 V –0.1 0.05
VAor VB=–7 V, VCC = 0 V –0.05 0.03
High-level input current,
IIH VIH = 2 V –60 26.4 μA
RE
IIL Low-level input current, RE VIL = 0.8 V –60 27.4 μA
Differential input
C(diff) VI= 0.4 sin (4E6πt) + 0.5 V, DE at 0 V 16 pF
capacitance RE at 0 V, D and DE at Receiver enabled and driver disabled 5 10 mA
0 V, No load
RE at VCC, DE at 0 V, Receiver disabled and driver disabled 1 5 μA
ICC Supply current D at VCC, No load (standby)
RE at 0 V,
D and DE at VCC, Receiver enabled and driver enabled 9 15 mA
No load
(1) All typical values are at 25°C and with a 5-V supply.
Copyright ©2002–2009, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): SN65HVD05 SN65HVD06 SN75HVD05 SN65HVD07 SN75HVD06 SN75HVD07
IOA
VOD 54 Ω ±1%
0 or 3 V
VOA
VOB
IOB
DE
VCC
II
VI
A
B
60 Ω ±1%
VOD
0 or 3 V
_
+-7 V < V(test)
< 12 V
DE
VCC
A
B
D
375 Ω ±1%
375 Ω ±1%
SN65HVD05, SN65HVD06
SN75HVD05, SN65HVD07
SN75HVD06, SN75HVD07
SLLS533E –MAY 2002–REVISED AUGUST 2009
www.ti.com
RECEIVER SWITCHING CHARACTERISTICS
over operating free-air temperature range unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
tPLH Propagation delay time, low-to-high-level output 1/2 UL HVD05 14.6 25 ns
tPHL Propagation delay time, high-to-low-level output 1/2 UL HVD05 14.6 25 ns
HVD06 55 70
tPLH Propagation delay time, low-to-high-level output 1/8 UL ns
HVD07 55 70
HVD06 55 70
tPHL Propagation delay time, high-to-low-level output 1/8 UL ns
VID =–1.5 V to 1.5 V,
HVD07 55 70
CL= 15 pF,
HVD05 2
See Figure 8
tsk(p) Pulse skew (|tPHL –tPLH|) HVD06 4.5 ns
HVD07 4.5
HVD05 6.5
tsk(pp) (2) Part-to-part skew HVD06 14 ns
HVD07 14
trOutput signal rise time 2 3
CL= 15 pF, ns
See Figure 8
tfOutput signal fall time 2 3
tPZH1 Output enable time to high level 10
CL= 15 pF,
tPZL1 Output enable time to low level 10
DE at 3 V, ns
tPHZ Output disable time from high level 15
See Figure 9
tPLZ Output disable time from low level 15
tPZH2 Propagation delay time, standby-to-high-level output 6
CL= 15 pF, DE at 0, μs
See Figure 10
tPZL2 Propagation delay time, standby-to-low-level output 6
(1) All typical values are at 25°C and with a 5-V supply.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
PARAMETER MEASUREMENT INFORMATION
Figure 1. Driver VOD Test Circuit and Voltage and Current Definitions
Figure 2. Driver VOD With Common-Mode Loading Test Circuit
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Product Folder Link(s): SN65HVD05 SN65HVD06 SN75HVD05 SN65HVD07 SN75HVD06 SN75HVD07
VOC
27 Ω ± 1%
Input
A
B
VA
VB
VOC(PP) ∆VOC(SS)
VOC
27 Ω ± 1%
CL = 50 pF ±20%
DA
B
DE
VCC
Input: PRR = 500 kHz, 50% Duty Cycle,tr<6ns, tf<6ns, ZO = 50 Ω
CL Includes Fixture and
Instrumentation Capacitance
VOD
RL = 54 Ω
± 1%
50 Ω
Generator: PRR = 500 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω
tPLH tPHL
1.5 V 1.5 V
3 V
≈ 2 V
≈ –2 V
90%
10%
0 V
VI
VOD
trtf
CL = 50 pF ±20%
CL Includes Fixture
and Instrumentation
Capacitance
DA
B
DE
VCC
VI
Input
Generator 90% 0 V
10%
0 V
RL = 110 Ω
± 1%
Input
Generator 50 Ω
Generator: PRR = 100 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω
3 V S1
0.5 V
3 V
0 V
VOH
≈ 0 V
tPHZ
tPZH(1 & 2)
1.5 V 1.5 V
VI
VO
CL = 50 pF ±20%
CL Includes Fixture
and Instrumentation
Capacitance
DA
B
DE
VO
VI
2.3 V
SN65HVD05, SN65HVD06
SN75HVD05, SN65HVD07
SN75HVD06, SN75HVD07
www.ti.com
SLLS533E –MAY 2002–REVISED AUGUST 2009
Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
Figure 4. Driver Switching Test Circuit and Voltage Waveforms
Figure 5. Driver High-Level Enable and Disable Time Test Circuit and Voltage Waveforms
Figure 6. Driver Low-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms
Copyright ©2002–2009, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): SN65HVD05 SN65HVD06 SN75HVD05 SN65HVD07 SN75HVD06 SN75HVD07
VID
VA
VB
IO
A
B
IBVO
R
IA
VIC
VA + VB
2
Input
Generator 50 Ω
Generator: PRR = 100 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω
VO
1.5 V
0 V
1.5 V 1.5 V
3 V
VOH
VOL
1.5 V
10%
1.5 V
tPLH tPHL
trtf
90%
VI
VO
CL = 15 pF ±20%
CL Includes Fixture
and Instrumentation
Capacitance
A
B
RE
VI
R
0 V
90%
10%
SN65HVD05, SN65HVD06
SN75HVD05, SN65HVD07
SN75HVD06, SN75HVD07
SLLS533E –MAY 2002–REVISED AUGUST 2009
www.ti.com
Figure 7. Receiver Voltage and Current Definitions
Figure 8. Receiver Switching Test Circuit and Voltage Waveforms
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50 Ω
Generator: PRR = 100 kHz,
50% Duty Cycle,
tr <6 ns, tf <6 ns, Zo = 50 Ω
VO
RE
VCC
0 V or 3 V
1.5 V 1.5 V
tPZH(1) tPHZ
1.5 V VOH –0.5 V
3 V
0 V
VOH
≈ 0 V
VO
CL = 15 pF ±20%
CL Includes Fixture and
Instrumentation Capacitance
VI
DE
D
1 kΩ ± 1%
VI
A
B
S1
D at 3 V
S1 to B
tPZL(1) tPLZ
1.5 V VOL +0.5 V VOL
VO
D at 0 V
S1 to A
Input
Generator
R
3 V
A
B
VCC
SN65HVD05, SN65HVD06
SN75HVD05, SN65HVD07
SN75HVD06, SN75HVD07
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SLLS533E –MAY 2002–REVISED AUGUST 2009
Figure 9. Receiver Enable and Disable Time Test Circuit and Voltage Waveforms With Drivers Enabled
Copyright ©2002–2009, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s): SN65HVD05 SN65HVD06 SN75HVD05 SN65HVD07 SN75HVD06 SN75HVD07
1.5 V
tPZH(2)
1.5 V
3 V
0 V
VOH
GND
VI
VO
0 V or 1.5 V
1.5 V or 0 V
A at 1.5 V
B at 0 V
S1 to B
tPZL(2)
1.5 V
VOL
VO
A at 0 V
B at 1.5 V
S1 to A
50 Ω
Generator: PRR = 100 kHz,
50% Duty Cycle,
tr <6 ns, tf <6 ns, Zo = 50 Ω
VO
RE
CL = 15 pF ±20%
CL Includes Fixture and
Instrumentation Capacitance
VI
DE
1 kΩ ± 1%
A
B
S1
Input
Generator
R
0 V
A
B
VCC
VCC
Pulse Generator,
15 µs Duration,
1% Duty Cycle
tr, tf ≤ 100 ns
100 Ω
± 1%
_
+
A
BR
D
DE
RE
0 V or 3 V
NOTE: This test is conducted to test survivability only. Data stability at the R output is not specified.
3 V or 0 V
SN65HVD05, SN65HVD06
SN75HVD05, SN65HVD07
SN75HVD06, SN75HVD07
SLLS533E –MAY 2002–REVISED AUGUST 2009
www.ti.com
Figure 10. Receiver Enable Time From Standby (Driver Disabled)
Figure 11. Test Circuit, Transient Over Voltage Test
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Product Folder Link(s): SN65HVD05 SN65HVD06 SN75HVD05 SN65HVD07 SN75HVD06 SN75HVD07
SN65HVD05, SN65HVD06
SN75HVD05, SN65HVD07
SN75HVD06, SN75HVD07
www.ti.com
SLLS533E –MAY 2002–REVISED AUGUST 2009
FUNCTION TABLES
Table 1. DRIVER
INPUT ENABLE OUTPUTS
D DE A B
H H H L
L H L H
X L Z Z
Open H H L
X Open Z Z
Table 2. RECEIVER(1)
DIFFERENTIAL INPUTS ENABLE OUTPUT
VID = VA–VBRE R
VID ≤ –0.2 V L L
–0.2 V <VID < –0.01 V L ?
–0.01 V≤VID L H
X H Z
Open Circuit L H
Short Circuit L H
IDLE Bus L H
X Open Z
(1) H = high level; L = low level; Z = high impedance; X = irrelevant;
? = indeterminate
Receiver Failsafe
The differential receiver is “failsafe”to invalid bus states caused by:
•open bus conditions such as a disconnected connector,
•shorted bus conditions such as cable damage shorting the twisted-pair together, or
•idle bus conditions that occur when no driver on the bus is actively driving
In any of these cases, the differential receiver outputs a failsafe logic High state, so that the output of the
receiver is not indeterminate.
Receiver failsafe is accomplished by offsetting the receiver thresholds so that the “input indeterminate”range
does not include zero volts differential. To comply with the RS-422 and RS-485 standards, the receiver output
must output a High when the differential input VID is more positive than +200 mV, and must output a Low when
the VID is more negative than -200 mV. The receiver parameters which determine the failsafe performance are
VIT+ and VIT- and VHYS. As seen in the Receiver Electrical Characteristics table, differential signals more negative
than -200 mV will always cause a Low receiver output. Similarly, differential signals more positive than +200 mV
will always cause a High receiver output.
When the differential input signal is close to zero, it will still be above the VIT+ threshold, and the receiver output
is High. Only when the differential input is more negative than VIT- will the receiver output transition to a Low
state. So, the noise immunity of the receiver inputs during a bus fault condition includes the receiver hysteresis
value VHYS (the separation between VIT+ and VIT- ) as well as the value of VIT+.
Copyright ©2002–2009, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s): SN65HVD05 SN65HVD06 SN75HVD05 SN65HVD07 SN75HVD06 SN75HVD07
9 V
1 kΩ
100 kΩ
Input
VCC
D and RE Inputs
9 V
1 kΩ
100 kΩ
Input
VCC
DE Input
16 V
16 V
100 kΩR3 R1
R2
Input
A Input
16 V
16 V
100 kΩ
R3 R1
R2
Input
B Input
16 V
16 V
VCC
A and B Outputs
9 V
VCC
R Output
5 ΩOutput
VCC
SN65HVD05
SN65HVD06
SN65HVD07
R1/R2
9 kΩ
36 kΩ
36 kΩ
R3
45 kΩ
180 kΩ
180 kΩ
VCC
Output
SN65HVD05, SN65HVD06
SN75HVD05, SN65HVD07
SN75HVD06, SN75HVD07
SLLS533E –MAY 2002–REVISED AUGUST 2009
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EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
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ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
85
25
1 10 40
Maximum Recommended Still-Air
Operating Temperature - TA(°C
Signaling Rate - Mbps
)
High K Board
Low K Board
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
85
25
1 10
Maximum Recommended Still-Air
Operating Temperature - TA
Signaling Rate - Mbps
(°C)
High K Board
Low K Board
30
40
50
60
70
80
90
100
110
120
0 5 10 15 20 25 30 35 40
ICC- RMS Supply Current - mA
TA = 25°C
RE at VCC
DE at VCC
RL = 54 Ω
CL = 50 pF
VCC = 5 V
Signaling Rate - Mbps
40
60
80
100
120
0 2.5 5 7.5 10
Signaling Rate - Mbps
ICC- RMS Supply Current - mA
TA = 25°C
RE at VCC
DE at VCC
RL = 54 Ω
CL = 50 pF
VCC = 5 V
SN65HVD05, SN65HVD06
SN75HVD05, SN65HVD07
SN75HVD06, SN75HVD07
www.ti.com
SLLS533E –MAY 2002–REVISED AUGUST 2009
TYPICAL CHARACTERISTICS
HVD05 HVD06
MAXIMUM RECOMMENDED STILL-AIR MAXIMUM RECOMMENDED STILL-AIR
OPERATING TEMPERATURE OPERATING TEMPERATURE
vs vs
SIGNALING RATE SIGNALING RATE
(D-PACKAGE) (D-PACKAGE)
Figure 12. Figure 13.
HVD05 HVD06
RMS SUPPLY CURRENT RMS SUPPLY CURRENT
vs vs
SIGNALILNG RATE SIGNALING RATE
Figure 14. Figure 15.
Copyright ©2002–2009, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): SN65HVD05 SN65HVD06 SN75HVD05 SN65HVD07 SN75HVD06 SN75HVD07
40
50
60
70
80
90
100
110
100 400 700 1000
ICC- RMS Supply Current - mA
TA = 25°C
RE at VCC
DE at VCC
RL = 54 Ω
CL = 50 pF
VCC = 5 V
Signaling Rate - kbps
-7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 9 1011 12
- Bus Input Current -IIAµ
VI - Bus Input Voltage - V
TA = 25°C
DE at 0 V
VCC = 5 V
-200
-150
-100
-50
0
50
100
150
200
250
HVD05
HVD06
HVD07
-160
-140
-120
-100
-80
-60
-40
-20
0
0 0.5 1 1.5 2 4.52.5 3 3.5 4
- Driver High-Level Output Current - mA
IOH
VO - High-Level Output Voltage - V 5
TA = 25°C
DE at VCC
D at VCC
VCC = 5 V
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
- Driver Low-Level Output Current - mA
IOL
VO - Low-Level Output Voltage - V
0
20
40
60
80
100
120
140
160 TA = 25°C
DE at VCC
D at 0 V
VCC = 5 V
SN65HVD05, SN65HVD06
SN75HVD05, SN65HVD07
SN75HVD06, SN75HVD07
SLLS533E –MAY 2002–REVISED AUGUST 2009
www.ti.com
TYPICAL CHARACTERISTICS (continued)
HVD07
RMS SUPPLY CURRENT BUS INPUT CURRENT
vs vs
SIGNALING RATE BUS INPUT VOLTAGE
Figure 16. Figure 17.
DRIVER HIGH-LEVEL OUTPUT CURRENT DRIVER LOW-LEVEL OUTPUT CURRENT
vs vs
HIGH-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE
Figure 18. Figure 19.
14 Submit Documentation Feedback Copyright ©2002–2009, Texas Instruments Incorporated
Product Folder Link(s): SN65HVD05 SN65HVD06 SN75HVD05 SN65HVD07 SN75HVD06 SN75HVD07
0 0.6 1.2 1.8 2.4 3 3.6 4.2 4.8 5.4
0
10
20
30
40
50
60
70
IO- Driver Output Current - mA
VCC - Supply V oltage - V
TA = 25°C
DE at VCC
D at VCC
RL = 54 Ω
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8
4
-40 -15 10 35 60 85
VOD- Differential Output V oltage - V
TA - Free-Air Temperature - °C
DE at VCC
D at VCC
VCC = 5 V
RL = 54 Ω
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0 20 40 60 80 100 120
- Differential Output Voltage - VVO
IOD - Differential Output Current - mA
60 Ω Load
Line
30 Ω Load
Line
TA = 25°C
DE at VCC
D at VCC
VCC = 5 V
0
100
400
500
600
-7 -2 3 8 13
HVD06
EnableTime − ns
V −
(TEST) Common-ModeVoltage − V
200
300
HVD07
HVD5
SN65HVD05, SN65HVD06
SN75HVD05, SN65HVD07
SN75HVD06, SN75HVD07
www.ti.com
SLLS533E –MAY 2002–REVISED AUGUST 2009
TYPICAL CHARACTERISTICS (continued)
DIFFERENTIAL OUTPUT VOLTAGE DRIVER OUTPUT CURRENT
vs vs
FREE-AIR TEMPERATURE SUPPLY VOLTAGE
Figure 20. Figure 21.
DIFFERENTIAL OUTPUT VOLTAGE ENABLE TIME
vs vs
DIFFERENTIAL OUTPUT CURRENT COMMON-MODE VOLTAGE (SEE Figure 24)
Figure 22. Figure 23.
Copyright ©2002–2009, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): SN65HVD05 SN65HVD06 SN75HVD05 SN65HVD07 SN75HVD06 SN75HVD07
60 W
1%±
50 W
375 W1%±
-7V<V <12V
(TEST)
VOD
V (low)
OD
t (diff)
pZL
t (diff)
pZH
V
0or3V
375 W1%±
50%
0V
1.5V
D
Z
DE
Y
-1.5V
V (high)
OD
Input
Generator
SN65HVD05, SN65HVD06
SN75HVD05, SN65HVD07
SN75HVD06, SN75HVD07
SLLS533E –MAY 2002–REVISED AUGUST 2009
www.ti.com
TYPICAL CHARACTERISTICS (continued)
Figure 24. Driver Enable Time From DE to VOD
The time tpZL(x) is the measure from DE to VOD(x). VOD is valid when it is greater than 1.5 V.
16 Submit Documentation Feedback Copyright ©2002–2009, Texas Instruments Incorporated
Product Folder Link(s): SN65HVD05 SN65HVD06 SN75HVD05 SN65HVD07 SN75HVD06 SN75HVD07
RTRT
Device
HVD05
HVD06
HVD07
Number of Devices on Bus
64
256
256
NOTE: The line should be terminated at both ends with its characteristic impedance (RT = ZO).
Stub lengths off the main line should be kept as short as possible.
SN65HVD05, SN65HVD06
SN75HVD05, SN65HVD07
SN75HVD06, SN75HVD07
www.ti.com
SLLS533E –MAY 2002–REVISED AUGUST 2009
APPLICATION INFORMATION
Figure 25. Typical Application Circuit
REVISION HISTORY
Changes from Revision D (July 2006) to Revision E Page
•Added IDLE Bus to the Receivers Function Table ............................................................................................................. 11
•Added the Receiver Failsafe paragraph. ............................................................................................................................ 11
Copyright ©2002–2009, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): SN65HVD05 SN65HVD06 SN75HVD05 SN65HVD07 SN75HVD06 SN75HVD07
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SN65HVD05D ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD05DG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD05DR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD05DRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD05P ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN65HVD05PE4 ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN65HVD06D ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD06DG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD06DR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD06DRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD06P ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN65HVD06PE4 ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN65HVD07D ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD07DG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD07DR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD07DRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD07P ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN65HVD07PE4 ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN75HVD05D ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75HVD05DG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75HVD05P ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN75HVD05PE4 ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN75HVD06D ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75HVD06DG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75HVD06DR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 27-Aug-2009
Addendum-Page 1
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SN75HVD06DRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75HVD06P ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN75HVD06PE4 ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN75HVD07D ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75HVD07DG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75HVD07DR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75HVD07DRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75HVD07P ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN75HVD07PE4 ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 27-Aug-2009
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN65HVD05DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN65HVD06DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN65HVD07DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN75HVD06DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN75HVD07DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 13-Aug-2009
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN65HVD05DR SOIC D 8 2500 340.5 338.1 20.6
SN65HVD06DR SOIC D 8 2500 340.5 338.1 20.6
SN65HVD07DR SOIC D 8 2500 340.5 338.1 20.6
SN75HVD06DR SOIC D 8 2500 340.5 338.1 20.6
SN75HVD07DR SOIC D 8 2500 340.5 338.1 20.6
PACKAGE MATERIALS INFORMATION
www.ti.com 13-Aug-2009
Pack Materials-Page 2
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